diff options
| author | Paul Mackerras <paulus@samba.org> | 2006-02-07 10:43:36 +1100 |
|---|---|---|
| committer | Paul Mackerras <paulus@samba.org> | 2006-02-07 10:43:36 +1100 |
| commit | 6cb6524d90b6e5497e79a1474bdb2f26755d1c02 (patch) | |
| tree | fd475ac8f57a6bd39c976056324d1bc79d11b4c9 /arch/arm/mm/proc-xscale.S | |
| parent | 837e9594fc3cb9a06bddd7ecf66151334a2e13d2 (diff) | |
| parent | 410c05427a69f53851637ccb85c2212131409fbd (diff) | |
Merge ../linux-2.6
Diffstat (limited to 'arch/arm/mm/proc-xscale.S')
| -rw-r--r-- | arch/arm/mm/proc-xscale.S | 16 |
1 files changed, 11 insertions, 5 deletions
diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S index 861b3594728..2d3823ec315 100644 --- a/arch/arm/mm/proc-xscale.S +++ b/arch/arm/mm/proc-xscale.S @@ -241,7 +241,15 @@ ENTRY(xscale_flush_user_cache_range) * it also trashes the mini I-cache used by JTAG debuggers. */ ENTRY(xscale_coherent_kern_range) - /* FALLTHROUGH */ + bic r0, r0, #CACHELINESIZE - 1 +1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry + add r0, r0, #CACHELINESIZE + cmp r0, r1 + blo 1b + mov r0, #0 + mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB + mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer + mov pc, lr /* * coherent_user_range(start, end) @@ -252,18 +260,16 @@ ENTRY(xscale_coherent_kern_range) * * - start - virtual start address * - end - virtual end address - * - * Note: single I-cache line invalidation isn't used here since - * it also trashes the mini I-cache used by JTAG debuggers. */ ENTRY(xscale_coherent_user_range) bic r0, r0, #CACHELINESIZE - 1 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry + mcr p15, 0, r0, c7, c5, 1 @ Invalidate I cache entry add r0, r0, #CACHELINESIZE cmp r0, r1 blo 1b mov r0, #0 - mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB + mcr p15, 0, r0, c7, c5, 6 @ Invalidate BTB mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer mov pc, lr |