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| author | Dan Williams <dan.j.williams@intel.com> | 2009-09-08 14:32:24 -0700 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2009-09-08 14:32:24 -0700 |
| commit | a348a7e6fdbcd2d5192a09719a479bb238fde727 (patch) | |
| tree | 5ff94185f4e5a810777469d7fe7832a8ec2d3430 /arch/arm/vfp/vfphw.S | |
| parent | 808347f6a31792079e345ec865e9cfcb6e8ae6b2 (diff) | |
| parent | 28d0325ce6e0a52f53d8af687e6427fee59004d3 (diff) | |
Merge commit 'v2.6.31-rc1' into dmaengine
Diffstat (limited to 'arch/arm/vfp/vfphw.S')
| -rw-r--r-- | arch/arm/vfp/vfphw.S | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/vfp/vfphw.S b/arch/arm/vfp/vfphw.S index 83c4e384b16..1aeae38725d 100644 --- a/arch/arm/vfp/vfphw.S +++ b/arch/arm/vfp/vfphw.S @@ -100,6 +100,7 @@ ENTRY(vfp_support_entry) beq no_old_VFP_process VFPFSTMIA r4, r5 @ save the working registers VFPFMRX r5, FPSCR @ current status +#ifndef CONFIG_CPU_FEROCEON tst r1, #FPEXC_EX @ is there additional state to save? beq 1f VFPFMRX r6, FPINST @ FPINST (only if FPEXC.EX is set) @@ -107,6 +108,7 @@ ENTRY(vfp_support_entry) beq 1f VFPFMRX r8, FPINST2 @ FPINST2 if needed (and present) 1: +#endif stmia r4, {r1, r5, r6, r8} @ save FPEXC, FPSCR, FPINST, FPINST2 @ and point r4 at the word at the @ start of the register dump @@ -119,6 +121,7 @@ no_old_VFP_process: VFPFLDMIA r10, r5 @ reload the working registers while @ FPEXC is in a safe state ldmia r10, {r1, r5, r6, r8} @ load FPEXC, FPSCR, FPINST, FPINST2 +#ifndef CONFIG_CPU_FEROCEON tst r1, #FPEXC_EX @ is there additional state to restore? beq 1f VFPFMXR FPINST, r6 @ restore FPINST (only if FPEXC.EX is set) @@ -126,6 +129,7 @@ no_old_VFP_process: beq 1f VFPFMXR FPINST2, r8 @ FPINST2 if needed (and present) 1: +#endif VFPFMXR FPSCR, r5 @ restore status check_for_exception: |