diff options
| author | Ben Dooks <ben@simtec.co.uk> | 2009-02-25 00:41:14 +0000 |
|---|---|---|
| committer | Andy Green <agreen@octopus.localdomain> | 2009-02-25 00:41:14 +0000 |
| commit | 05225d2426dd3cf614a642741fe7f0c5ad7702fa (patch) | |
| tree | 73c8070b73a77f5fc0b4c38f976759f4810d0dc0 /arch/arm | |
| parent | 932d271ee092dbcd21e6e35a87c7dd8a225700d6 (diff) | |
S3C64XX: Fix HCLK_GATE bit definitions
Fix the definitions of HCLK_GATE bits, which
had SDMA0/1 named SDMA1/2 and the definitions
of bits 26..29 in the wrong order.
Signed-off-by: Ben Dooks <ben@simtec.co.uk>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/plat-s3c64xx/include/plat/regs-clock.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-clock.h b/arch/arm/plat-s3c64xx/include/plat/regs-clock.h index 52836d41e33..0aefe3b9993 100644 --- a/arch/arm/plat-s3c64xx/include/plat/regs-clock.h +++ b/arch/arm/plat-s3c64xx/include/plat/regs-clock.h @@ -89,10 +89,10 @@ /* HCLK GATE Registers */ #define S3C_CLKCON_HCLK_BUS (1<<30) -#define S3C_CLKCON_HCLK_SECUR (1<<29) -#define S3C_CLKCON_HCLK_SDMA1 (1<<28) -#define S3C_CLKCON_HCLK_SDMA2 (1<<27) -#define S3C_CLKCON_HCLK_UHOST (1<<26) +#define S3C_CLKCON_HCLK_UHOST (1<<29) +#define S3C_CLKCON_HCLK_SECUR (1<<28) +#define S3C_CLKCON_HCLK_SDMA1 (1<<27) +#define S3C_CLKCON_HCLK_SDMA0 (1<<26) #define S3C_CLKCON_HCLK_IROM (1<<25) #define S3C_CLKCON_HCLK_DDR1 (1<<24) #define S3C_CLKCON_HCLK_DDR0 (1<<23) |