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authorBen Dooks <ben-linux@fluff.org>2010-01-19 18:36:12 +0900
committerBen Dooks <ben-linux@fluff.org>2010-01-19 18:36:12 +0900
commitea2de1dc8b5872de21a03757dca9d1560b5c9a81 (patch)
tree5501528ce36e2cbfff47ea5ffb1398f5d98ff330 /arch/arm
parent668dfc7527eb755e1bf194bf19c0c281e9df6deb (diff)
parentf9e011b6b305d38445bbd4a1e7a8814e056de37b (diff)
ARM: Merge next-samsung-clock2
Merge branch 'next-samsung-clock2' into next-samsung-try7
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/plat-s5pc1xx/clock.c9
-rw-r--r--arch/arm/plat-samsung/clock-clksrc.c25
2 files changed, 19 insertions, 15 deletions
diff --git a/arch/arm/plat-s5pc1xx/clock.c b/arch/arm/plat-s5pc1xx/clock.c
index aec0305174a..387f23190c3 100644
--- a/arch/arm/plat-s5pc1xx/clock.c
+++ b/arch/arm/plat-s5pc1xx/clock.c
@@ -64,18 +64,12 @@ struct clk clk_54m = {
.rate = 54000000,
};
-static int clk_dummy_enable(struct clk *clk, int enable)
-{
- return 0;
-}
-
struct clk clk_hd0 = {
.name = "hclkd0",
.id = -1,
.rate = 0,
.parent = NULL,
.ctrlbit = 0,
- .enable = clk_dummy_enable,
.ops = &clk_ops_def_setrate,
};
@@ -86,7 +80,6 @@ struct clk clk_pd0 = {
.parent = NULL,
.ctrlbit = 0,
.ops = &clk_ops_def_setrate,
- .enable = clk_dummy_enable,
};
static int s5pc1xx_clk_gate(void __iomem *reg, struct clk *clk, int enable)
@@ -680,6 +673,8 @@ static struct clk s5pc100_init_clocks[] = {
static struct clk *clks[] __initdata = {
&clk_ext,
&clk_epll,
+ &clk_pd0,
+ &clk_hd0,
&clk_27m,
&clk_48m,
&clk_54m,
diff --git a/arch/arm/plat-samsung/clock-clksrc.c b/arch/arm/plat-samsung/clock-clksrc.c
index 33c633a8be8..ae8b8507663 100644
--- a/arch/arm/plat-samsung/clock-clksrc.c
+++ b/arch/arm/plat-samsung/clock-clksrc.c
@@ -60,7 +60,7 @@ static int s3c_setrate_clksrc(struct clk *clk, unsigned long rate)
rate = clk_round_rate(clk, rate);
div = clk_get_rate(clk->parent) / rate;
- if (div > 16)
+ if (div > (1 << sclk->reg_div.size))
return -EINVAL;
val = __raw_readl(reg);
@@ -102,7 +102,9 @@ static int s3c_setparent_clksrc(struct clk *clk, struct clk *parent)
static unsigned long s3c_roundrate_clksrc(struct clk *clk,
unsigned long rate)
{
+ struct clksrc_clk *sclk = to_clksrc(clk);
unsigned long parent_rate = clk_get_rate(clk->parent);
+ int max_div = 1 << sclk->reg_div.size;
int div;
if (rate >= parent_rate)
@@ -114,8 +116,8 @@ static unsigned long s3c_roundrate_clksrc(struct clk *clk,
if (div == 0)
div = 1;
- if (div > 16)
- div = 16;
+ if (div > max_div)
+ div = max_div;
rate = parent_rate / div;
}
@@ -129,11 +131,16 @@ void __init_or_cpufreq s3c_set_clksrc(struct clksrc_clk *clk, bool announce)
{
struct clksrc_sources *srcs = clk->sources;
u32 mask = bit_mask(clk->reg_src.shift, clk->reg_src.size);
- u32 clksrc = 0;
+ u32 clksrc;
- if (clk->reg_src.reg)
- clksrc = __raw_readl(clk->reg_src.reg);
+ if (!clk->reg_src.reg) {
+ if (!clk->clk.parent)
+ printk(KERN_ERR "%s: no parent clock specified\n",
+ clk->clk.name);
+ return;
+ }
+ clksrc = __raw_readl(clk->reg_src.reg);
clksrc &= mask;
clksrc >>= clk->reg_src.shift;
@@ -172,9 +179,11 @@ void __init s3c_register_clksrc(struct clksrc_clk *clksrc, int size)
{
int ret;
- WARN_ON(!clksrc->reg_div.reg && !clksrc->reg_src.reg);
-
for (; size > 0; size--, clksrc++) {
+ if (!clksrc->reg_div.reg && !clksrc->reg_src.reg)
+ printk(KERN_ERR "%s: clock %s has no registers set\n",
+ __func__, clksrc->clk.name);
+
/* fill in the default functions */
if (!clksrc->clk.ops) {