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author | Linus Torvalds <torvalds@linux-foundation.org> | 2008-04-24 09:33:34 -0700 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2008-04-24 09:33:34 -0700 |
commit | 346ad4b7fe392571f19314f153db9151dbc1d82b (patch) | |
tree | 2d4085338c9044bca2f6472893da60387db3c96f /arch/blackfin/kernel/cplb-nompu/cplbinit.c | |
parent | 845199f194306dbd69ca42d3b40a5125cdb50b89 (diff) | |
parent | 2dc63a84b2db23b9680646aff93917211613bf1a (diff) |
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cooloney/blackfin-2.6
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cooloney/blackfin-2.6: (85 commits)
Blackfin char driver for Blackfin on-chip OTP memory (v3)
Blackfin Serial Driver: fix bug - use mod_timer to replace only add_timer.
Blackfin Serial Driver: the uart break anomaly has been given its own number, so switch to it
Blackfin Serial Driver: use BFIN_UART_NR_PORTS to help SIR driver in uart port.
Blackfin Serial Driver: Fix bug - kernel hangs when accessing uart 0 on bf537 when booting u-boot and linux on uart 1
Blackfin Serial Driver: punt unused lsr variable
Blackfin Serial Driver: Enable IR function when user application (irattach /dev/ttyBFx -s) call TIOCSETD ioctl with line discipline N_IRDA
[Blackfin] arch: add include/boot .gitignore files
[Blackfin] arch: Functional power management support: Add support for cpu frequency scaling
[Blackfin] arch: Functional power management support: Remove broken cpu frequency scaling drivers
[Blackfin] arch: Equalize include files: Add PLL_DIV Masks
[Blackfin] arch: Add a warning about the value of CLKIN.
[Blackfin] arch: take DDR DEVWD into consideration as well for BF548
[Blackfin] arch: Remove the circular buffering mechanism for exceptions
[Blackfin] arch: lose unnecessary dependency on CONFIG_BFIN_ICACHE for MPU
[Blackfin] arch: fix bug - before assign new channel to the map register, need clear the bits first.
[Blackfin] arch: add Blackfin on-chip SIR IrDA driver support
[Blackfin] arch: BF54x memsizes are in mbits, not mbytes
[Blackfin] arch: try to remove condition that causes double fault, by checking current before it gets dereferenced
[Blackfin] arch: Update anomaly list.
...
Diffstat (limited to 'arch/blackfin/kernel/cplb-nompu/cplbinit.c')
-rw-r--r-- | arch/blackfin/kernel/cplb-nompu/cplbinit.c | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/arch/blackfin/kernel/cplb-nompu/cplbinit.c b/arch/blackfin/kernel/cplb-nompu/cplbinit.c index 6320bc45fbb..917325bfbd8 100644 --- a/arch/blackfin/kernel/cplb-nompu/cplbinit.c +++ b/arch/blackfin/kernel/cplb-nompu/cplbinit.c @@ -26,6 +26,35 @@ #include <asm/cplb.h> #include <asm/cplbinit.h> +#ifdef CONFIG_MAX_MEM_SIZE +# define CPLB_MEM CONFIG_MAX_MEM_SIZE +#else +# define CPLB_MEM CONFIG_MEM_SIZE +#endif + +/* +* Number of required data CPLB switchtable entries +* MEMSIZE / 4 (we mostly install 4M page size CPLBs +* approx 16 for smaller 1MB page size CPLBs for allignment purposes +* 1 for L1 Data Memory +* possibly 1 for L2 Data Memory +* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO +* 1 for ASYNC Memory +*/ +#define MAX_SWITCH_D_CPLBS (((CPLB_MEM / 4) + 16 + 1 + 1 + 1 \ + + ASYNC_MEMORY_CPLB_COVERAGE) * 2) + +/* +* Number of required instruction CPLB switchtable entries +* MEMSIZE / 4 (we mostly install 4M page size CPLBs +* approx 12 for smaller 1MB page size CPLBs for allignment purposes +* 1 for L1 Instruction Memory +* possibly 1 for L2 Instruction Memory +* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO +*/ +#define MAX_SWITCH_I_CPLBS (((CPLB_MEM / 4) + 12 + 1 + 1 + 1) * 2) + + u_long icplb_table[MAX_CPLBS + 1]; u_long dcplb_table[MAX_CPLBS + 1]; @@ -295,6 +324,8 @@ void __init generate_cpl_tables(void) struct cplb_tab *t_d = NULL; struct s_cplb cplb; + printk(KERN_INFO "NOMPU: setting up cplb tables for global access\n"); + cplb.init_i.size = MAX_CPLBS; cplb.init_d.size = MAX_CPLBS; cplb.switch_i.size = MAX_SWITCH_I_CPLBS; |