diff options
| author | Jie Zhang <jie.zhang@analog.com> | 2009-06-16 09:48:33 +0000 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2009-06-22 21:15:59 -0400 |
| commit | 41ba653f24a39a0e6a4afe9b2763a95a57e042c2 (patch) | |
| tree | 43eb086046d4eef764878e04512ddd215ca8845b /arch/blackfin/mach-common | |
| parent | 7c039a90f02c3fdcab8d3ca170c05ad37014189e (diff) | |
Blackfin: decouple unrelated cache settings to get exact behavior
The current cache options don't really represent the hardware features.
They end up setting different aspects of the hardware so that the end
result is to turn on/off the cache. Unfortunately, when we hit cache
problems with the hardware, it's difficult to test different settings to
root cause the problem. The current settings also don't cleanly allow for
different caching behaviors with different regions of memory.
So split the configure options such that they properly reflect the settings
that are applied to the hardware.
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/mach-common')
| -rw-r--r-- | arch/blackfin/mach-common/arch_checks.c | 4 | ||||
| -rw-r--r-- | arch/blackfin/mach-common/cpufreq.c | 2 | ||||
| -rw-r--r-- | arch/blackfin/mach-common/pm.c | 4 |
3 files changed, 5 insertions, 5 deletions
diff --git a/arch/blackfin/mach-common/arch_checks.c b/arch/blackfin/mach-common/arch_checks.c index da93d920716..5998d8632a7 100644 --- a/arch/blackfin/mach-common/arch_checks.c +++ b/arch/blackfin/mach-common/arch_checks.c @@ -74,7 +74,7 @@ /* if 220 exists, can not set External Memory WB and L2 not_cached, either External Memory not_cached and L2 WB */ #if ANOMALY_05000220 && \ - ((defined(CONFIG_BFIN_WB) && defined(CONFIG_BFIN_L2_NOT_CACHED)) || \ - (!defined(CONFIG_BFIN_DCACHE) && defined(CONFIG_BFIN_L2_WB))) + ((defined(CONFIG_BFIN_EXTMEM_WRITEBACK) && !defined(CONFIG_BFIN_L2_DCACHEABLE)) || \ + (!defined(CONFIG_BFIN_EXTMEM_DCACHEABLE) && defined(CONFIG_BFIN_L2_WRITEBACK))) # error You are exposing Anomaly 220 in this config, either config L2 as Write Through, or make External Memory WB. #endif diff --git a/arch/blackfin/mach-common/cpufreq.c b/arch/blackfin/mach-common/cpufreq.c index 70e3411f558..85c65808327 100644 --- a/arch/blackfin/mach-common/cpufreq.c +++ b/arch/blackfin/mach-common/cpufreq.c @@ -141,7 +141,7 @@ static int __init __bfin_cpu_init(struct cpufreq_policy *policy) sclk = get_sclk() / 1000; #if ANOMALY_05000273 || ANOMALY_05000274 || \ - (!defined(CONFIG_BF54x) && defined(CONFIG_BFIN_DCACHE)) + (!defined(CONFIG_BF54x) && defined(CONFIG_BFIN_EXTMEM_DCACHEABLE)) min_cclk = sclk * 2; #else min_cclk = sclk; diff --git a/arch/blackfin/mach-common/pm.c b/arch/blackfin/mach-common/pm.c index bce5a84be49..9e7e27b7fc8 100644 --- a/arch/blackfin/mach-common/pm.c +++ b/arch/blackfin/mach-common/pm.c @@ -132,7 +132,7 @@ int bf53x_resume_l1_mem(unsigned char *memptr) return 0; } -#ifdef CONFIG_BFIN_WB +#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK) static void flushinv_all_dcache(void) { u32 way, bank, subbank, set; @@ -175,7 +175,7 @@ static inline void dcache_disable(void) #ifdef CONFIG_BFIN_DCACHE unsigned long ctrl; -#ifdef CONFIG_BFIN_WB +#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK) flushinv_all_dcache(); #endif SSYNC(); |