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authorMike Frysinger <vapier@gentoo.org>2009-04-10 20:52:08 +0000
committerMike Frysinger <vapier@gentoo.org>2009-06-12 06:03:45 -0400
commit5d89137a17ca804ee60077f5d4ad8d7ca60f0614 (patch)
treee6445551fdb86ffdbb3da14b8ab91d0e05c94612 /arch/blackfin/mach-common
parentf82e0a0c67621df83458753aef580a3508d5428e (diff)
Blackfin: fix data cache flushing when doing icache flushing
Make sure we flush all data caches and their write buffers before flushing icache, otherwise random edge cases could crop up where stale data is read into icache from external memory. As fallout, punt the combined icache + dcache flush function since we cannot safely do them back to back -- the SSYNC is needed between the dcache flush and the icache flush. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'arch/blackfin/mach-common')
-rw-r--r--arch/blackfin/mach-common/cache.S16
1 files changed, 0 insertions, 16 deletions
diff --git a/arch/blackfin/mach-common/cache.S b/arch/blackfin/mach-common/cache.S
index aa0648c6a9f..c295e8f837c 100644
--- a/arch/blackfin/mach-common/cache.S
+++ b/arch/blackfin/mach-common/cache.S
@@ -80,22 +80,6 @@ ENTRY(_blackfin_icache_flush_range)
do_flush IFLUSH, , nop
ENDPROC(_blackfin_icache_flush_range)
-/* Flush all cache lines assocoiated with this area of memory. */
-ENTRY(_blackfin_icache_dcache_flush_range)
-/*
- * Walkaround to avoid loading wrong instruction after invalidating icache
- * and following sequence is met.
- *
- * 1) One instruction address is cached in the instruction cache.
- * 2) This instruction in SDRAM is changed.
- * 3) IFLASH[P0] is executed only once in blackfin_icache_flush_range().
- * 4) This instruction is executed again, but the old one is loaded.
- */
- P0 = R0;
- IFLUSH[P0];
- do_flush FLUSH, IFLUSH
-ENDPROC(_blackfin_icache_dcache_flush_range)
-
/* Throw away all D-cached data in specified region without any obligation to
* write them back. Since the Blackfin ISA does not have an "invalidate"
* instruction, we use flush/invalidate. Perhaps as a speed optimization we