diff options
| author | Andi Kleen <ak@suse.de> | 2006-01-11 22:42:45 +0100 |
|---|---|---|
| committer | Linus Torvalds <torvalds@g5.osdl.org> | 2006-01-11 19:01:12 -0800 |
| commit | 39b3a7910556005a7a0d042ecb7ff98bfa84ea57 (patch) | |
| tree | efcb2602e6fd198c9af34e726741eb389fa4e292 /arch/i386/kernel/cpu/amd.c | |
| parent | 2d52ede9876ba566b583f255fdc43800eea81baa (diff) | |
[PATCH] i386/x86-64: Generalize X86_FEATURE_CONSTANT_TSC flag
Define it for i386 too.
This is a synthetic flag that signifies that the CPU's TSC runs
at a constant P state invariant frequency.
Fix up the logic on x86-64/i386 to set it on all known CPUs.
Use the AMD defined bit to set it on future AMD CPUs.
Cc: venkatesh.pallipadi@intel.com
Signed-off-by: Andi Kleen <ak@suse.de>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'arch/i386/kernel/cpu/amd.c')
| -rw-r--r-- | arch/i386/kernel/cpu/amd.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/i386/kernel/cpu/amd.c b/arch/i386/kernel/cpu/amd.c index e7697e077f6..4397f61705e 100644 --- a/arch/i386/kernel/cpu/amd.c +++ b/arch/i386/kernel/cpu/amd.c @@ -216,6 +216,11 @@ static void __init init_amd(struct cpuinfo_x86 *c) c->x86_max_cores = 1; } + if (cpuid_eax(0x80000000) >= 0x80000007) { + if (cpuid_edx(0x80000007) & (1<<8)) + set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability); + } + #ifdef CONFIG_X86_HT /* * On a AMD dual core setup the lower bits of the APIC id @@ -233,6 +238,7 @@ static void __init init_amd(struct cpuinfo_x86 *c) cpu, c->x86_max_cores, cpu_core_id[cpu]); } #endif + } static unsigned int amd_size_cache(struct cpuinfo_x86 * c, unsigned int size) |