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authorFuxin Zhang <zhangfx@lemote.com>2007-06-06 14:52:43 +0800
committerRalf Baechle <ralf@linux-mips.org>2007-07-10 17:33:02 +0100
commit2a21c7300b53b744d16903256a172d9cbcfdd03e (patch)
tree6a6f186fc7d4ab51fdda628a42f1fa845f189b8b /arch/mips/Kconfig
parentfee578fad1a29e6a149659e5467aedcae6897c06 (diff)
[MIPS] define Hit_Invalidate_I to Index_Invalidate_I for loongson2
Signed-off-by: Fuxin Zhang <zhangfx@lemote.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/Kconfig')
-rw-r--r--arch/mips/Kconfig22
1 files changed, 22 insertions, 0 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 624c31cd807..c8d954d6f2c 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -894,6 +894,16 @@ choice
prompt "CPU type"
default CPU_R4X00
+config CPU_LOONGSON2
+ bool "Loongson 2"
+ depends on SYS_HAS_CPU_LOONGSON2
+ select CPU_SUPPORTS_32BIT_KERNEL
+ select CPU_SUPPORTS_64BIT_KERNEL
+ select CPU_SUPPORTS_HIGHMEM
+ help
+ The Loongson 2E processor implements the MIPS III instruction set
+ with many extensions.
+
config CPU_MIPS32_R1
bool "MIPS32 Release 1"
depends on SYS_HAS_CPU_MIPS32_R1
@@ -1104,6 +1114,9 @@ config CPU_SB1
endchoice
+config SYS_HAS_CPU_LOONGSON2
+ bool
+
config SYS_HAS_CPU_MIPS32_R1
bool
@@ -1438,6 +1451,15 @@ config CPU_HAS_SMARTMIPS
config CPU_HAS_WB
bool
+config 64BIT_CONTEXT
+ bool "Save 64bit integer registers"
+ depends on 32BIT && CPU_LOONGSON2
+ help
+ Loongson2 CPU is 64bit , when used in 32BIT mode, its integer
+ registers can still be accessed as 64bit, mainly for multimedia
+ instructions. We must have all 64bit save/restored to make sure
+ those instructions to get correct result.
+
#
# Vectored interrupt mode is an R2 feature
#