diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 2006-04-03 17:56:36 +0100 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2006-04-19 04:14:21 +0200 |
| commit | e4ac58afdfac792c0583af30dbd9eae53e24c78b (patch) | |
| tree | 7517bef2c515fc630e4d3d238867b91cde96f558 /arch/mips/galileo-boards/ev96100/irq.c | |
| parent | d35d473c25d43d7db3e5e18b66d558d2a631cca8 (diff) | |
[MIPS] Rewrite all the assembler interrupt handlers to C.
Saves like 1,600 lines of code, is way easier to debug, compilers
frequently do a better job than the cut and paste type of handlers many
boards had. And finally having all the stuff done in a single place
also means alot of bug potencial for the MT ASE is gone.
The only surviving handler in assembler is the DECstation one; I hope
Maciej will rewrite it.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/galileo-boards/ev96100/irq.c')
| -rw-r--r-- | arch/mips/galileo-boards/ev96100/irq.c | 17 |
1 files changed, 14 insertions, 3 deletions
diff --git a/arch/mips/galileo-boards/ev96100/irq.c b/arch/mips/galileo-boards/ev96100/irq.c index 383801dd1b9..ee5d6720f23 100644 --- a/arch/mips/galileo-boards/ev96100/irq.c +++ b/arch/mips/galileo-boards/ev96100/irq.c @@ -40,8 +40,6 @@ #include <linux/interrupt.h> #include <asm/irq_cpu.h> -extern asmlinkage void ev96100IRQ(void); - static inline unsigned int ffz8(unsigned int word) { unsigned long k; @@ -54,13 +52,26 @@ static inline unsigned int ffz8(unsigned int word) return k; } +extern void mips_timer_interrupt(struct pt_regs *regs); + asmlinkage void ev96100_cpu_irq(unsigned int pending, struct pt_regs *regs) { do_IRQ(ffz8(pending >> 8), regs); } +asmlinkage void plat_irq_dispatch(struct pt_regs *regs) +{ + unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM; + + if (pending & CAUSEF_IP7) + mips_timer_interrupt(regs); + else if (pending) + ev96100_cpu_irq(pending, regs); + else + spurious_interrupt(regs); +} + void __init arch_init_irq(void) { - set_except_vector(0, ev96100IRQ); mips_cpu_irq_init(0); } |