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authorRalf Baechle <ralf@linux-mips.org>2007-11-19 12:23:51 +0000
committerRalf Baechle <ralf@linux-mips.org>2008-01-29 10:14:57 +0000
commit87353d8ac39c52784da605ecbe965ecdfad609ad (patch)
treec95ce7cbe9b099c21cab71a195621801b04bc05a /arch/mips/mips-boards
parent19388fb092d89e179575bd0b44f51b57e175edf5 (diff)
[MIPS] SMP: Call platform methods via ops structure.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mips-boards')
-rw-r--r--arch/mips/mips-boards/generic/init.c8
-rw-r--r--arch/mips/mips-boards/malta/malta_smtc.c66
2 files changed, 48 insertions, 26 deletions
diff --git a/arch/mips/mips-boards/generic/init.c b/arch/mips/mips-boards/generic/init.c
index 30f1f54cb68..1695dca5506 100644
--- a/arch/mips/mips-boards/generic/init.c
+++ b/arch/mips/mips-boards/generic/init.c
@@ -250,6 +250,8 @@ void __init mips_ejtag_setup(void)
flush_icache_range((unsigned long)base, (unsigned long)base + 0x80);
}
+extern struct plat_smp_ops msmtc_smp_ops;
+
void __init prom_init(void)
{
prom_argc = fw_arg0;
@@ -416,4 +418,10 @@ void __init prom_init(void)
#ifdef CONFIG_SERIAL_8250_CONSOLE
console_config();
#endif
+#ifdef CONFIG_MIPS_MT_SMP
+ register_smp_ops(&vsmp_smp_ops);
+#endif
+#ifdef CONFIG_MIPS_MT_SMTC
+ register_smp_ops(&msmtc_smp_ops);
+#endif
}
diff --git a/arch/mips/mips-boards/malta/malta_smtc.c b/arch/mips/mips-boards/malta/malta_smtc.c
index 5c980f4a48f..6f051ca243f 100644
--- a/arch/mips/mips-boards/malta/malta_smtc.c
+++ b/arch/mips/mips-boards/malta/malta_smtc.c
@@ -15,26 +15,24 @@
* Cause the specified action to be performed on a targeted "CPU"
*/
-void core_send_ipi(int cpu, unsigned int action)
+static void msmtc_send_ipi_single(int cpu, unsigned int action)
{
/* "CPU" may be TC of same VPE, VPE of same CPU, or different CPU */
smtc_send_ipi(cpu, LINUX_SMP_IPI, action);
}
-/*
- * Platform "CPU" startup hook
- */
-
-void __cpuinit prom_boot_secondary(int cpu, struct task_struct *idle)
+static void msmtc_send_ipi_mask(cpumask_t mask, unsigned int action)
{
- smtc_boot_secondary(cpu, idle);
+ unsigned int i;
+
+ for_each_cpu_mask(i, mask)
+ msmtc_send_ipi_single(i, action);
}
/*
* Post-config but pre-boot cleanup entry point
*/
-
-void __cpuinit prom_init_secondary(void)
+static void __cpuinit msmtc_init_secondary(void)
{
void smtc_init_secondary(void);
int myvpe;
@@ -50,45 +48,61 @@ void __cpuinit prom_init_secondary(void)
set_c0_status(0x100 << cp0_perfcount_irq);
}
- smtc_init_secondary();
+ smtc_init_secondary();
}
/*
- * Platform SMP pre-initialization
- *
- * As noted above, we can assume a single CPU for now
- * but it may be multithreaded.
+ * Platform "CPU" startup hook
*/
-
-void __cpuinit plat_smp_setup(void)
+static void __cpuinit msmtc_boot_secondary(int cpu, struct task_struct *idle)
{
- if (read_c0_config3() & (1<<2))
- mipsmt_build_cpu_map(0);
+ smtc_boot_secondary(cpu, idle);
}
-void __init plat_prepare_cpus(unsigned int max_cpus)
+/*
+ * SMP initialization finalization entry point
+ */
+static void __cpuinit msmtc_smp_finish(void)
{
- if (read_c0_config3() & (1<<2))
- mipsmt_prepare_cpus();
+ smtc_smp_finish();
}
/*
- * SMP initialization finalization entry point
+ * Hook for after all CPUs are online
*/
-void __cpuinit prom_smp_finish(void)
+static void msmtc_cpus_done(void)
{
- smtc_smp_finish();
}
/*
- * Hook for after all CPUs are online
+ * Platform SMP pre-initialization
+ *
+ * As noted above, we can assume a single CPU for now
+ * but it may be multithreaded.
*/
-void prom_cpus_done(void)
+static void __init msmtc_smp_setup(void)
{
+ mipsmt_build_cpu_map(0);
}
+static void __init msmtc_prepare_cpus(unsigned int max_cpus)
+{
+ mipsmt_prepare_cpus();
+}
+
+struct plat_smp_ops msmtc_smp_ops = {
+ .send_ipi_single = msmtc_send_ipi_single,
+ .send_ipi_mask = msmtc_send_ipi_mask,
+ .init_secondary = msmtc_init_secondary,
+ .smp_finish = msmtc_smp_finish,
+ .cpus_done = msmtc_cpus_done,
+ .boot_secondary = msmtc_boot_secondary,
+ .smp_setup = msmtc_smp_setup,
+ .prepare_cpus = msmtc_prepare_cpus,
+};
+
#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
/*
* IRQ affinity hook