[MIPS] Remove Momenco Ocelot G support

Signed-off-by: Franck Bui-Huu <fbuihuu@gmail.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

8 files changed, 0 insertions, 868 deletions

diff --git a/arch/mips/momentum/ocelot_g/Makefile b/arch/mips/momentum/ocelot_g/Makefile
deleted file mode 100644
index c0a0030d949..00000000000
--- a/arch/mips/momentum/ocelot_g/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-#
-# Makefile for Momentum Computer's Ocelot-G board.
-#
-
-obj-y	 		+= irq.o gt-irq.o prom.o reset.o setup.o
-obj-$(CONFIG_KGDB)	+= dbg_io.o
diff --git a/arch/mips/momentum/ocelot_g/dbg_io.c b/arch/mips/momentum/ocelot_g/dbg_io.c
deleted file mode 100644
index 32d6fb4ee67..00000000000
--- a/arch/mips/momentum/ocelot_g/dbg_io.c
+++ /dev/null
@@ -1,121 +0,0 @@
-
-#include <asm/serial.h> /* For the serial port location and base baud */
-
-/* --- CONFIG --- */
-
-typedef unsigned char uint8;
-typedef unsigned int uint32;
-
-/* --- END OF CONFIG --- */
-
-#define         UART16550_BAUD_2400             2400
-#define         UART16550_BAUD_4800             4800
-#define         UART16550_BAUD_9600             9600
-#define         UART16550_BAUD_19200            19200
-#define         UART16550_BAUD_38400            38400
-#define         UART16550_BAUD_57600            57600
-#define         UART16550_BAUD_115200           115200
-
-#define         UART16550_PARITY_NONE           0
-#define         UART16550_PARITY_ODD            0x08
-#define         UART16550_PARITY_EVEN           0x18
-#define         UART16550_PARITY_MARK           0x28
-#define         UART16550_PARITY_SPACE          0x38
-
-#define         UART16550_DATA_5BIT             0x0
-#define         UART16550_DATA_6BIT             0x1
-#define         UART16550_DATA_7BIT             0x2
-#define         UART16550_DATA_8BIT             0x3
-
-#define         UART16550_STOP_1BIT             0x0
-#define         UART16550_STOP_2BIT             0x4
-
-/* ----------------------------------------------------- */
-
-/* === CONFIG === */
-
-/* [jsun] we use the second serial port for kdb */
-#define         BASE                    OCELOT_SERIAL1_BASE
-#define         MAX_BAUD                OCELOT_BASE_BAUD
-
-/* === END OF CONFIG === */
-
-#define         REG_OFFSET              4
-
-/* register offset */
-#define         OFS_RCV_BUFFER          0
-#define         OFS_TRANS_HOLD          0
-#define         OFS_SEND_BUFFER         0
-#define         OFS_INTR_ENABLE         (1*REG_OFFSET)
-#define         OFS_INTR_ID             (2*REG_OFFSET)
-#define         OFS_DATA_FORMAT         (3*REG_OFFSET)
-#define         OFS_LINE_CONTROL        (3*REG_OFFSET)
-#define         OFS_MODEM_CONTROL       (4*REG_OFFSET)
-#define         OFS_RS232_OUTPUT        (4*REG_OFFSET)
-#define         OFS_LINE_STATUS         (5*REG_OFFSET)
-#define         OFS_MODEM_STATUS        (6*REG_OFFSET)
-#define         OFS_RS232_INPUT         (6*REG_OFFSET)
-#define         OFS_SCRATCH_PAD         (7*REG_OFFSET)
-
-#define         OFS_DIVISOR_LSB         (0*REG_OFFSET)
-#define         OFS_DIVISOR_MSB         (1*REG_OFFSET)
-
-
-/* memory-mapped read/write of the port */
-#define         UART16550_READ(y)    (*((volatile uint8*)(BASE + y)))
-#define         UART16550_WRITE(y, z)  ((*((volatile uint8*)(BASE + y))) = z)
-
-void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
-{
-	/* disable interrupts */
-	UART16550_WRITE(OFS_INTR_ENABLE, 0);
-
-	/* set up baud rate */
-	{
-		uint32 divisor;
-
-		/* set DIAB bit */
-		UART16550_WRITE(OFS_LINE_CONTROL, 0x80);
-
-		/* set divisor */
-		divisor = MAX_BAUD / baud;
-		UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);
-		UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8);
-
-		/* clear DIAB bit */
-		UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
-	}
-
-	/* set data format */
-	UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);
-}
-
-static int remoteDebugInitialized = 0;
-
-uint8 getDebugChar(void)
-{
-	if (!remoteDebugInitialized) {
-		remoteDebugInitialized = 1;
-		debugInit(UART16550_BAUD_38400,
-			  UART16550_DATA_8BIT,
-			  UART16550_PARITY_NONE, UART16550_STOP_1BIT);
-	}
-
-	while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0);
-	return UART16550_READ(OFS_RCV_BUFFER);
-}
-
-
-int putDebugChar(uint8 byte)
-{
-	if (!remoteDebugInitialized) {
-		remoteDebugInitialized = 1;
-		debugInit(UART16550_BAUD_38400,
-			  UART16550_DATA_8BIT,
-			  UART16550_PARITY_NONE, UART16550_STOP_1BIT);
-	}
-
-	while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0);
-	UART16550_WRITE(OFS_SEND_BUFFER, byte);
-	return 1;
-}
diff --git a/arch/mips/momentum/ocelot_g/gt-irq.c b/arch/mips/momentum/ocelot_g/gt-irq.c
deleted file mode 100644
index e5576bd50fa..00000000000
--- a/arch/mips/momentum/ocelot_g/gt-irq.c
+++ /dev/null
@@ -1,212 +0,0 @@
-/*
- *
- * Copyright 2002 Momentum Computer
- * Author: mdharm@momenco.com
- *
- * arch/mips/momentum/ocelot_g/gt_irq.c
- *     Interrupt routines for gt64240.  Currently it only handles timer irq.
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/kernel_stat.h>
-#include <asm/gt64240.h>
-#include <asm/io.h>
-
-unsigned long bus_clock;
-
-/*
- * These are interrupt handlers for the GT on-chip interrupts.  They
- * all come in to the MIPS on a single interrupt line, and have to
- * be handled and ack'ed differently than other MIPS interrupts.
- */
-
-#if 0
-
-struct tq_struct irq_handlers[MAX_CAUSE_REGS][MAX_CAUSE_REG_WIDTH];
-void hook_irq_handler(int int_cause, int bit_num, void *isr_ptr);
-
-/*
- * Hooks IRQ handler to the system. When the system is interrupted
- * the interrupt service routine is called.
- *
- * Inputs :
- * int_cause - The interrupt cause number. In EVB64120 two parameters
- *             are declared, INT_CAUSE_MAIN and INT_CAUSE_HIGH.
- * bit_num   - Indicates which bit number in the cause register
- * isr_ptr   - Pointer to the interrupt service routine
- */
-void hook_irq_handler(int int_cause, int bit_num, void *isr_ptr)
-{
-	irq_handlers[int_cause][bit_num].routine = isr_ptr;
-}
-
-
-/*
- * Enables the IRQ on Galileo Chip
- *
- * Inputs :
- * int_cause - The interrupt cause number. In EVB64120 two parameters
- *             are declared, INT_CAUSE_MAIN and INT_CAUSE_HIGH.
- * bit_num   - Indicates which bit number in the cause register
- *
- * Outputs :
- * 1 if successful, 0 if failure
- */
-int enable_galileo_irq(int int_cause, int bit_num)
-{
-	if (int_cause == INT_CAUSE_MAIN)
-		SET_REG_BITS(CPU_INTERRUPT_MASK_REGISTER, (1 << bit_num));
-	else if (int_cause == INT_CAUSE_HIGH)
-		SET_REG_BITS(CPU_HIGH_INTERRUPT_MASK_REGISTER,
-			     (1 << bit_num));
-	else
-		return 0;
-
-	return 1;
-}
-
-/*
- * Disables the IRQ on Galileo Chip
- *
- * Inputs :
- * int_cause - The interrupt cause number. In EVB64120 two parameters
- *             are declared, INT_CAUSE_MAIN and INT_CAUSE_HIGH.
- * bit_num   - Indicates which bit number in the cause register
- *
- * Outputs :
- * 1 if successful, 0 if failure
- */
-int disable_galileo_irq(int int_cause, int bit_num)
-{
-	if (int_cause == INT_CAUSE_MAIN)
-		RESET_REG_BITS(CPU_INTERRUPT_MASK_REGISTER,
-			       (1 << bit_num));
-	else if (int_cause == INT_CAUSE_HIGH)
-		RESET_REG_BITS(CPU_HIGH_INTERRUPT_MASK_REGISTER,
-			       (1 << bit_num));
-	else
-		return 0;
-	return 1;
-}
-#endif /* 0 */
-
-/*
- * Interrupt handler for interrupts coming from the Galileo chip via P0_INT#.
- *
- * We route the timer interrupt to P0_INT# (IRQ 6), and that's all this
- * routine can handle, for now.
- *
- * In the future, we'll route more interrupts to this pin, and that's why
- * we keep this particular structure in the function.
- */
-
-static irqreturn_t gt64240_p0int_irq(int irq, void *dev)
-{
-	uint32_t irq_src, irq_src_mask;
-	int handled;
-
-	/* get the low interrupt cause register */
-	irq_src = MV_READ(LOW_INTERRUPT_CAUSE_REGISTER);
-
-	/* get the mask register for this pin */
-	irq_src_mask = MV_READ(PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW);
-
-	/* mask off only the interrupts we're interested in */
-	irq_src = irq_src & irq_src_mask;
-
-	handled = IRQ_NONE;
-
-	/* Check for timer interrupt */
-	if (irq_src & 0x00000100) {
-		handled = IRQ_HANDLED;
-		irq_src &= ~0x00000100;
-
-		/* Clear any pending cause bits */
-		MV_WRITE(TIMER_COUNTER_0_3_INTERRUPT_CAUSE, 0x0);
-
-		/* handle the timer call */
-		do_timer(1);
-#ifndef CONFIG_SMP
-		update_process_times(user_mode(get_irq_regs()));
-#endif
-	}
-
-	if (irq_src) {
-		printk(KERN_INFO
-		       "UNKNOWN P0_INT# interrupt received, irq_src=0x%x\n",
-		       irq_src);
-	}
-
-	return handled;
-}
-
-/*
- * Initializes timer using galileo's built in timer.
- */
-
-/*
- * This will ignore the standard MIPS timer interrupt handler
- * that is passed in as *irq (=irq0 in ../kernel/time.c).
- * We will do our own timer interrupt handling.
- */
-void gt64240_time_init(void)
-{
-	static struct irqaction timer;
-
-	/* Stop the timer -- we'll use timer #0 */
-	MV_WRITE(TIMER_COUNTER_0_3_CONTROL, 0x0);
-
-	/* Load timer value for 100 Hz */
-	MV_WRITE(TIMER_COUNTER0, bus_clock / 100);
-
-	/*
-	 * Create the IRQ structure entry for the timer.  Since we're too early
-	 * in the boot process to use the "request_irq()" call, we'll hard-code
-	 * the values to the correct interrupt line.
-	 */
-	timer.handler = &gt64240_p0int_irq;
-	timer.flags = IRQF_SHARED | IRQF_DISABLED;
-	timer.name = "timer";
-	timer.dev_id = NULL;
-	timer.next = NULL;
-	timer.mask = CPU_MASK_NONE;
-	irq_desc[6].action = &timer;
-
-	enable_irq(6);
-
-	/* Clear any pending cause bits */
-	MV_WRITE(TIMER_COUNTER_0_3_INTERRUPT_CAUSE, 0x0);
-
-	/* Enable the interrupt for timer 0 */
-	MV_WRITE(TIMER_COUNTER_0_3_INTERRUPT_MASK, 0x1);
-
-	/* Enable the timer interrupt for GT-64240 pin P0_INT# */
-	MV_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0x100);
-
-	/* Configure and start the timer */
-	MV_WRITE(TIMER_COUNTER_0_3_CONTROL, 0x3);
-}
-
-void gt64240_irq_init(void)
-{
-#if 0
-	int i, j;
-
-	/* Reset irq handlers pointers to NULL */
-	for (i = 0; i < MAX_CAUSE_REGS; i++) {
-		for (j = 0; j < MAX_CAUSE_REG_WIDTH; j++) {
-			irq_handlers[i][j].next = NULL;
-			irq_handlers[i][j].sync = 0;
-			irq_handlers[i][j].routine = NULL;
-			irq_handlers[i][j].data = NULL;
-		}
-	}
-#endif /* 0 */
-}
diff --git a/arch/mips/momentum/ocelot_g/irq.c b/arch/mips/momentum/ocelot_g/irq.c
deleted file mode 100644
index 273541fe708..00000000000
--- a/arch/mips/momentum/ocelot_g/irq.c
+++ /dev/null
@@ -1,101 +0,0 @@
-/*
- * Copyright (C) 2000 RidgeRun, Inc.
- * Author: RidgeRun, Inc.
- *   glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
- *
- * Copyright 2001 MontaVista Software Inc.
- * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
- * Copyright (C) 2000, 01, 05 Ralf Baechle (ralf@linux-mips.org)
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-#include <linux/errno.h>
-#include <linux/init.h>
-#include <linux/kernel_stat.h>
-#include <linux/module.h>
-#include <linux/signal.h>
-#include <linux/sched.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/timex.h>
-#include <linux/slab.h>
-#include <linux/random.h>
-#include <linux/bitops.h>
-#include <asm/bootinfo.h>
-#include <asm/io.h>
-#include <asm/irq.h>
-#include <asm/irq_cpu.h>
-#include <asm/mipsregs.h>
-#include <asm/system.h>
-
-asmlinkage void plat_irq_dispatch(void)
-{
-	unsigned int pending = read_c0_cause() & read_c0_status();
-
-	if (pending & STATUSF_IP2)
-		do_IRQ(2);
-	else if (pending & STATUSF_IP3)
-		do_IRQ(3);
-	else if (pending & STATUSF_IP4)
-		do_IRQ(4);
-	else if (pending & STATUSF_IP5)
-		do_IRQ(5);
-	else if (pending & STATUSF_IP6)
-		do_IRQ(6);
-	else if (pending & STATUSF_IP7)
-		do_IRQ(7);
-	else {
-		/*
-		 * Now look at the extended interrupts
-		 */
-		pending = (read_c0_cause() & (read_c0_intcontrol() << 8)) >> 16;
-
-		if (pending & STATUSF_IP8)
-			do_IRQ(8);
-		else if (pending & STATUSF_IP9)
-			do_IRQ(9);
-		else if (pending & STATUSF_IP10)
-			do_IRQ(10);
-		else if (pending & STATUSF_IP11)
-			do_IRQ(11);
-		else
-			spurious_interrupt();
-	}
-}
-
-extern void gt64240_irq_init(void);
-
-void __init arch_init_irq(void)
-{
-	/*
-	 * Clear all of the interrupts while we change the able around a bit.
-	 * int-handler is not on bootstrap
-	 */
-	clear_c0_status(ST0_IM);
-	local_irq_disable();
-
-	mips_cpu_irq_init();
-	rm7k_cpu_irq_init();
-
-	gt64240_irq_init();
-}
diff --git a/arch/mips/momentum/ocelot_g/ocelot_pld.h b/arch/mips/momentum/ocelot_g/ocelot_pld.h
deleted file mode 100644
index 95e0534026d..00000000000
--- a/arch/mips/momentum/ocelot_g/ocelot_pld.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * Ocelot Board Register Definitions
- *
- * (C) 2001 Red Hat, Inc.
- *
- * GPL'd
- */
-#ifndef __MOMENCO_OCELOT_PLD_H__
-#define __MOMENCO_OCELOT_PLD_H__
-
-#define OCELOT_CS0_ADDR (0xfc000000)
-
-#define OCELOT_REG_BOARDREV (0)
-#define OCELOT_REG_PLD1_ID (1)
-#define OCELOT_REG_PLD2_ID (2)
-#define OCELOT_REG_RESET_STATUS (3)
-#define OCELOT_REG_BOARD_STATUS (4)
-#define OCELOT_REG_CPCI_ID (5)
-#define OCELOT_REG_I2C_CTRL (8)
-#define OCELOT_REG_EEPROM_MODE (9)
-#define OCELOT_REG_INTMASK (10)
-#define OCELOT_REG_INTSTATUS (11)
-#define OCELOT_REG_INTSET (12)
-#define OCELOT_REG_INTCLR (13)
-
-#define __PLD_REG_TO_ADDR(reg) ((void *) OCELOT_CS0_ADDR + OCELOT_REG_##reg)
-#define OCELOT_PLD_WRITE(x, reg) writeb(x, __PLD_REG_TO_ADDR(reg))
-#define OCELOT_PLD_READ(reg) readb(__PLD_REG_TO_ADDR(reg))
-
-#endif /* __MOMENCO_OCELOT_PLD_H__ */
diff --git a/arch/mips/momentum/ocelot_g/prom.c b/arch/mips/momentum/ocelot_g/prom.c
deleted file mode 100644
index 836d0830720..00000000000
--- a/arch/mips/momentum/ocelot_g/prom.c
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * Copyright 2002 Momentum Computer Inc.
- * Author: Matthew Dharm <mdharm@momenco.com>
- *
- * Based on Ocelot Linux port, which is
- * Copyright 2001 MontaVista Software Inc.
- * Author: jsun@mvista.com or jsun@junsun.net
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/sched.h>
-#include <linux/bootmem.h>
-
-#include <asm/addrspace.h>
-#include <asm/bootinfo.h>
-#include <asm/pmon.h>
-#include <asm/gt64240.h>
-
-#include "ocelot_pld.h"
-
-struct callvectors* debug_vectors;
-
-extern unsigned long marvell_base;
-extern unsigned long bus_clock;
-
-#ifdef CONFIG_GALILEO_GT64240_ETH
-extern unsigned char prom_mac_addr_base[6];
-#endif
-
-const char *get_system_type(void)
-{
-	return "Momentum Ocelot";
-}
-
-void __init prom_init(void)
-{
-	int argc = fw_arg0;
-	char **arg = (char **) fw_arg1;
-	char **env = (char **) fw_arg2;
-	struct callvectors *cv = (struct callvectors *) fw_arg3;
-	int i;
-
-	/* save the PROM vectors for debugging use */
-	debug_vectors = cv;
-
-	/* arg[0] is "g", the rest is boot parameters */
-	arcs_cmdline[0] = '\0';
-	for (i = 1; i < argc; i++) {
-		if (strlen(arcs_cmdline) + strlen(arg[i] + 1)
-		    >= sizeof(arcs_cmdline))
-			break;
-		strcat(arcs_cmdline, arg[i]);
-		strcat(arcs_cmdline, " ");
-	}
-
-	mips_machgroup = MACH_GROUP_MOMENCO;
-	mips_machtype = MACH_MOMENCO_OCELOT_G;
-
-#ifdef CONFIG_GALILEO_GT64240_ETH
-	/* get the base MAC address for on-board ethernet ports */
-	memcpy(prom_mac_addr_base, (void*)0xfc807cf2, 6);
-#endif
-
-	while (*env) {
-		if (strncmp("gtbase", *env, strlen("gtbase")) == 0) {
-			marvell_base = simple_strtol(*env + strlen("gtbase="),
-							NULL, 16);
-		}
-		if (strncmp("busclock", *env, strlen("busclock")) == 0) {
-			bus_clock = simple_strtol(*env + strlen("busclock="),
-							NULL, 10);
-		}
-		env++;
-	}
-}
-
-void __init prom_free_prom_memory(void)
-{
-}
diff --git a/arch/mips/momentum/ocelot_g/reset.c b/arch/mips/momentum/ocelot_g/reset.c
deleted file mode 100644
index 3fd499adf4c..00000000000
--- a/arch/mips/momentum/ocelot_g/reset.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- *
- * Copyright (C) 1997, 2001 Ralf Baechle
- * Copyright 2001 MontaVista Software Inc.
- * Author: jsun@mvista.com or jsun@junsun.net
- */
-#include <linux/sched.h>
-#include <linux/mm.h>
-#include <asm/io.h>
-#include <asm/pgtable.h>
-#include <asm/processor.h>
-#include <asm/reboot.h>
-#include <asm/system.h>
-#include <linux/delay.h>
-
-void momenco_ocelot_restart(char *command)
-{
-	void *nvram = ioremap_nocache(0x2c807000, 0x1000);
-
-	if (!nvram) {
-		printk(KERN_NOTICE "ioremap of reset register failed\n");
-		return;
-	}
-	writeb(0x84, nvram + 0xff7); /* Ask the NVRAM/RTC/watchdog chip to
-					assert reset in 1/16 second */
-	mdelay(10+(1000/16));
-	iounmap(nvram);
-	printk(KERN_NOTICE "Watchdog reset failed\n");
-}
-
-void momenco_ocelot_halt(void)
-{
-	printk(KERN_NOTICE "\n** You can safely turn off the power\n");
-	while (1)
-		__asm__(".set\tmips3\n\t"
-	                "wait\n\t"
-			".set\tmips0");
-}
-
-void momenco_ocelot_power_off(void)
-{
-	momenco_ocelot_halt();
-}
diff --git a/arch/mips/momentum/ocelot_g/setup.c b/arch/mips/momentum/ocelot_g/setup.c
deleted file mode 100644
index 9db638a7982..00000000000
--- a/arch/mips/momentum/ocelot_g/setup.c
+++ /dev/null
@@ -1,267 +0,0 @@
-/*
- * BRIEF MODULE DESCRIPTION
- * Momentum Computer Ocelot-G (CP7000G) - board dependent boot routines
- *
- * Copyright (C) 1996, 1997, 2001  Ralf Baechle
- * Copyright (C) 2000 RidgeRun, Inc.
- * Copyright (C) 2001 Red Hat, Inc.
- * Copyright (C) 2002 Momentum Computer
- *
- * Author: Matthew Dharm, Momentum Computer
- *   mdharm@momenco.com
- *
- * Author: RidgeRun, Inc.
- *   glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
- *
- * Copyright 2001 MontaVista Software Inc.
- * Author: jsun@mvista.com or jsun@junsun.net
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/mm.h>
-#include <linux/swap.h>
-#include <linux/ioport.h>
-#include <linux/sched.h>
-#include <linux/interrupt.h>
-#include <linux/pci.h>
-#include <linux/pm.h>
-#include <linux/timex.h>
-#include <linux/vmalloc.h>
-
-#include <asm/time.h>
-#include <asm/bootinfo.h>
-#include <asm/page.h>
-#include <asm/io.h>
-#include <asm/gt64240.h>
-#include <asm/irq.h>
-#include <asm/pci.h>
-#include <asm/pgtable.h>
-#include <asm/processor.h>
-#include <asm/reboot.h>
-#include <linux/bootmem.h>
-
-#include "ocelot_pld.h"
-
-#ifdef CONFIG_GALILEO_GT64240_ETH
-extern unsigned char prom_mac_addr_base[6];
-#endif
-
-unsigned long marvell_base;
-
-/* These functions are used for rebooting or halting the machine*/
-extern void momenco_ocelot_restart(char *command);
-extern void momenco_ocelot_halt(void);
-extern void momenco_ocelot_power_off(void);
-
-extern void gt64240_time_init(void);
-extern void momenco_ocelot_irq_setup(void);
-
-static char reset_reason;
-
-static unsigned long ENTRYLO(unsigned long paddr)
-{
-	return ((paddr & PAGE_MASK) |
-	       (_PAGE_PRESENT | __READABLE | __WRITEABLE | _PAGE_GLOBAL |
-		_CACHE_UNCACHED)) >> 6;
-}
-
-/* setup code for a handoff from a version 2 PMON 2000 PROM */
-void PMON_v2_setup(void)
-{
-	/* A wired TLB entry for the GT64240 and the serial port. The
-	   GT64240 is going to be hit on every IRQ anyway - there's
-	   absolutely no point in letting it be a random TLB entry, as
-	   it'll just cause needless churning of the TLB. And we use
-	   the other half for the serial port, which is just a PITA
-	   otherwise :)
-
-		Device			Physical	Virtual
-		GT64240 Internal Regs	0xf4000000	0xe0000000
-		UARTs (CS2)		0xfd000000	0xe0001000
-	*/
-	add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000),
-	                0xf4000000, PM_64K);
-	add_wired_entry(ENTRYLO(0xfd000000), ENTRYLO(0xfd001000),
-	                0xfd000000, PM_4K);
-
-	/* Also a temporary entry to let us talk to the Ocelot PLD and NVRAM
-	   in the CS[012] region. We can't use ioremap() yet. The NVRAM
-	   is a ST M48T37Y, which includes NVRAM, RTC, and Watchdog functions.
-
-		Ocelot PLD (CS0)	0xfc000000	0xe0020000
-		NVRAM (CS1)		0xfc800000	0xe0030000
-	*/
-	add_temporary_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfc010000),
-	                    0xfc000000, PM_64K);
-	add_temporary_entry(ENTRYLO(0xfc800000), ENTRYLO(0xfc810000),
-	                    0xfc800000, PM_64K);
-
-	marvell_base = 0xf4000000;
-}
-
-extern int rm7k_tcache_enabled;
-
-/*
- * This runs in KSEG1. See the verbiage in rm7k.c::probe_scache()
- */
-#define Page_Invalidate_T 0x16
-static void __init setup_l3cache(unsigned long size)
-{
-	int register i;
-
-	printk("Enabling L3 cache...");
-
-	/* Enable the L3 cache in the GT64120A's CPU Configuration register */
-	MV_WRITE(0, MV_READ(0) | (1<<14));
-
-	/* Enable the L3 cache in the CPU */
-	set_c0_config(1<<12 /* CONF_TE */);
-
-	/* Clear the cache */
-	write_c0_taglo(0);
-	write_c0_taghi(0);
-
-	for (i=0; i < size; i+= 4096) {
-		__asm__ __volatile__ (
-			".set noreorder\n\t"
-			".set mips3\n\t"
-			"cache %1, (%0)\n\t"
-			".set mips0\n\t"
-			".set reorder"
-			:
-			: "r" (KSEG0ADDR(i)),
-			  "i" (Page_Invalidate_T));
-	}
-
-	/* Let the RM7000 MM code know that the tertiary cache is enabled */
-	rm7k_tcache_enabled = 1;
-
-	printk("Done\n");
-}
-
-void __init plat_timer_setup(struct irqaction *irq)
-{
-}
-
-void __init plat_mem_setup(void)
-{
-	void (*l3func)(unsigned long) = (void *) KSEG1ADDR(setup_l3cache);
-	unsigned int tmpword;
-
-	board_time_init = gt64240_time_init;
-
-	_machine_restart = momenco_ocelot_restart;
-	_machine_halt = momenco_ocelot_halt;
-	pm_power_off = momenco_ocelot_power_off;
-
-	/*
-	 * initrd_start = (unsigned long)ocelot_initrd_start;
-	 * initrd_end = (unsigned long)ocelot_initrd_start + (ulong)ocelot_initrd_size;
-	 * initrd_below_start_ok = 1;
-	 */
-
-	/* do handoff reconfiguration */
-	PMON_v2_setup();
-
-#ifdef CONFIG_GALILEO_GT64240_ETH
-	/* get the mac addr */
-	memcpy(prom_mac_addr_base, (void*)0xfc807cf2, 6);
-#endif
-
-	/* Turn off the Bit-Error LED */
-	OCELOT_PLD_WRITE(0x80, INTCLR);
-
-	tmpword = OCELOT_PLD_READ(BOARDREV);
-	if (tmpword < 26)
-		printk("Momenco Ocelot-G: Board Assembly Rev. %c\n", 'A'+tmpword);
-	else
-		printk("Momenco Ocelot-G: Board Assembly Revision #0x%x\n", tmpword);
-
-	tmpword = OCELOT_PLD_READ(PLD1_ID);
-	printk("PLD 1 ID: %d.%d\n", tmpword>>4, tmpword&15);
-	tmpword = OCELOT_PLD_READ(PLD2_ID);
-	printk("PLD 2 ID: %d.%d\n", tmpword>>4, tmpword&15);
-	tmpword = OCELOT_PLD_READ(RESET_STATUS);
-	printk("Reset reason: 0x%x\n", tmpword);
-	reset_reason = tmpword;
-	OCELOT_PLD_WRITE(0xff, RESET_STATUS);
-
-	tmpword = OCELOT_PLD_READ(BOARD_STATUS);
-	printk("Board Status register: 0x%02x\n", tmpword);
-	printk("  - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent");
-	printk("  - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent");
-	printk("  - Tulip PHY %s connected\n", (tmpword&0x10)?"is":"not");
-	printk("  - L3 Cache size: %d MiB\n", (1<<((tmpword&12) >> 2))&~1);
-	printk("  - SDRAM size: %d MiB\n", 1<<(6+(tmpword&3)));
-
-	if (tmpword&12)
-		l3func((1<<(((tmpword&12) >> 2)+20)));
-
-	switch(tmpword &3) {
-	case 3:
-		/* 512MiB -- two banks of 256MiB */
-		add_memory_region(  0x0<<20, 0x100<<20, BOOT_MEM_RAM);
-/*
-		add_memory_region(0x100<<20, 0x100<<20, BOOT_MEM_RAM);
-*/
-		break;
-	case 2:
-		/* 256MiB -- two banks of 128MiB */
-		add_memory_region( 0x0<<20, 0x80<<20, BOOT_MEM_RAM);
-		add_memory_region(0x80<<20, 0x80<<20, BOOT_MEM_RAM);
-		break;
-	case 1:
-		/* 128MiB -- 64MiB per bank */
-		add_memory_region( 0x0<<20, 0x40<<20, BOOT_MEM_RAM);
-		add_memory_region(0x40<<20, 0x40<<20, BOOT_MEM_RAM);
-		break;
-	case 0:
-		/* 64MiB */
-		add_memory_region( 0x0<<20, 0x40<<20, BOOT_MEM_RAM);
-		break;
-	}
-
-	/* FIXME: Fix up the DiskOnChip mapping */
-	MV_WRITE(0x468, 0xfef73);
-}
-
-/* This needs to be one of the first initcalls, because no I/O port access
-   can work before this */
-
-static int io_base_ioremap(void)
-{
-	/* we're mapping PCI accesses from 0xc0000000 to 0xf0000000 */
-	unsigned long io_remap_range;
-
-	io_remap_range = (unsigned long) ioremap(0xc0000000, 0x30000000);
-	if (!io_remap_range)
-		panic("Could not ioremap I/O port range");
-
-	set_io_port_base(io_remap_range - 0xc0000000);
-
-	return 0;
-}
-
-module_init(io_base_ioremap);