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authorPaul Mackerras <paulus@samba.org>2008-06-09 12:19:41 +1000
committerPaul Mackerras <paulus@samba.org>2008-06-09 12:19:41 +1000
commit8a3e1c670e503ddd6f6c373b307f38b783ee3a50 (patch)
tree03094e8425b750d2693a271ebc89b49312e5476a /arch/mips/pci
parente026892c85571e12f11abffde5a90bcc704d663e (diff)
parent60d5019be8acef268f4676d229c490186d338fbc (diff)
Merge branch 'merge'
Conflicts: arch/powerpc/sysdev/fsl_soc.c
Diffstat (limited to 'arch/mips/pci')
-rw-r--r--arch/mips/pci/ops-bridge.c20
-rw-r--r--arch/mips/pci/pci-ip27.c8
2 files changed, 26 insertions, 2 deletions
diff --git a/arch/mips/pci/ops-bridge.c b/arch/mips/pci/ops-bridge.c
index 1fa09929cd7..b46b3e21177 100644
--- a/arch/mips/pci/ops-bridge.c
+++ b/arch/mips/pci/ops-bridge.c
@@ -14,6 +14,22 @@
#include <asm/sn/sn0/hub.h>
/*
+ * Most of the IOC3 PCI config register aren't present
+ * we emulate what is needed for a normal PCI enumeration
+ */
+static u32 emulate_ioc3_cfg(int where, int size)
+{
+ if (size == 1 && where == 0x3d)
+ return 0x01;
+ else if (size == 2 && where == 0x3c)
+ return 0x0100;
+ else if (size == 4 && where == 0x3c)
+ return 0x00000100;
+
+ return 0;
+}
+
+/*
* The Bridge ASIC supports both type 0 and type 1 access. Type 1 is
* not really documented, so right now I can't write code which uses it.
* Therefore we use type 0 accesses for now even though they won't work
@@ -64,7 +80,7 @@ oh_my_gawd:
* generic PCI code a chance to look at the wrong register.
*/
if ((where >= 0x14 && where < 0x40) || (where >= 0x48)) {
- *value = 0;
+ *value = emulate_ioc3_cfg(where, size);
return PCIBIOS_SUCCESSFUL;
}
@@ -127,7 +143,7 @@ oh_my_gawd:
* generic PCI code a chance to look at the wrong register.
*/
if ((where >= 0x14 && where < 0x40) || (where >= 0x48)) {
- *value = 0;
+ *value = emulate_ioc3_cfg(where, size);
return PCIBIOS_SUCCESSFUL;
}
diff --git a/arch/mips/pci/pci-ip27.c b/arch/mips/pci/pci-ip27.c
index bb64828a92f..a18516925cd 100644
--- a/arch/mips/pci/pci-ip27.c
+++ b/arch/mips/pci/pci-ip27.c
@@ -47,6 +47,9 @@ int __cpuinit bridge_probe(nasid_t nasid, int widget_id, int masterwid)
static int num_bridges = 0;
bridge_t *bridge;
int slot;
+ extern int pci_probe_only;
+
+ pci_probe_only = 1;
printk("a bridge\n");
@@ -100,6 +103,11 @@ int __cpuinit bridge_probe(nasid_t nasid, int widget_id, int masterwid)
*/
bridge->b_wid_control |= BRIDGE_CTRL_IO_SWAP |
BRIDGE_CTRL_MEM_SWAP;
+#ifdef CONFIG_PAGE_SIZE_4KB
+ bridge->b_wid_control &= ~BRIDGE_CTRL_PAGE_SIZE;
+#else /* 16kB or larger */
+ bridge->b_wid_control |= BRIDGE_CTRL_PAGE_SIZE;
+#endif
/*
* Hmm... IRIX sets additional bits in the address which