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author | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-05-11 09:59:50 -0700 |
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committer | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-05-11 09:59:50 -0700 |
commit | f2c60ed038dedcc43a0eb3ef4e0602741ba90384 (patch) | |
tree | 1d06b6c080e1c164d87b66f8cc4b13203378b85a /arch/mips/pci | |
parent | cabca0cb0d0e8579428d8f8c3f606e2f01d26d14 (diff) | |
parent | 3f2d560e9029ec0b7edf8be0c32425f4bb57d582 (diff) |
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (28 commits)
[MIPS] Rework cobalt_board_id
[MIPS] Use RTC_CMOS for Cobalt
[MIPS] Use platform_device for Cobalt UART
[MIPS] Separate Alchemy processor based boards config
[MIPS] Fix build error in atomic64_cmpxchg
[MIPS] Run checksyscalls for N32 and O32 ABI
[MIPS] tlbex: use __maybe_unused
[MIPS] excite: use __maybe_unused
[MIPS] Add extern cobalt_board_id
[MIPS] Remove unused CONFIG_TOSHIBA_BOARDS
[MIPS] Rename tb0229_defconfig to tb0219_defconfig
[MIPS] Update tb0229_defconfig; add CONFIG_GPIO_TB0219.
[MIPS] Add minimum defconfig for RBHMA4200
[MIPS] SB1: Build fix.
[MIPS] Drop __devinit tag from allocate_irqno() and free_irqno()
[MIPS] clocksource: use CLOCKSOURCE_MASK() macro
[MIPS] Remove LIMITED_DMA support
[MIPS] Remove Momenco Jaguar ATX support
[MIPS] Remove Momenco Ocelot G support
[MIPS] FPU hazard handling
...
Diffstat (limited to 'arch/mips/pci')
-rw-r--r-- | arch/mips/pci/Makefile | 2 | ||||
-rw-r--r-- | arch/mips/pci/fixup-cobalt.c | 25 | ||||
-rw-r--r-- | arch/mips/pci/fixup-jaguar.c | 43 | ||||
-rw-r--r-- | arch/mips/pci/fixup-ocelot-g.c | 37 | ||||
-rw-r--r-- | arch/mips/pci/pci-ocelot-g.c | 97 |
5 files changed, 22 insertions, 182 deletions
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile index df487c063b1..aba3dbf47ed 100644 --- a/arch/mips/pci/Makefile +++ b/arch/mips/pci/Makefile @@ -30,11 +30,9 @@ obj-$(CONFIG_SOC_AU1500) += fixup-au1000.o ops-au1000.o obj-$(CONFIG_SOC_AU1550) += fixup-au1000.o ops-au1000.o obj-$(CONFIG_SOC_PNX8550) += fixup-pnx8550.o ops-pnx8550.o obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o -obj-$(CONFIG_MOMENCO_JAGUAR_ATX)+= fixup-jaguar.o obj-$(CONFIG_MOMENCO_OCELOT) += fixup-ocelot.o pci-ocelot.o obj-$(CONFIG_MOMENCO_OCELOT_3) += fixup-ocelot3.o obj-$(CONFIG_MOMENCO_OCELOT_C) += fixup-ocelot-c.o pci-ocelot-c.o -obj-$(CONFIG_MOMENCO_OCELOT_G) += fixup-ocelot-g.o pci-ocelot-g.o obj-$(CONFIG_PMC_YOSEMITE) += fixup-yosemite.o ops-titan.o ops-titan-ht.o \ pci-yosemite.o obj-$(CONFIG_SGI_IP27) += ops-bridge.o pci-ip27.o diff --git a/arch/mips/pci/fixup-cobalt.c b/arch/mips/pci/fixup-cobalt.c index 7d5f6bbf7a9..d57ffd7242c 100644 --- a/arch/mips/pci/fixup-cobalt.c +++ b/arch/mips/pci/fixup-cobalt.c @@ -17,9 +17,7 @@ #include <asm/io.h> #include <asm/gt64120.h> -#include <asm/mach-cobalt/cobalt.h> - -extern int cobalt_board_id; +#include <cobalt.h> static void qube_raq_galileo_early_fixup(struct pci_dev *dev) { @@ -115,6 +113,27 @@ static void qube_raq_galileo_fixup(struct pci_dev *dev) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111, qube_raq_galileo_fixup); +int cobalt_board_id; + +static void qube_raq_via_board_id_fixup(struct pci_dev *dev) +{ + u8 id; + int retval; + + retval = pci_read_config_byte(dev, VIA_COBALT_BRD_ID_REG, &id); + if (retval) { + panic("Cannot read board ID"); + return; + } + + cobalt_board_id = VIA_COBALT_BRD_REG_to_ID(id); + + printk(KERN_INFO "Cobalt board ID: %d\n", cobalt_board_id); +} + +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, + qube_raq_via_board_id_fixup); + static char irq_tab_qube1[] __initdata = { [COBALT_PCICONF_CPU] = 0, [COBALT_PCICONF_ETH0] = COBALT_QUBE1_ETH0_IRQ, diff --git a/arch/mips/pci/fixup-jaguar.c b/arch/mips/pci/fixup-jaguar.c deleted file mode 100644 index 6c5e1d47179..00000000000 --- a/arch/mips/pci/fixup-jaguar.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Marvell MV64340 interrupt fixup code. - * - * Marvell wants an NDA for their docs so this was written without - * documentation. You've been warned. - * - * Copyright (C) 2004 Ralf Baechle (ralf@linux-mips.org) - */ -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/pci.h> - -#include <asm/mipsregs.h> - -/* - * WARNING: Example of how _NOT_ to do it. - */ -int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) -{ - int bus = dev->bus->number; - - if (bus == 0 && slot == 1) - return 3; /* PCI-X A */ - if (bus == 0 && slot == 2) - return 4; /* PCI-X B */ - if (bus == 1 && slot == 1) - return 5; /* PCI A */ - if (bus == 1 && slot == 2) - return 6; /* PCI B */ - -return 0; - panic("Whooops in pcibios_map_irq"); -} - -/* Do platform specific device initialization at pci_enable_device() time */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} diff --git a/arch/mips/pci/fixup-ocelot-g.c b/arch/mips/pci/fixup-ocelot-g.c deleted file mode 100644 index d7a652e326c..00000000000 --- a/arch/mips/pci/fixup-ocelot-g.c +++ /dev/null @@ -1,37 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * Copyright (C) 2004 Ralf Baechle (ralf@linux-mips.org) - */ -#include <linux/types.h> -#include <linux/pci.h> -#include <linux/kernel.h> -#include <linux/init.h> - -int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) -{ - int bus = dev->bus->number; - - if (bus == 0 && slot == 1) /* Intel 82543 Gigabit MAC */ - return 2; /* irq_nr is 2 for INT0 */ - - if (bus == 0 && slot == 2) /* Intel 82543 Gigabit MAC */ - return 3; /* irq_nr is 3 for INT1 */ - - if (bus == 1 && slot == 3) /* Intel 21555 bridge */ - return 5; /* irq_nr is 8 for INT6 */ - - if (bus == 1 && slot == 4) /* PMC Slot */ - return 9; /* irq_nr is 9 for INT7 */ - - return -1; -} - -/* Do platform specific device initialization at pci_enable_device() time */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} diff --git a/arch/mips/pci/pci-ocelot-g.c b/arch/mips/pci/pci-ocelot-g.c deleted file mode 100644 index 1e3430154fa..00000000000 --- a/arch/mips/pci/pci-ocelot-g.c +++ /dev/null @@ -1,97 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) - * - * This doesn't really fly - but I don't have a GT64240 system for testing. - */ -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/types.h> -#include <linux/pci.h> -#include <asm/gt64240.h> - -/* - * We assume these address ranges have been programmed into the GT-64240 by - * the firmware. PMON in case of the Ocelot G does that. Note the size of - * the I/O range is completly stupid; I/O mappings are limited to at most - * 256 bytes by the PCI spec and deprecated; and just to make things worse - * apparently many devices don't decode more than 64k of I/O space. - */ - -#define gt_io_size 0x20000000UL -#define gt_io_base 0xe0000000UL - -static struct resource gt_pci_mem0_resource = { - .name = "MV64240 PCI0 MEM", - .start = 0xc0000000UL, - .end = 0xcfffffffUL, - .flags = IORESOURCE_MEM -}; - -static struct resource gt_pci_io_mem0_resource = { - .name = "MV64240 PCI0 IO MEM", - .start = 0xe0000000UL, - .end = 0xefffffffUL, - .flags = IORESOURCE_IO -}; - -static struct mv_pci_controller gt_bus0_controller = { - .pcic = { - .pci_ops = &mv_pci_ops, - .mem_resource = >_pci_mem0_resource, - .mem_offset = 0xc0000000UL, - .io_resource = >_pci_io_mem0_resource, - .io_offset = 0x00000000UL - }, - .config_addr = PCI_0CONFIGURATION_ADDRESS, - .config_vreg = PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER, -}; - -static struct resource gt_pci_mem1_resource = { - .name = "MV64240 PCI1 MEM", - .start = 0xd0000000UL, - .end = 0xdfffffffUL, - .flags = IORESOURCE_MEM -}; - -static struct resource gt_pci_io_mem1_resource = { - .name = "MV64240 PCI1 IO MEM", - .start = 0xf0000000UL, - .end = 0xffffffffUL, - .flags = IORESOURCE_IO -}; - -static struct mv_pci_controller gt_bus1_controller = { - .pcic = { - .pci_ops = &mv_pci_ops, - .mem_resource = >_pci_mem1_resource, - .mem_offset = 0xd0000000UL, - .io_resource = >_pci_io_mem1_resource, - .io_offset = 0x10000000UL - }, - .config_addr = PCI_1CONFIGURATION_ADDRESS, - .config_vreg = PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER, -}; - -static __init int __init ocelot_g_pci_init(void) -{ - unsigned long io_v_base; - - if (gt_io_size) { - io_v_base = (unsigned long) ioremap(gt_io_base, gt_io_size); - if (!io_v_base) - panic("Could not ioremap I/O port range"); - - set_io_port_base(io_v_base); - } - - register_pci_controller(>_bus0_controller.pcic); - register_pci_controller(>_bus1_controller.pcic); - - return 0; -} - -arch_initcall(ocelot_g_pci_init); |