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authorKumar Gala <galak@kernel.crashing.org>2008-05-30 13:43:43 -0500
committerKumar Gala <galak@kernel.crashing.org>2008-06-02 14:44:25 -0500
commitc054065bc10a7ee2bcf78b5bc95f4b4d9bdc923a (patch)
tree023b60c1b55c04c2db08983a3aaef151d081fcac /arch/powerpc/boot/dts/tqm8540.dts
parentacd4b715ec83e451990bb82bdbf28ecaeab1b67d (diff)
[POWERPC] 85xx: Add next-level-cache property
Added next-level-cache to the L1 and a reference to the new L2 label. This is per the ePAPR 0.94 spec. Since we are't really dependent on this today we aren't supporting the "legacy" l2-cache phandle that is specified in the PPC v2.1 OF Binding spec. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/boot/dts/tqm8540.dts')
-rw-r--r--arch/powerpc/boot/dts/tqm8540.dts3
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/powerpc/boot/dts/tqm8540.dts b/arch/powerpc/boot/dts/tqm8540.dts
index 8ee4664c749..7b653a583a2 100644
--- a/arch/powerpc/boot/dts/tqm8540.dts
+++ b/arch/powerpc/boot/dts/tqm8540.dts
@@ -40,6 +40,7 @@
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
+ next-level-cache = <&L2>;
};
};
@@ -64,7 +65,7 @@
interrupts = <18 2>;
};
- l2-cache-controller@20000 {
+ L2: l2-cache-controller@20000 {
compatible = "fsl,8540-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <32>;