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authorVictor Gallardo <vgallardo@amcc.com>2008-09-18 12:41:26 +0000
committerDavid S. Miller <davem@davemloft.net>2008-10-08 15:27:14 -0700
commit6fbc779c03591ee536fef9efb7d7e20f281d0b5c (patch)
tree2721ba739886a19f600082c97aeba48a6358f680 /arch/powerpc/include/asm
parentc6d6a511d768cf7627ab54fc18f40edf85097362 (diff)
ibm_newemac: Fix EMAC soft reset on 460EX/GT
This patch fixes EMAC soft reset on 460EX/GT when no external clock is available. Signed-off-by: Victor Gallardo <vgallardo@amcc.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch/powerpc/include/asm')
-rw-r--r--arch/powerpc/include/asm/dcr-regs.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/dcr-regs.h b/arch/powerpc/include/asm/dcr-regs.h
index 29b0ecef980..f15296cf359 100644
--- a/arch/powerpc/include/asm/dcr-regs.h
+++ b/arch/powerpc/include/asm/dcr-regs.h
@@ -68,6 +68,10 @@
#define SDR0_UART3 0x0123
#define SDR0_CUST0 0x4000
+/* SDRs (460EX/460GT) */
+#define SDR0_ETH_CFG 0x4103
+#define SDR0_ETH_CFG_ECS 0x00000100 /* EMAC int clk source */
+
/*
* All those DCR register addresses are offsets from the base address
* for the SRAM0 controller (e.g. 0x20 on 440GX). The base address is