Merge branch 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc

* 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc: (27 commits)
  [POWERPC] 83xx: Update mpc8349emitx(gp) defconfig for USB
  [POWERPC] 83xx: Update mpc832x_rdb_defconfig to enable MMC-over-SPI
  [POWERPC] 83xx: MPC832x RDB - remove spidev stub, use mmc_spi
  [POWERPC] 8xxx: MDS board RTC fixes
  [POWERPC] Fix 8xx build breakage due to _tlbie changes
  [POWERPC] Fix device tree interrupt map for Freescale ULI1575 boards
  [POWERPC] Fix possible division by zero in scaled time accounting
  [POWERPC] spufs: Fix context destroy vs /spu readdir race
  [POWERPC] Fix RTAS os-term usage on kernel panic
  [POWERPC] 83xx: Handle mpc8360 rev. 2.1 RGMII timing erratum
  [POWERPC] Document rgmii-rxid and rgmii-txid phy-connection-types
  [POWERPC] 83xx: Fix 2nd UCC entry in mpc832x_mds.dts
  [POWERPC] 83xx: mpc832x mds: Fix board PHY reset code
  [POWERPC] Fix potential NULL dereference
  [POWERPC] vdso: Fixes for cache block sizes
  [POWERPC] pasemi: Don't reset mpic at boot
  [POWERPC] Fix kmalloc alignment on non-coherent DMA platforms
  [POWERPC] Fix build failure on legacy iSeries
  [POWERPC] 4xx: Use virtual PVR value to init FPU on arch/ppc 440EP
  [POWERPC] 4xx: UIC add mask_ack callback
  ...

1 files changed, 29 insertions, 12 deletions

diff --git a/arch/powerpc/kernel/vdso32/cacheflush.S b/arch/powerpc/kernel/vdso32/cacheflush.S
index 9cb319992c3..1ba6feb71b3 100644
--- a/arch/powerpc/kernel/vdso32/cacheflush.S
+++ b/arch/powerpc/kernel/vdso32/cacheflush.S
@@ -23,29 +23,46 @@
  *
  * Flushes the data cache & invalidate the instruction cache for the
  * provided range [start, end[
- *
- * Note: all CPUs supported by this kernel have a 128 bytes cache
- * line size so we don't have to peek that info from the datapage
  */
 V_FUNCTION_BEGIN(__kernel_sync_dicache)
   .cfi_startproc
-	li	r5,127
-	andc	r6,r3,r5		/* round low to line bdy */
+	mflr	r12
+  .cfi_register lr,r12
+	mr	r11,r3
+	bl	__get_datapage@local
+	mtlr	r12
+	mr	r10,r3
+
+	lwz	r7,CFG_DCACHE_BLOCKSZ(r10)
+	addi	r5,r7,-1
+	andc	r6,r11,r5		/* round low to line bdy */
 	subf	r8,r6,r4		/* compute length */
 	add	r8,r8,r5		/* ensure we get enough */
-	srwi.	r8,r8,7			/* compute line count */
+	lwz	r9,CFG_DCACHE_LOGBLOCKSZ(r10)
+	srw.	r8,r8,r9		/* compute line count */
 	crclr	cr0*4+so
 	beqlr				/* nothing to do? */
 	mtctr	r8
-	mr	r3,r6
-1:	dcbst	0,r3
-	addi	r3,r3,128
+1:	dcbst	0,r6
+	add	r6,r6,r7
 	bdnz	1b
 	sync
+
+/* Now invalidate the instruction cache */
+
+	lwz	r7,CFG_ICACHE_BLOCKSZ(r10)
+	addi	r5,r7,-1
+	andc	r6,r11,r5		/* round low to line bdy */
+	subf	r8,r6,r4		/* compute length */
+	add	r8,r8,r5
+	lwz	r9,CFG_ICACHE_LOGBLOCKSZ(r10)
+	srw.	r8,r8,r9		/* compute line count */
+	crclr	cr0*4+so
+	beqlr				/* nothing to do? */
 	mtctr	r8
-1:	icbi	0,r6
-	addi	r6,r6,128
-	bdnz	1b
+2:	icbi	0,r6
+	add	r6,r6,r7
+	bdnz	2b
 	isync
 	li	r3,0
 	blr