diff options
| author | Roy Zang <tie-fei.zang@freescale.com> | 2007-06-13 17:13:42 +0800 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2007-07-03 02:04:29 -0500 |
| commit | 68fb0d203f4f62c8d1ac24d8ef2473582d8ea9db (patch) | |
| tree | 616a6293121cafd2dc2ba83f46399cadf9f9dc5e /arch/powerpc | |
| parent | a4ecababf4f007940300374ff68ac10b96733586 (diff) | |
[POWERPC] 85xx: Fix 8548CDS reset bug
Begin with MPC8548 a new reset control register is added that asserts
HRESET_REQ to board logic.
This register is used for chip reset.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc')
| -rw-r--r-- | arch/powerpc/boot/dts/mpc8548cds.dts | 6 | ||||
| -rw-r--r-- | arch/powerpc/platforms/85xx/misc.c | 32 |
2 files changed, 38 insertions, 0 deletions
diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts index ad96381033c..0550a3c391a 100644 --- a/arch/powerpc/boot/dts/mpc8548cds.dts +++ b/arch/powerpc/boot/dts/mpc8548cds.dts @@ -177,6 +177,12 @@ interrupt-parent = <&mpic>; }; + global-utilities@e0000 { //global utilities reg + compatible = "fsl,mpc8548-guts"; + reg = <e0000 1000>; + fsl,has-rstcr; + }; + pci1: pci@8000 { interrupt-map-mask = <1f800 0 0 7>; interrupt-map = < diff --git a/arch/powerpc/platforms/85xx/misc.c b/arch/powerpc/platforms/85xx/misc.c index 3e62fcb04c1..4fe376e9c3b 100644 --- a/arch/powerpc/platforms/85xx/misc.c +++ b/arch/powerpc/platforms/85xx/misc.c @@ -13,11 +13,43 @@ #include <linux/irq.h> #include <linux/module.h> #include <asm/irq.h> +#include <asm/io.h> +#include <asm/prom.h> +#include <sysdev/fsl_soc.h> + +static __be32 __iomem *rstcr; extern void abort(void); +static int __init mpc85xx_rstcr(void) +{ + struct device_node *np; + np = of_find_node_by_name(NULL, "global-utilities"); + if ((np && of_get_property(np, "fsl,has-rstcr", NULL))) { + const u32 *prop = of_get_property(np, "reg", NULL); + if (prop) { + /* map reset control register + * 0xE00B0 is offset of reset control register + */ + rstcr = ioremap(get_immrbase() + *prop + 0xB0, 0xff); + if (!rstcr) + printk (KERN_EMERG "Error: reset control " + "register not mapped!\n"); + } + } else + printk (KERN_INFO "rstcr compatible register does not exist!\n"); + if (np) + of_node_put(np); + return 0; +} + +arch_initcall(mpc85xx_rstcr); + void mpc85xx_restart(char *cmd) { local_irq_disable(); + if (rstcr) + /* set reset control register */ + out_be32(rstcr, 0x2); /* HRESET_REQ */ abort(); } |