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| author | James Bottomley <jejb@mulgrave.il.steeleye.com> | 2006-06-10 13:47:26 -0500 |
|---|---|---|
| committer | James Bottomley <jejb@mulgrave.il.steeleye.com> | 2006-06-10 13:47:26 -0500 |
| commit | f0cd91a68acdc9b49d7f6738b514a426da627649 (patch) | |
| tree | 8ad73564015794197583b094217ae0a71e71e753 /arch/ppc/kernel/head_8xx.S | |
| parent | 60eef25701d25e99c991dd0f4a9f3832a0c3ad3e (diff) | |
| parent | 128e6ced247cda88f96fa9f2e4ba8b2c4a681560 (diff) | |
Merge ../linux-2.6
Diffstat (limited to 'arch/ppc/kernel/head_8xx.S')
| -rw-r--r-- | arch/ppc/kernel/head_8xx.S | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S index ec53c7d65f2..7a2f20583be 100644 --- a/arch/ppc/kernel/head_8xx.S +++ b/arch/ppc/kernel/head_8xx.S @@ -355,9 +355,7 @@ InstructionTLBMiss: . = 0x1200 DataStoreTLBMiss: -#ifdef CONFIG_8xx_CPU6 stw r3, 8(r0) -#endif DO_8xx_CPU6(0x3f80, r3) mtspr SPRN_M_TW, r10 /* Save a couple of working registers */ mfcr r10 @@ -417,9 +415,7 @@ DataStoreTLBMiss: lwz r11, 0(r0) mtcr r11 lwz r11, 4(r0) -#ifdef CONFIG_8xx_CPU6 lwz r3, 8(r0) -#endif rfi /* This is an instruction TLB error on the MPC8xx. This could be due |