diff options
| author | Robert Richter <robert.richter@amd.com> | 2009-05-25 17:59:06 +0200 |
|---|---|---|
| committer | Robert Richter <robert.richter@amd.com> | 2009-06-11 19:42:15 +0200 |
| commit | 42399adb239d4f1413899cc618ecf640779e79df (patch) | |
| tree | 8c7ed4b60b00be9faca1acd175dfe84beacddef5 /arch/x86/oprofile/op_model_ppro.c | |
| parent | 3370d358569755625aba4d9a846a040ce691d9ed (diff) | |
x86/oprofile: replace CTR_OVERFLOWED macros
The patch replaces all CTR_OVERFLOWED macros. 64 bit MSR functions and
64 bit counter values are used now. Thus, it will be easier to later
extend the models to use more than 32 bit width counters.
Signed-off-by: Robert Richter <robert.richter@amd.com>
Diffstat (limited to 'arch/x86/oprofile/op_model_ppro.c')
| -rw-r--r-- | arch/x86/oprofile/op_model_ppro.c | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/arch/x86/oprofile/op_model_ppro.c b/arch/x86/oprofile/op_model_ppro.c index 3092f998baf..82db396dc3e 100644 --- a/arch/x86/oprofile/op_model_ppro.c +++ b/arch/x86/oprofile/op_model_ppro.c @@ -26,8 +26,6 @@ static int num_counters = 2; static int counter_width = 32; -#define CTR_OVERFLOWED(n) (!((n) & (1ULL<<(counter_width-1)))) - #define MSR_PPRO_EVENTSEL_RESERVED ((0xFFFFFFFFULL<<32)|(1ULL<<21)) static u64 *reset_value; @@ -124,10 +122,10 @@ static int ppro_check_ctrs(struct pt_regs * const regs, if (!reset_value[i]) continue; rdmsrl(msrs->counters[i].addr, val); - if (CTR_OVERFLOWED(val)) { - oprofile_add_sample(regs, i); - wrmsrl(msrs->counters[i].addr, -reset_value[i]); - } + if (val & (1ULL << (counter_width - 1))) + continue; + oprofile_add_sample(regs, i); + wrmsrl(msrs->counters[i].addr, -reset_value[i]); } /* Only P6 based Pentium M need to re-unmask the apic vector but it |