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authorChen, Kenneth W <kenneth.w.chen@intel.com>2005-11-17 01:38:42 -0800
committerTony Luck <tony.luck@intel.com>2005-11-17 09:47:18 -0800
commitfedb25fae72bc2c3709448a43be067439643da87 (patch)
treea394188d38b6e1052d7c6abac7b4e17eda903bd5 /arch
parent6027994423e12a3c0b22d3dbf9ac87364ca4e0ec (diff)
[IA64] 4 level page table bug fix in vhpt_miss
From source code inspection, I think there is a bug with 4 level page table with vhpt_miss handler. In the code path of rechecking page table entry against previously read value after tlb insertion, *pte value in register r18 was overwritten with value newly read from pud pointer, render the check of new *pte against previous *pte completely wrong. Though the bug is none fatal and the penalty is to purge the entry and retry. For functional correctness, it should be fixed. The fix is to use a different register so new *pud don't trash *pte. (btw, the comments in the cmp statement is wrong as well, which I will address in the next patch). Signed-off-by: Ken Chen <kenneth.w.chen@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/ia64/kernel/ivt.S4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/ia64/kernel/ivt.S b/arch/ia64/kernel/ivt.S
index e06f21f60dc..c71c79262a4 100644
--- a/arch/ia64/kernel/ivt.S
+++ b/arch/ia64/kernel/ivt.S
@@ -209,13 +209,13 @@ ENTRY(vhpt_miss)
ld8 r25=[r21] // read L4 entry again
ld8 r26=[r17] // read L3 PTE again
#ifdef CONFIG_PGTABLE_4
- ld8 r18=[r28] // read L2 entry again
+ ld8 r19=[r28] // read L2 entry again
#endif
cmp.ne p6,p7=r0,r0
;;
cmp.ne.or.andcm p6,p7=r26,r20 // did L3 entry change
#ifdef CONFIG_PGTABLE_4
- cmp.ne.or.andcm p6,p7=r29,r18 // did L4 PTE change
+ cmp.ne.or.andcm p6,p7=r19,r29 // did L4 PTE change
#endif
mov r27=PAGE_SHIFT<<2
;;