diff options
| author | Naveen Gupta <ngupta@google.com> | 2005-08-17 09:11:46 +0200 |
|---|---|---|
| committer | Wim Van Sebroeck <wim@iguana.be> | 2005-09-11 21:51:18 +0200 |
| commit | ce2f50b4ae71f700c7b4b0bf0ff11c328611dae8 (patch) | |
| tree | 52570a06396baa2fa96eafe4b7403b9328b676ed /drivers/char/watchdog/i6300esb.h | |
| parent | 28562af3d4b21d687dd57c44006aeeed1036c781 (diff) | |
[WATCHDOG] i6300esb-set_correct_reload_register_bit
This patch writes into bit 8 of the reload register to perform the
correct 'Reload Sequence' instead of writing into bit 4 of Watchdog for
Intel 6300ESB chipset.
Signed-off-by: Naveen Gupta <ngupta@google.com>
Signed-off-by: David Hardeman <david@2gen.com>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Diffstat (limited to 'drivers/char/watchdog/i6300esb.h')
| -rw-r--r-- | drivers/char/watchdog/i6300esb.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/char/watchdog/i6300esb.h b/drivers/char/watchdog/i6300esb.h index b5b47e3dda1..20c923bbb1c 100644 --- a/drivers/char/watchdog/i6300esb.h +++ b/drivers/char/watchdog/i6300esb.h @@ -54,6 +54,8 @@ #define ESB_WDT_FREQ ( 0x01 << 2 ) /* Decrement frequency */ #define ESB_WDT_INTTYPE ( 0x11 << 0 ) /* Interrupt type on timer1 timeout */ +/* Reload register bits */ +#define ESB_WDT_RELOAD ( 0x01 << 8 ) /* prevent timeout */ /* * Some magic constants |