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author | Eric Anholt <eric@anholt.net> | 2009-06-21 22:14:55 -0700 |
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committer | Eric Anholt <eric@anholt.net> | 2009-06-21 22:33:15 -0700 |
commit | be9f1c4f738a715abbd8ea742f3ec60a1ce73f4b (patch) | |
tree | 0385b0a9af9a0996e3b8f01a317f3e1da8637ae8 /drivers/gpu/drm/i915/i915_reg.h | |
parent | 8c52da503b7e4cf961807f11824e3258ef9f7f1c (diff) | |
parent | fb0f8fbf97e8a25074c81c629500d94cafa9e366 (diff) |
Merge commit 'keithp/drm-intel-next' into drm-intel-next
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
-rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index f6237a0b113..544d5677a2f 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -569,6 +569,19 @@ #define C0DRB3 0x10206 #define C1DRB3 0x10606 +/* Clocking configuration register */ +#define CLKCFG 0x10c00 +#define CLKCFG_FSB_400 (0 << 0) /* hrawclk 100 */ +#define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */ +#define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */ +#define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */ +#define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */ +#define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */ +/* this is a guess, could be 5 as well */ +#define CLKCFG_FSB_1600 (4 << 0) /* hrawclk 400 */ +#define CLKCFG_FSB_1600_ALT (5 << 0) /* hrawclk 400 */ +#define CLKCFG_FSB_MASK (7 << 0) + /** GM965 GM45 render standby register */ #define MCHBAR_RENDER_STANDBY 0x111B8 |