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authorMichael Krufky <mkrufky@linuxtv.org>2008-04-22 14:46:23 -0300
committerMauro Carvalho Chehab <mchehab@infradead.org>2008-04-24 14:07:55 -0300
commit4efb0ca5d00f2c7a8bf9632556a4b4330cf409c5 (patch)
tree4ce1c38c66a64c590ef06403e6a38e2be7175772 /drivers/media/dvb/frontends/tda18271-fe.c
parent40194b2b1bdd01358c1e9b5a9b8dd78390cc05f7 (diff)
V4L/DVB (7435): tda18271: add function tda18271_charge_pump_source
Force the main pll charge pump or cal pll charge pump to source current to the main pll loop filter or cal pll loop filter, respectively. Signed-off-by: Michael Krufky <mkrufky@linuxtv.org> Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
Diffstat (limited to 'drivers/media/dvb/frontends/tda18271-fe.c')
-rw-r--r--drivers/media/dvb/frontends/tda18271-fe.c18
1 files changed, 6 insertions, 12 deletions
diff --git a/drivers/media/dvb/frontends/tda18271-fe.c b/drivers/media/dvb/frontends/tda18271-fe.c
index b3b0425dbbe..46905a773e4 100644
--- a/drivers/media/dvb/frontends/tda18271-fe.c
+++ b/drivers/media/dvb/frontends/tda18271-fe.c
@@ -119,14 +119,12 @@ static int tda18271_channel_configuration(struct dvb_frontend *fe,
tda18271_write_regs(fe, R_TM, 7);
/* main pll charge pump source */
- regs[R_EB4] |= 0x20;
- tda18271_write_regs(fe, R_EB4, 1);
+ tda18271_charge_pump_source(fe, TDA18271_MAIN_PLL, 1);
msleep(1);
/* normal operation for the main pll */
- regs[R_EB4] &= ~0x20;
- tda18271_write_regs(fe, R_EB4, 1);
+ tda18271_charge_pump_source(fe, TDA18271_MAIN_PLL, 0);
msleep(20);
@@ -285,12 +283,10 @@ static int tda18271_calibrate_rf(struct dvb_frontend *fe, u32 freq)
tda18271_write_regs(fe, R_EB13, 1);
/* main pll charge pump source */
- regs[R_EB4] |= 0x20;
- tda18271_write_regs(fe, R_EB4, 1);
+ tda18271_charge_pump_source(fe, TDA18271_MAIN_PLL, 1);
/* cal pll charge pump source */
- regs[R_EB7] |= 0x20;
- tda18271_write_regs(fe, R_EB7, 1);
+ tda18271_charge_pump_source(fe, TDA18271_CAL_PLL, 1);
/* force dcdc converter to 0 V */
regs[R_EB14] = 0x00;
@@ -328,12 +324,10 @@ static int tda18271_calibrate_rf(struct dvb_frontend *fe, u32 freq)
/* --------------------------------------------------------------- */
/* normal operation for the main pll */
- regs[R_EB4] &= ~0x20;
- tda18271_write_regs(fe, R_EB4, 1);
+ tda18271_charge_pump_source(fe, TDA18271_MAIN_PLL, 0);
/* normal operation for the cal pll */
- regs[R_EB7] &= ~0x20;
- tda18271_write_regs(fe, R_EB7, 1);
+ tda18271_charge_pump_source(fe, TDA18271_CAL_PLL, 0);
msleep(10); /* plls locking */