diff options
author | Andy Walls <awalls@radix.net> | 2010-01-03 23:28:18 -0300 |
---|---|---|
committer | Mauro Carvalho Chehab <mchehab@redhat.com> | 2010-02-26 15:10:30 -0300 |
commit | f05b7f5ee19de6de972020ea18e6c30b672d401b (patch) | |
tree | 7e51166d129f564784672186a7217b94cb75e770 /drivers/media | |
parent | a8073119d69d0b4aa8f445ed4d7d56b89b602708 (diff) |
V4L/DVB (13913): saa7127: Add support for generating SECAM output for the SAA712[89] chips
This change fixes up saa7127_s_std() generate SECAM out, if the user has
requested a 50 Hz video standard set that only contains a request for SECAM
standards and not PAL. Only the SAA712[89] chips can generate SECAM, the
SAA712[67] chips cannot.
I was unclear on the burst start and end values - I couldn't figure out
the units - so I left them the same as for the PAL systems.
A the video decoders on both a PVR-350 (SAA7115) and an HVR-1600 (CX23418)
identify the SECAM signal generated by a SAA7129 with this patch as SECAM.
Signed-off-by: Andy Walls <awalls@radix.net>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/media')
-rw-r--r-- | drivers/media/video/saa7127.c | 47 |
1 files changed, 40 insertions, 7 deletions
diff --git a/drivers/media/video/saa7127.c b/drivers/media/video/saa7127.c index 2fe7a701b95..250ef84cf5c 100644 --- a/drivers/media/video/saa7127.c +++ b/drivers/media/video/saa7127.c @@ -181,7 +181,7 @@ static const struct i2c_reg_value saa7127_init_config_common[] = { #define SAA7127_60HZ_DAC_CONTROL 0x15 static const struct i2c_reg_value saa7127_init_config_60hz[] = { { SAA7127_REG_BURST_START, 0x19 }, - /* BURST_END is also used as a chip ID in saa7127_detect_client */ + /* BURST_END is also used as a chip ID in saa7127_probe */ { SAA7127_REG_BURST_END, 0x1d }, { SAA7127_REG_CHROMA_PHASE, 0xa3 }, { SAA7127_REG_GAINU, 0x98 }, @@ -200,10 +200,10 @@ static const struct i2c_reg_value saa7127_init_config_60hz[] = { { 0, 0 } }; -#define SAA7127_50HZ_DAC_CONTROL 0x02 -static struct i2c_reg_value saa7127_init_config_50hz[] = { +#define SAA7127_50HZ_PAL_DAC_CONTROL 0x02 +static struct i2c_reg_value saa7127_init_config_50hz_pal[] = { { SAA7127_REG_BURST_START, 0x21 }, - /* BURST_END is also used as a chip ID in saa7127_detect_client */ + /* BURST_END is also used as a chip ID in saa7127_probe */ { SAA7127_REG_BURST_END, 0x1d }, { SAA7127_REG_CHROMA_PHASE, 0x3f }, { SAA7127_REG_GAINU, 0x7d }, @@ -222,6 +222,28 @@ static struct i2c_reg_value saa7127_init_config_50hz[] = { { 0, 0 } }; +#define SAA7127_50HZ_SECAM_DAC_CONTROL 0x08 +static struct i2c_reg_value saa7127_init_config_50hz_secam[] = { + { SAA7127_REG_BURST_START, 0x21 }, + /* BURST_END is also used as a chip ID in saa7127_probe */ + { SAA7127_REG_BURST_END, 0x1d }, + { SAA7127_REG_CHROMA_PHASE, 0x3f }, + { SAA7127_REG_GAINU, 0x6a }, + { SAA7127_REG_GAINV, 0x81 }, + { SAA7127_REG_BLACK_LEVEL, 0x33 }, + { SAA7127_REG_BLANKING_LEVEL, 0x35 }, + { SAA7127_REG_VBI_BLANKING, 0x35 }, + { SAA7127_REG_DAC_CONTROL, 0x08 }, + { SAA7127_REG_BURST_AMP, 0x2f }, + { SAA7127_REG_SUBC3, 0xb2 }, + { SAA7127_REG_SUBC2, 0x3b }, + { SAA7127_REG_SUBC1, 0xa3 }, + { SAA7127_REG_SUBC0, 0x28 }, + { SAA7127_REG_MULTI, 0x90 }, + { SAA7127_REG_CLOSED_CAPTION, 0x00 }, + { 0, 0 } +}; + /* ********************************************************************** * @@ -463,10 +485,21 @@ static int saa7127_set_std(struct v4l2_subdev *sd, v4l2_std_id std) v4l2_dbg(1, debug, sd, "Selecting 60 Hz video Standard\n"); inittab = saa7127_init_config_60hz; state->reg_61 = SAA7127_60HZ_DAC_CONTROL; + + } else if (state->ident == V4L2_IDENT_SAA7129 && + (std & V4L2_STD_SECAM) && + !(std & (V4L2_STD_625_50 & ~V4L2_STD_SECAM))) { + + /* If and only if SECAM, with a SAA712[89] */ + v4l2_dbg(1, debug, sd, + "Selecting 50 Hz SECAM video Standard\n"); + inittab = saa7127_init_config_50hz_secam; + state->reg_61 = SAA7127_50HZ_SECAM_DAC_CONTROL; + } else { - v4l2_dbg(1, debug, sd, "Selecting 50 Hz video Standard\n"); - inittab = saa7127_init_config_50hz; - state->reg_61 = SAA7127_50HZ_DAC_CONTROL; + v4l2_dbg(1, debug, sd, "Selecting 50 Hz PAL video Standard\n"); + inittab = saa7127_init_config_50hz_pal; + state->reg_61 = SAA7127_50HZ_PAL_DAC_CONTROL; } /* Write Table */ |