diff options
| author | Russell King <rmk@dyn-67.arm.linux.org.uk> | 2006-09-27 19:57:54 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2006-09-27 19:57:54 +0100 |
| commit | 2dc94310bd94d0906febea7d0f7c188da620c952 (patch) | |
| tree | 6de4096f1887e2c00966177354b1c378e59bd632 /drivers/net/ewrk3.h | |
| parent | c06015148fa9a3cc452ec7121b8c3f59f4a7d6ac (diff) | |
| parent | fb60cf4ab52f3520c2119aa42f7d4ed8e7594eb6 (diff) | |
Merge master.kernel.org:/pub/scm/linux/kernel/git/tmlind/linux-omap-upstream into devel
Diffstat (limited to 'drivers/net/ewrk3.h')
| -rw-r--r-- | drivers/net/ewrk3.h | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/drivers/net/ewrk3.h b/drivers/net/ewrk3.h index fb74bd05367..8e0ee906567 100644 --- a/drivers/net/ewrk3.h +++ b/drivers/net/ewrk3.h @@ -63,7 +63,7 @@ */ #define CSR_RA 0x80 /* Runt Accept */ #define CSR_PME 0x40 /* Promiscuous Mode Enable */ -#define CSR_MCE 0x20 /* Multicast Enable */ +#define CSR_MCE 0x20 /* Multicast Enable */ #define CSR_TNE 0x08 /* TX Done Queue Not Empty */ #define CSR_RNE 0x04 /* RX Queue Not Empty */ #define CSR_TXD 0x02 /* TX Disable */ @@ -127,7 +127,7 @@ #define CMR_DRAM 0x02 /* 0-> 1DRAM, 1-> 2 DRAM on board */ #define CMR_0WS 0x01 /* Zero Wait State */ -/* +/* ** MAC Receive Status Register bit definitions */ @@ -138,7 +138,7 @@ #define R_CRC 0x02 /* CRC error */ #define R_PLL 0x01 /* Phase Lock Lost */ -/* +/* ** MAC Transmit Control Register bit definitions */ @@ -150,7 +150,7 @@ #define TCR_IFC 0x02 /* Insert Frame Check */ #define TCR_ISA 0x01 /* Insert Source Address */ -/* +/* ** MAC Transmit Status Register bit definitions */ @@ -168,15 +168,15 @@ #define T_XUR 0x03 /* Excessive Underruns */ #define T_TXE 0x7f /* TX Errors */ -/* -** EISA Configuration Register bit definitions +/* +** EISA Configuration Register bit definitions */ -#define EISA_ID iobase + 0x0c80 /* EISA ID Registers */ -#define EISA_ID0 iobase + 0x0c80 /* EISA ID Register 0 */ -#define EISA_ID1 iobase + 0x0c81 /* EISA ID Register 1 */ -#define EISA_ID2 iobase + 0x0c82 /* EISA ID Register 2 */ -#define EISA_ID3 iobase + 0x0c83 /* EISA ID Register 3 */ +#define EISA_ID iobase + 0x0c80 /* EISA ID Registers */ +#define EISA_ID0 iobase + 0x0c80 /* EISA ID Register 0 */ +#define EISA_ID1 iobase + 0x0c81 /* EISA ID Register 1 */ +#define EISA_ID2 iobase + 0x0c82 /* EISA ID Register 2 */ +#define EISA_ID3 iobase + 0x0c83 /* EISA ID Register 3 */ #define EISA_CR iobase + 0x0c84 /* EISA Control Register */ /* @@ -223,7 +223,7 @@ /* ** EEPROM MISCELLANEOUS FLAGS */ -#define RBE_SHADOW 0x0100 /* Remote Boot Enable Shadow */ +#define RBE_SHADOW 0x0100 /* Remote Boot Enable Shadow */ #define READ_AHEAD 0x0080 /* Read Ahead feature */ #define IRQ_SEL2 0x0070 /* IRQ line selection (LeMAC2) */ #define IRQ_SEL 0x0060 /* IRQ line selection */ @@ -242,7 +242,7 @@ /* ** EEPROM SW FLAGS */ -#define SW_SQE 0x10 /* Signal Quality Error */ +#define SW_SQE 0x10 /* Signal Quality Error */ #define SW_LAB 0x08 /* Less Aggressive Backoff */ #define SW_INIT 0x04 /* Initialized */ #define SW_TIMEOUT 0x02 /* 0:2.5 mins, 1: 30 secs */ @@ -299,8 +299,8 @@ struct ewrk3_ioctl { unsigned char __user *data; /* Pointer to the data buffer */ }; -/* -** Recognised commands for the driver +/* +** Recognised commands for the driver */ #define EWRK3_GET_HWADDR 0x01 /* Get the hardware address */ #define EWRK3_SET_HWADDR 0x02 /* Get the hardware address */ |