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authorBrice Goglin <brice@myri.com>2006-08-31 01:32:59 -0400
committerJeff Garzik <jeff@garzik.org>2006-09-06 11:06:46 -0400
commitce7f93680aa1d37171c654536ae0ce9745d86a24 (patch)
tree7c88e6ebafbcdf5c0a89feb82b572a5ea4e6d000 /drivers/net
parentb4d01327e4c05ab555a4cf38a33f4b4fa2f75e64 (diff)
[PATCH] myri10ge: improve firmware selection
Improve the firmware selection by adding 2 cases where we should use the optimized firmware: * when the actual PCIe link width is lower than 8x. * when the board is plugged to one of the new Intel PCIe chipsets that are known to provide aligned PCIe completions. The patch actually raises two concerns: * We might want to add a generic PCI function to get the PCIe link width since some other drivers (at least ipath) do the same. But we probably do not want to add a new function for every PCIe capability. I will probably look at it and discuss it on linux-pci in the future. * As requested during the submission, the PCI ids of chipsets that are known to provided aligned completion are defined in the myri10ge code. If we keep adding new ones, it might become better to move them to pciids.h. But, this sort of quirk to detect these chipsets are very specific to our NIC, I don't think it is worth moving it to the PCI core until somebody else really needs it. Signed-off-by: Brice Goglin <brice@myri.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/myri10ge/myri10ge.c35
1 files changed, 28 insertions, 7 deletions
diff --git a/drivers/net/myri10ge/myri10ge.c b/drivers/net/myri10ge/myri10ge.c
index e2346e8a4d5..b19e2034d11 100644
--- a/drivers/net/myri10ge/myri10ge.c
+++ b/drivers/net/myri10ge/myri10ge.c
@@ -2417,6 +2417,8 @@ static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp)
*/
#define PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE 0x0132
+#define PCI_DEVICE_ID_INTEL_E5000_PCIE23 0x25f7
+#define PCI_DEVICE_ID_INTEL_E5000_PCIE47 0x25fa
static void myri10ge_select_firmware(struct myri10ge_priv *mgp)
{
@@ -2426,15 +2428,34 @@ static void myri10ge_select_firmware(struct myri10ge_priv *mgp)
mgp->fw_name = myri10ge_fw_unaligned;
if (myri10ge_force_firmware == 0) {
+ int link_width, exp_cap;
+ u16 lnk;
+
+ exp_cap = pci_find_capability(mgp->pdev, PCI_CAP_ID_EXP);
+ pci_read_config_word(mgp->pdev, exp_cap + PCI_EXP_LNKSTA, &lnk);
+ link_width = (lnk >> 4) & 0x3f;
+
myri10ge_enable_ecrc(mgp);
- /* Check to see if the upstream bridge is known to
- * provide aligned completions */
- if (bridge
- /* ServerWorks HT2000/HT1000 */
- && bridge->vendor == PCI_VENDOR_ID_SERVERWORKS
- && bridge->device ==
- PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE) {
+ /* Check to see if Link is less than 8 or if the
+ * upstream bridge is known to provide aligned
+ * completions */
+ if (link_width < 8) {
+ dev_info(&mgp->pdev->dev, "PCIE x%d Link\n",
+ link_width);
+ mgp->tx.boundary = 4096;
+ mgp->fw_name = myri10ge_fw_aligned;
+ } else if (bridge &&
+ /* ServerWorks HT2000/HT1000 */
+ ((bridge->vendor == PCI_VENDOR_ID_SERVERWORKS
+ && bridge->device ==
+ PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE)
+ /* All Intel E5000 PCIE ports */
+ || (bridge->vendor == PCI_VENDOR_ID_INTEL
+ && bridge->device >=
+ PCI_DEVICE_ID_INTEL_E5000_PCIE23
+ && bridge->device <=
+ PCI_DEVICE_ID_INTEL_E5000_PCIE47))) {
dev_info(&mgp->pdev->dev,
"Assuming aligned completions (0x%x:0x%x)\n",
bridge->vendor, bridge->device);