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| author | Keith Packard <keithp@keithp.com> | 2009-06-11 22:31:31 -0700 |
|---|---|---|
| committer | Keith Packard <keithp@keithp.com> | 2009-06-18 15:54:14 -0700 |
| commit | fb0f8fbf97e8a25074c81c629500d94cafa9e366 (patch) | |
| tree | 61998d92216f4d23cda286853d0e5e5fe1397bc9 /drivers/staging/agnx/pci.c | |
| parent | a5b3da543d4882d57a2f3e05d37ad8e1e1453489 (diff) | |
drm/i915: Generate 2MHz clock for display port aux channel I/O. Retry I/O.
The display port aux channel clock is taken from the hrawclk value, which is
provided to the chip as the FSB frequency (as far as I can determine). The
strapping values for that are available in the CLKCFG register, now used to
select an appropriate divider to generate a 2MHz clock.
In addition, the DisplayPort spec requires that each aux channel I/O be
retried 'at least 3 times' in case the sink is idle when the first request
comes in.
Signed-off-by: Keith Packard <keithp@keithp.com>
Diffstat (limited to 'drivers/staging/agnx/pci.c')
0 files changed, 0 insertions, 0 deletions