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authorLinus Torvalds <torvalds@linux-foundation.org>2009-06-16 13:06:10 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2009-06-16 13:06:10 -0700
commite1f5b94fd0c93c3e27ede88b7ab652d086dc960f (patch)
treee8de7a132eb88521dd1c19e128eba2d5349bdf4f /drivers/usb/gadget
parent6fd03301d76bc439382710e449f58efbb233df1b (diff)
parent1b6ed69f974f6f32c8be0d9a7fc952822eb83b6f (diff)
Merge git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb-2.6
* git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb-2.6: (143 commits) USB: xhci depends on PCI. USB: xhci: Add Makefile, MAINTAINERS, and Kconfig entries. USB: xhci: Respect critical sections. USB: xHCI: Fix interrupt moderation. USB: xhci: Remove packed attribute from structures. usb; xhci: Fix TRB offset calculations. USB: xhci: replace if-elseif-else with switch-case USB: xhci: Make xhci-mem.c include linux/dmapool.h USB: xhci: drop spinlock in xhci_urb_enqueue() error path. USB: Change names of SuperSpeed ep companion descriptor structs. USB: xhci: Avoid compiler reordering in Link TRB giveback. USB: xhci: Clean up xhci_irq() function. USB: xhci: Avoid global namespace pollution. USB: xhci: Fix Link TRB handoff bit twiddling. USB: xhci: Fix register write order. USB: xhci: fix some compiler warnings in xhci.h USB: xhci: fix lots of compiler warnings. USB: xhci: use xhci_handle_event instead of handle_event USB: xhci: URB cancellation support. USB: xhci: Scatter gather list support for bulk transfers. ...
Diffstat (limited to 'drivers/usb/gadget')
-rw-r--r--drivers/usb/gadget/Kconfig53
-rw-r--r--drivers/usb/gadget/Makefile8
-rw-r--r--drivers/usb/gadget/at91_udc.c4
-rw-r--r--drivers/usb/gadget/atmel_usba_udc.c20
-rw-r--r--drivers/usb/gadget/audio.c302
-rw-r--r--drivers/usb/gadget/ci13xxx_udc.c6
-rw-r--r--drivers/usb/gadget/f_audio.c707
-rw-r--r--drivers/usb/gadget/f_rndis.c4
-rw-r--r--drivers/usb/gadget/file_storage.c93
-rw-r--r--drivers/usb/gadget/fsl_mx3_udc.c95
-rw-r--r--drivers/usb/gadget/fsl_udc_core.c (renamed from drivers/usb/gadget/fsl_usb2_udc.c)69
-rw-r--r--drivers/usb/gadget/fsl_usb2_udc.h18
-rw-r--r--drivers/usb/gadget/gadget_chips.h8
-rw-r--r--drivers/usb/gadget/goku_udc.c6
-rw-r--r--drivers/usb/gadget/imx_udc.c14
-rw-r--r--drivers/usb/gadget/inode.c14
-rw-r--r--drivers/usb/gadget/langwell_udc.c3373
-rw-r--r--drivers/usb/gadget/langwell_udc.h228
-rw-r--r--drivers/usb/gadget/pxa27x_udc.c71
-rw-r--r--drivers/usb/gadget/pxa27x_udc.h2
-rw-r--r--drivers/usb/gadget/s3c-hsotg.c3269
-rw-r--r--drivers/usb/gadget/u_audio.c319
-rw-r--r--drivers/usb/gadget/u_audio.h56
-rw-r--r--drivers/usb/gadget/u_serial.c1
24 files changed, 8617 insertions, 123 deletions
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index 080bb1e4b84..5d1ddf485d1 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -156,7 +156,7 @@ config USB_ATMEL_USBA
config USB_GADGET_FSL_USB2
boolean "Freescale Highspeed USB DR Peripheral Controller"
- depends on FSL_SOC
+ depends on FSL_SOC || ARCH_MXC
select USB_GADGET_DUALSPEED
help
Some of Freescale PowerPC processors have a High Speed
@@ -253,7 +253,7 @@ config USB_PXA25X_SMALL
config USB_GADGET_PXA27X
boolean "PXA 27x"
- depends on ARCH_PXA && PXA27x
+ depends on ARCH_PXA && (PXA27x || PXA3xx)
select USB_OTG_UTILS
help
Intel's PXA 27x series XScale ARM v5TE processors include
@@ -272,6 +272,20 @@ config USB_PXA27X
default USB_GADGET
select USB_GADGET_SELECTED
+config USB_GADGET_S3C_HSOTG
+ boolean "S3C HS/OtG USB Device controller"
+ depends on S3C_DEV_USB_HSOTG
+ select USB_GADGET_S3C_HSOTG_PIO
+ help
+ The Samsung S3C64XX USB2.0 high-speed gadget controller
+ integrated into the S3C64XX series SoC.
+
+config USB_S3C_HSOTG
+ tristate
+ depends on USB_GADGET_S3C_HSOTG
+ default USB_GADGET
+ select USB_GADGET_SELECTED
+
config USB_GADGET_S3C2410
boolean "S3C2410 USB Device Controller"
depends on ARCH_S3C2410
@@ -460,6 +474,27 @@ config USB_GOKU
default USB_GADGET
select USB_GADGET_SELECTED
+config USB_GADGET_LANGWELL
+ boolean "Intel Langwell USB Device Controller"
+ depends on PCI
+ select USB_GADGET_DUALSPEED
+ help
+ Intel Langwell USB Device Controller is a High-Speed USB
+ On-The-Go device controller.
+
+ The number of programmable endpoints is different through
+ controller revision.
+
+ Say "y" to link the driver statically, or "m" to build a
+ dynamically linked module called "langwell_udc" and force all
+ gadget drivers to also be dynamically linked.
+
+config USB_LANGWELL
+ tristate
+ depends on USB_GADGET_LANGWELL
+ default USB_GADGET
+ select USB_GADGET_SELECTED
+
#
# LAST -- dummy/emulated controller
@@ -566,6 +601,20 @@ config USB_ZERO_HNPTEST
the "B-Peripheral" role, that device will use HNP to let this
one serve as the USB host instead (in the "B-Host" role).
+config USB_AUDIO
+ tristate "Audio Gadget (EXPERIMENTAL)"
+ depends on SND
+ help
+ Gadget Audio is compatible with USB Audio Class specification 1.0.
+ It will include at least one AudioControl interface, zero or more
+ AudioStream interface and zero or more MIDIStream interface.
+
+ Gadget Audio will use on-board ALSA (CONFIG_SND) audio card to
+ playback or capture audio stream.
+
+ Say "y" to link the driver statically, or "m" to build a
+ dynamically linked module called "g_audio".
+
config USB_ETH
tristate "Ethernet Gadget (with CDC Ethernet support)"
depends on NET
diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile
index 39a51d746cb..e6017e6bf6d 100644
--- a/drivers/usb/gadget/Makefile
+++ b/drivers/usb/gadget/Makefile
@@ -18,14 +18,21 @@ obj-$(CONFIG_USB_S3C2410) += s3c2410_udc.o
obj-$(CONFIG_USB_AT91) += at91_udc.o
obj-$(CONFIG_USB_ATMEL_USBA) += atmel_usba_udc.o
obj-$(CONFIG_USB_FSL_USB2) += fsl_usb2_udc.o
+fsl_usb2_udc-objs := fsl_udc_core.o
+ifeq ($(CONFIG_ARCH_MXC),y)
+fsl_usb2_udc-objs += fsl_mx3_udc.o
+endif
obj-$(CONFIG_USB_M66592) += m66592-udc.o
obj-$(CONFIG_USB_FSL_QE) += fsl_qe_udc.o
obj-$(CONFIG_USB_CI13XXX) += ci13xxx_udc.o
+obj-$(CONFIG_USB_S3C_HSOTG) += s3c-hsotg.o
+obj-$(CONFIG_USB_LANGWELL) += langwell_udc.o
#
# USB gadget drivers
#
g_zero-objs := zero.o
+g_audio-objs := audio.o
g_ether-objs := ether.o
g_serial-objs := serial.o
g_midi-objs := gmidi.o
@@ -35,6 +42,7 @@ g_printer-objs := printer.o
g_cdc-objs := cdc2.o
obj-$(CONFIG_USB_ZERO) += g_zero.o
+obj-$(CONFIG_USB_AUDIO) += g_audio.o
obj-$(CONFIG_USB_ETH) += g_ether.o
obj-$(CONFIG_USB_GADGETFS) += gadgetfs.o
obj-$(CONFIG_USB_FILE_STORAGE) += g_file_storage.o
diff --git a/drivers/usb/gadget/at91_udc.c b/drivers/usb/gadget/at91_udc.c
index 53bcdd2f828..72bae8f39d8 100644
--- a/drivers/usb/gadget/at91_udc.c
+++ b/drivers/usb/gadget/at91_udc.c
@@ -485,7 +485,7 @@ static int at91_ep_enable(struct usb_ep *_ep,
return -ESHUTDOWN;
}
- tmp = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
+ tmp = usb_endpoint_type(desc);
switch (tmp) {
case USB_ENDPOINT_XFER_CONTROL:
DBG("only one control endpoint\n");
@@ -517,7 +517,7 @@ ok:
local_irq_save(flags);
/* initialize endpoint to match this descriptor */
- ep->is_in = (desc->bEndpointAddress & USB_DIR_IN) != 0;
+ ep->is_in = usb_endpoint_dir_in(desc);
ep->is_iso = (tmp == USB_ENDPOINT_XFER_ISOC);
ep->stopped = 0;
if (ep->is_in)
diff --git a/drivers/usb/gadget/atmel_usba_udc.c b/drivers/usb/gadget/atmel_usba_udc.c
index 05c913cc365..4e970cf0e29 100644
--- a/drivers/usb/gadget/atmel_usba_udc.c
+++ b/drivers/usb/gadget/atmel_usba_udc.c
@@ -326,13 +326,7 @@ static int vbus_is_present(struct usba_udc *udc)
return 1;
}
-#if defined(CONFIG_AVR32)
-
-static void toggle_bias(int is_on)
-{
-}
-
-#elif defined(CONFIG_ARCH_AT91)
+#if defined(CONFIG_ARCH_AT91SAM9RL)
#include <mach/at91_pmc.h>
@@ -346,7 +340,13 @@ static void toggle_bias(int is_on)
at91_sys_write(AT91_CKGR_UCKR, uckr & ~(AT91_PMC_BIASEN));
}
-#endif /* CONFIG_ARCH_AT91 */
+#else
+
+static void toggle_bias(int is_on)
+{
+}
+
+#endif /* CONFIG_ARCH_AT91SAM9RL */
static void next_fifo_transaction(struct usba_ep *ep, struct usba_request *req)
{
@@ -550,12 +550,12 @@ usba_ep_enable(struct usb_ep *_ep, const struct usb_endpoint_descriptor *desc)
DBG(DBG_HW, "%s: EPT_SIZE = %lu (maxpacket = %lu)\n",
ep->ep.name, ept_cfg, maxpacket);
- if ((desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) {
+ if (usb_endpoint_dir_in(desc)) {
ep->is_in = 1;
ept_cfg |= USBA_EPT_DIR_IN;
}
- switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
+ switch (usb_endpoint_type(desc)) {
case USB_ENDPOINT_XFER_CONTROL:
ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_CONTROL);
ept_cfg |= USBA_BF(BK_NUMBER, USBA_BK_NUMBER_ONE);
diff --git a/drivers/usb/gadget/audio.c b/drivers/usb/gadget/audio.c
new file mode 100644
index 00000000000..94de7e86461
--- /dev/null
+++ b/drivers/usb/gadget/audio.c
@@ -0,0 +1,302 @@
+/*
+ * audio.c -- Audio gadget driver
+ *
+ * Copyright (C) 2008 Bryan Wu <cooloney@kernel.org>
+ * Copyright (C) 2008 Analog Devices, Inc
+ *
+ * Enter bugs at http://blackfin.uclinux.org/
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+/* #define VERBOSE_DEBUG */
+
+#include <linux/kernel.h>
+#include <linux/utsname.h>
+
+#include "u_audio.h"
+
+#define DRIVER_DESC "Linux USB Audio Gadget"
+#define DRIVER_VERSION "Dec 18, 2008"
+
+/*-------------------------------------------------------------------------*/
+
+/*
+ * Kbuild is not very cooperative with respect to linking separately
+ * compiled library objects into one module. So for now we won't use
+ * separate compilation ... ensuring init/exit sections work to shrink
+ * the runtime footprint, and giving us at least some parts of what
+ * a "gcc --combine ... part1.c part2.c part3.c ... " build would.
+ */
+#include "composite.c"
+#include "usbstring.c"
+#include "config.c"
+#include "epautoconf.c"
+
+#include "u_audio.c"
+#include "f_audio.c"
+
+/*-------------------------------------------------------------------------*/
+
+/* DO NOT REUSE THESE IDs with a protocol-incompatible driver!! Ever!!
+ * Instead: allocate your own, using normal USB-IF procedures.
+ */
+
+/* Thanks to NetChip Technologies for donating this product ID. */
+#define AUDIO_VENDOR_NUM 0x0525 /* NetChip */
+#define AUDIO_PRODUCT_NUM 0xa4a1 /* Linux-USB Audio Gadget */
+
+/*-------------------------------------------------------------------------*/
+
+static struct usb_device_descriptor device_desc = {
+ .bLength = sizeof device_desc,
+ .bDescriptorType = USB_DT_DEVICE,
+
+ .bcdUSB = __constant_cpu_to_le16(0x200),
+
+ .bDeviceClass = USB_CLASS_PER_INTERFACE,
+ .bDeviceSubClass = 0,
+ .bDeviceProtocol = 0,
+ /* .bMaxPacketSize0 = f(hardware) */
+
+ /* Vendor and product id defaults change according to what configs
+ * we support. (As does bNumConfigurations.) These values can
+ * also be overridden by module parameters.
+ */
+ .idVendor = __constant_cpu_to_le16(AUDIO_VENDOR_NUM),
+ .idProduct = __constant_cpu_to_le16(AUDIO_PRODUCT_NUM),
+ /* .bcdDevice = f(hardware) */
+ /* .iManufacturer = DYNAMIC */
+ /* .iProduct = DYNAMIC */
+ /* NO SERIAL NUMBER */
+ .bNumConfigurations = 1,
+};
+
+static struct usb_otg_descriptor otg_descriptor = {
+ .bLength = sizeof otg_descriptor,
+ .bDescriptorType = USB_DT_OTG,
+
+ /* REVISIT SRP-only hardware is possible, although
+ * it would not be called "OTG" ...
+ */
+ .bmAttributes = USB_OTG_SRP | USB_OTG_HNP,
+};
+
+static const struct usb_descriptor_header *otg_desc[] = {
+ (struct usb_descriptor_header *) &otg_descriptor,
+ NULL,
+};
+
+/*-------------------------------------------------------------------------*/
+
+/**
+ * Handle USB audio endpoint set/get command in setup class request
+ */
+
+static int audio_set_endpoint_req(struct usb_configuration *c,
+ const struct usb_ctrlrequest *ctrl)
+{
+ struct usb_composite_dev *cdev = c->cdev;
+ int value = -EOPNOTSUPP;
+ u16 ep = le16_to_cpu(ctrl->wIndex);
+ u16 len = le16_to_cpu(ctrl->wLength);
+ u16 w_value = le16_to_cpu(ctrl->wValue);
+
+ DBG(cdev, "bRequest 0x%x, w_value 0x%04x, len %d, endpoint %d\n",
+ ctrl->bRequest, w_value, len, ep);
+
+ switch (ctrl->bRequest) {
+ case SET_CUR:
+ value = 0;
+ break;
+
+ case SET_MIN:
+ break;
+
+ case SET_MAX:
+ break;
+
+ case SET_RES:
+ break;
+
+ case SET_MEM:
+ break;
+
+ default:
+ break;
+ }
+
+ return value;
+}
+
+static int audio_get_endpoint_req(struct usb_configuration *c,
+ const struct usb_ctrlrequest *ctrl)
+{
+ struct usb_composite_dev *cdev = c->cdev;
+ int value = -EOPNOTSUPP;
+ u8 ep = ((le16_to_cpu(ctrl->wIndex) >> 8) & 0xFF);
+ u16 len = le16_to_cpu(ctrl->wLength);
+ u16 w_value = le16_to_cpu(ctrl->wValue);
+
+ DBG(cdev, "bRequest 0x%x, w_value 0x%04x, len %d, endpoint %d\n",
+ ctrl->bRequest, w_value, len, ep);
+
+ switch (ctrl->bRequest) {
+ case GET_CUR:
+ case GET_MIN:
+ case GET_MAX:
+ case GET_RES:
+ value = 3;
+ break;
+ case GET_MEM:
+ break;
+ default:
+ break;
+ }
+
+ return value;
+}
+
+static int
+audio_setup(struct usb_configuration *c, const struct usb_ctrlrequest *ctrl)
+{
+ struct usb_composite_dev *cdev = c->cdev;
+ struct usb_request *req = cdev->req;
+ int value = -EOPNOTSUPP;
+ u16 w_index = le16_to_cpu(ctrl->wIndex);
+ u16 w_value = le16_to_cpu(ctrl->wValue);
+ u16 w_length = le16_to_cpu(ctrl->wLength);
+
+ /* composite driver infrastructure handles everything except
+ * Audio class messages; interface activation uses set_alt().
+ */
+ switch (ctrl->bRequestType) {
+ case USB_AUDIO_SET_ENDPOINT:
+ value = audio_set_endpoint_req(c, ctrl);
+ break;
+
+ case USB_AUDIO_GET_ENDPOINT:
+ value = audio_get_endpoint_req(c, ctrl);
+ break;
+
+ default:
+ ERROR(cdev, "Invalid control req%02x.%02x v%04x i%04x l%d\n",
+ ctrl->bRequestType, ctrl->bRequest,
+ w_value, w_index, w_length);
+ }
+
+ /* respond with data transfer or status phase? */
+ if (value >= 0) {
+ DBG(cdev, "Audio req%02x.%02x v%04x i%04x l%d\n",
+ ctrl->bRequestType, ctrl->bRequest,
+ w_value, w_index, w_length);
+ req->zero = 0;
+ req->length = value;
+ value = usb_ep_queue(cdev->gadget->ep0, req, GFP_ATOMIC);
+ if (value < 0)
+ ERROR(cdev, "Audio response on err %d\n", value);
+ }
+
+ /* device either stalls (value < 0) or reports success */
+ return value;
+}
+
+/*-------------------------------------------------------------------------*/
+
+static int __init audio_do_config(struct usb_configuration *c)
+{
+ /* FIXME alloc iConfiguration string, set it in c->strings */
+
+ if (gadget_is_otg(c->cdev->gadget)) {
+ c->descriptors = otg_desc;
+ c->bmAttributes |= USB_CONFIG_ATT_WAKEUP;
+ }
+
+ audio_bind_config(c);
+
+ return 0;
+}
+
+static struct usb_configuration audio_config_driver = {
+ .label = DRIVER_DESC,
+ .bind = audio_do_config,
+ .setup = audio_setup,
+ .bConfigurationValue = 1,
+ /* .iConfiguration = DYNAMIC */
+ .bmAttributes = USB_CONFIG_ATT_SELFPOWER,
+};
+
+/*-------------------------------------------------------------------------*/
+
+static int __init audio_bind(struct usb_composite_dev *cdev)
+{
+ int gcnum;
+ int status;
+
+ gcnum = usb_gadget_controller_number(cdev->gadget);
+ if (gcnum >= 0)
+ device_desc.bcdDevice = cpu_to_le16(0x0300 | gcnum);
+ else {
+ ERROR(cdev, "controller '%s' not recognized; trying %s\n",
+ cdev->gadget->name,
+ audio_config_driver.label);
+ device_desc.bcdDevice =
+ __constant_cpu_to_le16(0x0300 | 0x0099);
+ }
+
+ /* device descriptor strings: manufacturer, product */
+ snprintf(manufacturer, sizeof manufacturer, "%s %s with %s",
+ init_utsname()->sysname, init_utsname()->release,
+ cdev->gadget->name);
+ status = usb_string_id(cdev);
+ if (status < 0)
+ goto fail;
+ strings_dev[STRING_MANUFACTURER_IDX].id = status;
+ device_desc.iManufacturer = status;
+
+ status = usb_string_id(cdev);
+ if (status < 0)
+ goto fail;
+ strings_dev[STRING_PRODUCT_IDX].id = status;
+ device_desc.iProduct = status;
+
+ status = usb_add_config(cdev, &audio_config_driver);
+ if (status < 0)
+ goto fail;
+
+ INFO(cdev, "%s, version: %s\n", DRIVER_DESC, DRIVER_VERSION);
+ return 0;
+
+fail:
+ return status;
+}
+
+static int __exit audio_unbind(struct usb_composite_dev *cdev)
+{
+ return 0;
+}
+
+static struct usb_composite_driver audio_driver = {
+ .name = "g_audio",
+ .dev = &device_desc,
+ .strings = audio_strings,
+ .bind = audio_bind,
+ .unbind = __exit_p(audio_unbind),
+};
+
+static int __init init(void)
+{
+ return usb_composite_register(&audio_driver);
+}
+module_init(init);
+
+static void __exit cleanup(void)
+{
+ usb_composite_unregister(&audio_driver);
+}
+module_exit(cleanup);
+
+MODULE_DESCRIPTION(DRIVER_DESC);
+MODULE_AUTHOR("Bryan Wu <cooloney@kernel.org>");
+MODULE_LICENSE("GPL");
+
diff --git a/drivers/usb/gadget/ci13xxx_udc.c b/drivers/usb/gadget/ci13xxx_udc.c
index 38e531ecae4..c7cb87a6fee 100644
--- a/drivers/usb/gadget/ci13xxx_udc.c
+++ b/drivers/usb/gadget/ci13xxx_udc.c
@@ -1977,9 +1977,9 @@ static int ep_enable(struct usb_ep *ep,
if (!list_empty(&mEp->qh[mEp->dir].queue))
warn("enabling a non-empty endpoint!");
- mEp->dir = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? TX : RX;
- mEp->num = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
- mEp->type = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
+ mEp->dir = usb_endpoint_dir_in(desc) ? TX : RX;
+ mEp->num = usb_endpoint_num(desc);
+ mEp->type = usb_endpoint_type(desc);
mEp->ep.maxpacket = __constant_le16_to_cpu(desc->wMaxPacketSize);
diff --git a/drivers/usb/gadget/f_audio.c b/drivers/usb/gadget/f_audio.c
new file mode 100644
index 00000000000..66527ba2d2e
--- /dev/null
+++ b/drivers/usb/gadget/f_audio.c
@@ -0,0 +1,707 @@
+/*
+ * f_audio.c -- USB Audio class function driver
+ *
+ * Copyright (C) 2008 Bryan Wu <cooloney@kernel.org>
+ * Copyright (C) 2008 Analog Devices, Inc
+ *
+ * Enter bugs at http://blackfin.uclinux.org/
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <asm/atomic.h>
+
+#include "u_audio.h"
+
+#define OUT_EP_MAX_PACKET_SIZE 200
+static int req_buf_size = OUT_EP_MAX_PACKET_SIZE;
+module_param(req_buf_size, int, S_IRUGO);
+MODULE_PARM_DESC(req_buf_size, "ISO OUT endpoint request buffer size");
+
+static int req_count = 256;
+module_param(req_count, int, S_IRUGO);
+MODULE_PARM_DESC(req_count, "ISO OUT endpoint request count");
+
+static int audio_buf_size = 48000;
+module_param(audio_buf_size, int, S_IRUGO);
+MODULE_PARM_DESC(audio_buf_size, "Audio buffer size");
+
+/*
+ * DESCRIPTORS ... most are static, but strings and full
+ * configuration descriptors are built on demand.
+ */
+
+/*
+ * We have two interfaces- AudioControl and AudioStreaming
+ * TODO: only supcard playback currently
+ */
+#define F_AUDIO_AC_INTERFACE 0
+#define F_AUDIO_AS_INTERFACE 1
+#define F_AUDIO_NUM_INTERFACES 2
+
+/* B.3.1 Standard AC Interface Descriptor */
+static struct usb_interface_descriptor ac_interface_desc __initdata = {
+ .bLength = USB_DT_INTERFACE_SIZE,
+ .bDescriptorType = USB_DT_INTERFACE,
+ .bNumEndpoints = 0,
+ .bInterfaceClass = USB_CLASS_AUDIO,
+ .bInterfaceSubClass = USB_SUBCLASS_AUDIOCONTROL,
+};
+
+DECLARE_USB_AC_HEADER_DESCRIPTOR(2);
+
+#define USB_DT_AC_HEADER_LENGH USB_DT_AC_HEADER_SIZE(F_AUDIO_NUM_INTERFACES)
+/* B.3.2 Class-Specific AC Interface Descriptor */
+static struct usb_ac_header_descriptor_2 ac_header_desc = {
+ .bLength = USB_DT_AC_HEADER_LENGH,
+ .bDescriptorType = USB_DT_CS_INTERFACE,
+ .bDescriptorSubtype = HEADER,
+ .bcdADC = __constant_cpu_to_le16(0x0100),
+ .wTotalLength = __constant_cpu_to_le16(USB_DT_AC_HEADER_LENGH),
+ .bInCollection = F_AUDIO_NUM_INTERFACES,
+ .baInterfaceNr = {
+ [0] = F_AUDIO_AC_INTERFACE,
+ [1] = F_AUDIO_AS_INTERFACE,
+ }
+};
+
+#define INPUT_TERMINAL_ID 1
+static struct usb_input_terminal_descriptor input_terminal_desc = {
+ .bLength = USB_DT_AC_INPUT_TERMINAL_SIZE,
+ .bDescriptorType = USB_DT_CS_INTERFACE,
+ .bDescriptorSubtype = INPUT_TERMINAL,
+ .bTerminalID = INPUT_TERMINAL_ID,
+ .wTerminalType = USB_AC_TERMINAL_STREAMING,
+ .bAssocTerminal = 0,
+ .wChannelConfig = 0x3,
+};
+
+DECLARE_USB_AC_FEATURE_UNIT_DESCRIPTOR(0);
+
+#define FEATURE_UNIT_ID 2
+static struct usb_ac_feature_unit_descriptor_0 feature_unit_desc = {
+ .bLength = USB_DT_AC_FEATURE_UNIT_SIZE(0),
+ .bDescriptorType = USB_DT_CS_INTERFACE,
+ .bDescriptorSubtype = FEATURE_UNIT,
+ .bUnitID = FEATURE_UNIT_ID,
+ .bSourceID = INPUT_TERMINAL_ID,
+ .bControlSize = 2,
+ .bmaControls[0] = (FU_MUTE | FU_VOLUME),
+};
+
+static struct usb_audio_control mute_control = {
+ .list = LIST_HEAD_INIT(mute_control.list),
+ .name = "Mute Control",
+ .type = MUTE_CONTROL,
+ /* Todo: add real Mute control code */
+ .set = generic_set_cmd,
+ .get = generic_get_cmd,
+};
+
+static struct usb_audio_control volume_control = {
+ .list = LIST_HEAD_INIT(volume_control.list),
+ .name = "Volume Control",
+ .type = VOLUME_CONTROL,
+ /* Todo: add real Volume control code */
+ .set = generic_set_cmd,
+ .get = generic_get_cmd,
+};
+
+static struct usb_audio_control_selector feature_unit = {
+ .list = LIST_HEAD_INIT(feature_unit.list),
+ .id = FEATURE_UNIT_ID,
+ .name = "Mute & Volume Control",
+ .type = FEATURE_UNIT,
+ .desc = (struct usb_descriptor_header *)&feature_unit_desc,
+};
+
+#define OUTPUT_TERMINAL_ID 3
+static struct usb_output_terminal_descriptor output_terminal_desc = {
+ .bLength = USB_DT_AC_OUTPUT_TERMINAL_SIZE,
+ .bDescriptorType = USB_DT_CS_INTERFACE,
+ .bDescriptorSubtype = OUTPUT_TERMINAL,
+ .bTerminalID = OUTPUT_TERMINAL_ID,
+ .wTerminalType = USB_AC_OUTPUT_TERMINAL_SPEAKER,
+ .bAssocTerminal = FEATURE_UNIT_ID,
+ .bSourceID = FEATURE_UNIT_ID,
+};
+
+/* B.4.1 Standard AS Interface Descriptor */
+static struct usb_interface_descriptor as_interface_alt_0_desc = {
+ .bLength = USB_DT_INTERFACE_SIZE,
+ .bDescriptorType = USB_DT_INTERFACE,
+ .bAlternateSetting = 0,
+ .bNumEndpoints = 0,
+ .bInterfaceClass = USB_CLASS_AUDIO,
+ .bInterfaceSubClass = USB_SUBCLASS_AUDIOSTREAMING,
+};
+
+static struct usb_interface_descriptor as_interface_alt_1_desc = {
+ .bLength = USB_DT_INTERFACE_SIZE,
+ .bDescriptorType = USB_DT_INTERFACE,
+ .bAlternateSetting = 1,
+ .bNumEndpoints = 1,
+ .bInterfaceClass = USB_CLASS_AUDIO,
+ .bInterfaceSubClass = USB_SUBCLASS_AUDIOSTREAMING,
+};
+
+/* B.4.2 Class-Specific AS Interface Descriptor */
+static struct usb_as_header_descriptor as_header_desc = {
+ .bLength = USB_DT_AS_HEADER_SIZE,
+ .bDescriptorType = USB_DT_CS_INTERFACE,
+ .bDescriptorSubtype = AS_GENERAL,
+ .bTerminalLink = INPUT_TERMINAL_ID,
+ .bDelay = 1,
+ .wFormatTag = USB_AS_AUDIO_FORMAT_TYPE_I_PCM,
+};
+
+DECLARE_USB_AS_FORMAT_TYPE_I_DISCRETE_DESC(1);
+
+static struct usb_as_formate_type_i_discrete_descriptor_1 as_type_i_desc = {
+ .bLength = USB_AS_FORMAT_TYPE_I_DISCRETE_DESC_SIZE(1),
+ .bDescriptorType = USB_DT_CS_INTERFACE,
+ .bDescriptorSubtype = FORMAT_TYPE,
+ .bFormatType = USB_AS_FORMAT_TYPE_I,
+ .bSubframeSize = 2,
+ .bBitResolution = 16,
+ .bSamFreqType = 1,
+};
+
+/* Standard ISO OUT Endpoint Descriptor */
+static struct usb_endpoint_descriptor as_out_ep_desc __initdata = {
+ .bLength = USB_DT_ENDPOINT_AUDIO_SIZE,
+ .bDescriptorType = USB_DT_ENDPOINT,
+ .bEndpointAddress = USB_DIR_OUT,
+ .bmAttributes = USB_AS_ENDPOINT_ADAPTIVE
+ | USB_ENDPOINT_XFER_ISOC,
+ .wMaxPacketSize = __constant_cpu_to_le16(OUT_EP_MAX_PACKET_SIZE),
+ .bInterval = 4,
+};
+
+/* Class-specific AS ISO OUT Endpoint Descriptor */
+static struct usb_as_iso_endpoint_descriptor as_iso_out_desc __initdata = {
+ .bLength = USB_AS_ISO_ENDPOINT_DESC_SIZE,
+ .bDescriptorType = USB_DT_CS_ENDPOINT,
+ .bDescriptorSubtype = EP_GENERAL,
+ .bmAttributes = 1,
+ .bLockDelayUnits = 1,
+ .wLockDelay = __constant_cpu_to_le16(1),
+};
+
+static struct usb_descriptor_header *f_audio_desc[] __initdata = {
+ (struct usb_descriptor_header *)&ac_interface_desc,
+ (struct usb_descriptor_header *)&ac_header_desc,
+
+ (struct usb_descriptor_header *)&input_terminal_desc,
+ (struct usb_descriptor_header *)&output_terminal_desc,
+ (struct usb_descriptor_header *)&feature_unit_desc,
+
+ (struct usb_descriptor_header *)&as_interface_alt_0_desc,
+ (struct usb_descriptor_header *)&as_interface_alt_1_desc,
+ (struct usb_descriptor_header *)&as_header_desc,
+
+ (struct usb_descriptor_header *)&as_type_i_desc,
+
+ (struct usb_descriptor_header *)&as_out_ep_desc,
+ (struct usb_descriptor_header *)&as_iso_out_desc,
+ NULL,
+};
+
+/* string IDs are assigned dynamically */
+
+#define STRING_MANUFACTURER_IDX 0
+#define STRING_PRODUCT_IDX 1
+
+static char manufacturer[50];
+
+static struct usb_string strings_dev[] = {
+ [STRING_MANUFACTURER_IDX].s = manufacturer,
+ [STRING_PRODUCT_IDX].s = DRIVER_DESC,
+ { } /* end of list */
+};
+
+static struct usb_gadget_strings stringtab_dev = {
+ .language = 0x0409, /* en-us */
+ .strings = strings_dev,
+};
+
+static struct usb_gadget_strings *audio_strings[] = {
+ &stringtab_dev,
+ NULL,
+};
+
+/*
+ * This function is an ALSA sound card following USB Audio Class Spec 1.0.
+ */
+
+/*-------------------------------------------------------------------------*/
+struct f_audio_buf {
+ u8 *buf;
+ int actual;
+ struct list_head list;
+};
+
+static struct f_audio_buf *f_audio_buffer_alloc(int buf_size)
+{
+ struct f_audio_buf *copy_buf;
+
+ copy_buf = kzalloc(sizeof *copy_buf, GFP_ATOMIC);
+ if (!copy_buf)
+ return (struct f_audio_buf *)-ENOMEM;
+
+ copy_buf->buf = kzalloc(buf_size, GFP_ATOMIC);
+ if (!copy_buf->buf) {
+ kfree(copy_buf);
+ return (struct f_audio_buf *)-ENOMEM;
+ }
+
+ return copy_buf;
+}
+
+static void f_audio_buffer_free(struct f_audio_buf *audio_buf)
+{
+ kfree(audio_buf->buf);
+ kfree(audio_buf);
+}
+/*-------------------------------------------------------------------------*/
+
+struct f_audio {
+ struct gaudio card;
+
+ /* endpoints handle full and/or high speeds */
+ struct usb_ep *out_ep;
+ struct usb_endpoint_descriptor *out_desc;
+
+ spinlock_t lock;
+ struct f_audio_buf *copy_buf;
+ struct work_struct playback_work;
+ struct list_head play_queue;
+
+ /* Control Set command */
+ struct list_head cs;
+ u8 set_cmd;
+ struct usb_audio_control *set_con;
+};
+
+static inline struct f_audio *func_to_audio(struct usb_function *f)
+{
+ return container_of(f, struct f_audio, card.func);
+}
+
+/*-------------------------------------------------------------------------*/
+
+static void f_audio_playback_work(struct work_struct *data)
+{
+ struct f_audio *audio = container_of(data, struct f_audio,
+ playback_work);
+ struct f_audio_buf *play_buf;
+
+ spin_lock_irq(&audio->lock);
+ if (list_empty(&audio->play_queue)) {
+ spin_unlock_irq(&audio->lock);
+ return;
+ }
+ play_buf = list_first_entry(&audio->play_queue,
+ struct f_audio_buf, list);
+ list_del(&play_buf->list);
+ spin_unlock_irq(&audio->lock);
+
+ u_audio_playback(&audio->card, play_buf->buf, play_buf->actual);
+ f_audio_buffer_free(play_buf);
+
+ return;
+}
+
+static int f_audio_out_ep_complete(struct usb_ep *ep, struct usb_request *req)
+{
+ struct f_audio *audio = req->context;
+ struct usb_composite_dev *cdev = audio->card.func.config->cdev;
+ struct f_audio_buf *copy_buf = audio->copy_buf;
+ int err;
+
+ if (!copy_buf)
+ return -EINVAL;
+
+ /* Copy buffer is full, add it to the play_queue */
+ if (audio_buf_size - copy_buf->actual < req->actual) {
+ list_add_tail(&copy_buf->list, &audio->play_queue);
+ schedule_work(&audio->playback_work);
+ copy_buf = f_audio_buffer_alloc(audio_buf_size);
+ if (copy_buf < 0)
+ return -ENOMEM;
+ }
+
+ memcpy(copy_buf->buf + copy_buf->actual, req->buf, req->actual);
+ copy_buf->actual += req->actual;
+ audio->copy_buf = copy_buf;
+
+ err = usb_ep_queue(ep, req, GFP_ATOMIC);
+ if (err)
+ ERROR(cdev, "%s queue req: %d\n", ep->name, err);
+
+ return 0;
+
+}
+
+static void f_audio_complete(struct usb_ep *ep, struct usb_request *req)
+{
+ struct f_audio *audio = req->context;
+ int status = req->status;
+ u32 data = 0;
+ struct usb_ep *out_ep = audio->out_ep;
+
+ switch (status) {
+
+ case 0: /* normal completion? */
+ if (ep == out_ep)
+ f_audio_out_ep_complete(ep, req);
+ else if (audio->set_con) {
+ memcpy(&data, req->buf, req->length);
+ audio->set_con->set(audio->set_con, audio->set_cmd,
+ le16_to_cpu(data));
+ audio->set_con = NULL;
+ }
+ break;
+ default:
+ break;
+ }
+}
+
+static int audio_set_intf_req(struct usb_function *f,
+ const struct usb_ctrlrequest *ctrl)
+{
+ struct f_audio *audio = func_to_audio(f);
+ struct usb_composite_dev *cdev = f->config->cdev;
+ struct usb_request *req = cdev->req;
+ u8 id = ((le16_to_cpu(ctrl->wIndex) >> 8) & 0xFF);
+ u16 len = le16_to_cpu(ctrl->wLength);
+ u16 w_value = le16_to_cpu(ctrl->wValue);
+ u8 con_sel = (w_value >> 8) & 0xFF;
+ u8 cmd = (ctrl->bRequest & 0x0F);
+ struct usb_audio_control_selector *cs;
+ struct usb_audio_control *con;
+
+ DBG(cdev, "bRequest 0x%x, w_value 0x%04x, len %d, entity %d\n",
+ ctrl->bRequest, w_value, len, id);
+
+ list_for_each_entry(cs, &audio->cs, list) {
+ if (cs->id == id) {
+ list_for_each_entry(con, &cs->control, list) {
+ if (con->type == con_sel) {
+ audio->set_con = con;
+ break;
+ }
+ }
+ break;
+ }
+ }
+
+ audio->set_cmd = cmd;
+ req->context = audio;
+ req->complete = f_audio_complete;
+
+ return len;
+}
+
+static int audio_get_intf_req(struct usb_function *f,
+ const struct usb_ctrlrequest *ctrl)
+{
+ struct f_audio *audio = func_to_audio(f);
+ struct usb_composite_dev *cdev = f->config->cdev;
+ struct usb_request *req = cdev->req;
+ int value = -EOPNOTSUPP;
+ u8 id = ((le16_to_cpu(ctrl->wIndex) >> 8) & 0xFF);
+ u16 len = le16_to_cpu(ctrl->wLength);
+ u16 w_value = le16_to_cpu(ctrl->wValue);
+ u8 con_sel = (w_value >> 8) & 0xFF;
+ u8 cmd = (ctrl->bRequest & 0x0F);
+ struct usb_audio_control_selector *cs;
+ struct usb_audio_control *con;
+
+ DBG(cdev, "bRequest 0x%x, w_value 0x%04x, len %d, entity %d\n",
+ ctrl->bRequest, w_value, len, id);
+
+ list_for_each_entry(cs, &audio->cs, list) {
+ if (cs->id == id) {
+ list_for_each_entry(con, &cs->control, list) {
+ if (con->type == con_sel && con->get) {
+ value = con->get(con, cmd);
+ break;
+ }
+ }
+ break;
+ }
+ }
+
+ req->context = audio;
+ req->complete = f_audio_complete;
+ memcpy(req->buf, &value, len);
+
+ return len;
+}
+
+static int
+f_audio_setup(struct usb_function *f, const struct usb_ctrlrequest *ctrl)
+{
+ struct usb_composite_dev *cdev = f->config->cdev;
+ struct usb_request *req = cdev->req;
+ int value = -EOPNOTSUPP;
+ u16 w_index = le16_to_cpu(ctrl->wIndex);
+ u16 w_value = le16_to_cpu(ctrl->wValue);
+ u16 w_length = le16_to_cpu(ctrl->wLength);
+
+ /* composite driver infrastructure handles everything except
+ * Audio class messages; interface activation uses set_alt().
+ */
+ switch (ctrl->bRequestType) {
+ case USB_AUDIO_SET_INTF:
+ value = audio_set_intf_req(f, ctrl);
+ break;
+
+ case USB_AUDIO_GET_INTF:
+ value = audio_get_intf_req(f, ctrl);
+ break;
+
+ default:
+ ERROR(cdev, "invalid control req%02x.%02x v%04x i%04x l%d\n",
+ ctrl->bRequestType, ctrl->bRequest,
+ w_value, w_index, w_length);
+ }
+
+ /* respond with data transfer or status phase? */
+ if (value >= 0) {
+ DBG(cdev, "audio req%02x.%02x v%04x i%04x l%d\n",
+ ctrl->bRequestType, ctrl->bRequest,
+ w_value, w_index, w_length);
+ req->zero = 0;
+ req->length = value;
+ value = usb_ep_queue(cdev->gadget->ep0, req, GFP_ATOMIC);
+ if (value < 0)
+ ERROR(cdev, "audio response on err %d\n", value);
+ }
+
+ /* device either stalls (value < 0) or reports success */
+ return value;
+}
+
+static int f_audio_set_alt(struct usb_function *f, unsigned intf, unsigned alt)
+{
+ struct f_audio *audio = func_to_audio(f);
+ struct usb_composite_dev *cdev = f->config->cdev;
+ struct usb_ep *out_ep = audio->out_ep;
+ struct usb_request *req;
+ int i = 0, err = 0;
+
+ DBG(cdev, "intf %d, alt %d\n", intf, alt);
+
+ if (intf == 1) {
+ if (alt == 1) {
+ usb_ep_enable(out_ep, audio->out_desc);
+ out_ep->driver_data = audio;
+ audio->copy_buf = f_audio_buffer_alloc(audio_buf_size);
+
+ /*
+ * allocate a bunch of read buffers
+ * and queue them all at once.
+ */
+ for (i = 0; i < req_count && err == 0; i++) {
+ req = usb_ep_alloc_request(out_ep, GFP_ATOMIC);
+ if (req) {
+ req->buf = kzalloc(req_buf_size,
+ GFP_ATOMIC);
+ if (req->buf) {
+ req->length = req_buf_size;
+ req->context = audio;
+ req->complete =
+ f_audio_complete;
+ err = usb_ep_queue(out_ep,
+ req, GFP_ATOMIC);
+ if (err)
+ ERROR(cdev,
+ "%s queue req: %d\n",
+ out_ep->name, err);
+ } else
+ err = -ENOMEM;
+ } else
+ err = -ENOMEM;
+ }
+
+ } else {
+ struct f_audio_buf *copy_buf = audio->copy_buf;
+ if (copy_buf) {
+ list_add_tail(&copy_buf->list,
+ &audio->play_queue);
+ schedule_work(&audio->playback_work);
+ }
+ }
+ }
+
+ return err;
+}
+
+static void f_audio_disable(struct usb_function *f)
+{
+ return;
+}
+
+/*-------------------------------------------------------------------------*/
+
+static void f_audio_build_desc(struct f_audio *audio)
+{
+ struct gaudio *card = &audio->card;
+ u8 *sam_freq;
+ int rate;
+
+ /* Set channel numbers */
+ input_terminal_desc.bNrChannels = u_audio_get_playback_channels(card);
+ as_type_i_desc.bNrChannels = u_audio_get_playback_channels(card);
+
+ /* Set sample rates */
+ rate = u_audio_get_playback_rate(card);
+ sam_freq = as_type_i_desc.tSamFreq[0];
+ memcpy(sam_freq, &rate, 3);
+
+ /* Todo: Set Sample bits and other parameters */
+
+ return;
+}
+
+/* audio function driver setup/binding */
+static int __init
+f_audio_bind(struct usb_configuration *c, struct usb_function *f)
+{
+ struct usb_composite_dev *cdev = c->cdev;
+ struct f_audio *audio = func_to_audio(f);
+ int status;
+ struct usb_ep *ep;
+
+ f_audio_build_desc(audio);
+
+ /* allocate instance-specific interface IDs, and patch descriptors */
+ status = usb_interface_id(c, f);
+ if (status < 0)
+ goto fail;
+ ac_interface_desc.bInterfaceNumber = status;
+
+ status = usb_interface_id(c, f);
+ if (status < 0)
+ goto fail;
+ as_interface_alt_0_desc.bInterfaceNumber = status;
+ as_interface_alt_1_desc.bInterfaceNumber = status;
+
+ status = -ENODEV;
+
+ /* allocate instance-specific endpoints */
+ ep = usb_ep_autoconfig(cdev->gadget, &as_out_ep_desc);
+ if (!ep)
+ goto fail;
+ audio->out_ep = ep;
+ ep->driver_data = cdev; /* claim */
+
+ status = -ENOMEM;
+
+ /* supcard all relevant hardware speeds... we expect that when
+ * hardware is dual speed, all bulk-capable endpoints work at
+ * both speeds
+ */
+
+ /* copy descriptors, and track endpoint copies */
+ if (gadget_is_dualspeed(c->cdev->gadget)) {
+ c->highspeed = true;
+ f->hs_descriptors = usb_copy_descriptors(f_audio_desc);
+ } else
+ f->descriptors = usb_copy_descriptors(f_audio_desc);
+
+ return 0;
+
+fail:
+
+ return status;
+}
+
+static void
+f_audio_unbind(struct usb_configuration *c, struct usb_function *f)
+{
+ struct f_audio *audio = func_to_audio(f);
+
+ usb_free_descriptors(f->descriptors);
+ kfree(audio);
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* Todo: add more control selecotor dynamically */
+int __init control_selector_init(struct f_audio *audio)
+{
+ INIT_LIST_HEAD(&audio->cs);
+ list_add(&feature_unit.list, &audio->cs);
+
+ INIT_LIST_HEAD(&feature_unit.control);
+ list_add(&mute_control.list, &feature_unit.control);
+ list_add(&volume_control.list, &feature_unit.control);
+
+ volume_control.data[_CUR] = 0xffc0;
+ volume_control.data[_MIN] = 0xe3a0;
+ volume_control.data[_MAX] = 0xfff0;
+ volume_control.data[_RES] = 0x0030;
+
+ return 0;
+}
+
+/**
+ * audio_bind_config - add USB audio fucntion to a configuration
+ * @c: the configuration to supcard the USB audio function
+ * Context: single threaded during gadget setup
+ *
+ * Returns zero on success, else negative errno.
+ */
+int __init audio_bind_config(struct usb_configuration *c)
+{
+ struct f_audio *audio;
+ int status;
+
+ /* allocate and initialize one new instance */
+ audio = kzalloc(sizeof *audio, GFP_KERNEL);
+ if (!audio)
+ return -ENOMEM;
+
+ audio->card.func.name = "g_audio";
+ audio->card.gadget = c->cdev->gadget;
+
+ INIT_LIST_HEAD(&audio->play_queue);
+ spin_lock_init(&audio->lock);
+
+ /* set up ASLA audio devices */
+ status = gaudio_setup(&audio->card);
+ if (status < 0)
+ goto setup_fail;
+
+ audio->card.func.strings = audio_strings;
+ audio->card.func.bind = f_audio_bind;
+ audio->card.func.unbind = f_audio_unbind;
+ audio->card.func.set_alt = f_audio_set_alt;
+ audio->card.func.setup = f_audio_setup;
+ audio->card.func.disable = f_audio_disable;
+ audio->out_desc = &as_out_ep_desc;
+
+ control_selector_init(audio);
+
+ INIT_WORK(&audio->playback_work, f_audio_playback_work);
+
+ status = usb_add_function(c, &audio->card.func);
+ if (status)
+ goto add_fail;
+
+ INFO(c->cdev, "audio_buf_size %d, req_buf_size %d, req_count %d\n",
+ audio_buf_size, req_buf_size, req_count);
+
+ return status;
+
+add_fail:
+ gaudio_cleanup(&audio->card);
+setup_fail:
+ kfree(audio);
+ return status;
+}
diff --git a/drivers/usb/gadget/f_rndis.c b/drivers/usb/gadget/f_rndis.c
index 3279a472604..424a37c5773 100644
--- a/drivers/usb/gadget/f_rndis.c
+++ b/drivers/usb/gadget/f_rndis.c
@@ -475,7 +475,9 @@ static int rndis_set_alt(struct usb_function *f, unsigned intf, unsigned alt)
if (rndis->port.in_ep->driver_data) {
DBG(cdev, "reset rndis\n");
gether_disconnect(&rndis->port);
- } else {
+ }
+
+ if (!rndis->port.in) {
DBG(cdev, "init rndis\n");
rndis->port.in = ep_choose(cdev->gadget,
rndis->hs.in, rndis->fs.in);
diff --git a/drivers/usb/gadget/file_storage.c b/drivers/usb/gadget/file_storage.c
index 381a53b3e11..1e6aa504d58 100644
--- a/drivers/usb/gadget/file_storage.c
+++ b/drivers/usb/gadget/file_storage.c
@@ -248,6 +248,8 @@
#include <linux/freezer.h>
#include <linux/utsname.h>
+#include <asm/unaligned.h>
+
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
@@ -799,29 +801,9 @@ static int fsg_set_halt(struct fsg_dev *fsg, struct usb_ep *ep)
/* Routines for unaligned data access */
-static u16 get_be16(u8 *buf)
-{
- return ((u16) buf[0] << 8) | ((u16) buf[1]);
-}
-
-static u32 get_be32(u8 *buf)
-{
- return ((u32) buf[0] << 24) | ((u32) buf[1] << 16) |
- ((u32) buf[2] << 8) | ((u32) buf[3]);
-}
-
-static void put_be16(u8 *buf, u16 val)
-{
- buf[0] = val >> 8;
- buf[1] = val;
-}
-
-static void put_be32(u8 *buf, u32 val)
+static u32 get_unaligned_be24(u8 *buf)
{
- buf[0] = val >> 24;
- buf[1] = val >> 16;
- buf[2] = val >> 8;
- buf[3] = val & 0xff;
+ return 0xffffff & (u32) get_unaligned_be32(buf - 1);
}
@@ -1582,9 +1564,9 @@ static int do_read(struct fsg_dev *fsg)
/* Get the starting Logical Block Address and check that it's
* not too big */
if (fsg->cmnd[0] == SC_READ_6)
- lba = (fsg->cmnd[1] << 16) | get_be16(&fsg->cmnd[2]);
+ lba = get_unaligned_be24(&fsg->cmnd[1]);
else {
- lba = get_be32(&fsg->cmnd[2]);
+ lba = get_unaligned_be32(&fsg->cmnd[2]);
/* We allow DPO (Disable Page Out = don't save data in the
* cache) and FUA (Force Unit Access = don't read from the
@@ -1717,9 +1699,9 @@ static int do_write(struct fsg_dev *fsg)
/* Get the starting Logical Block Address and check that it's
* not too big */
if (fsg->cmnd[0] == SC_WRITE_6)
- lba = (fsg->cmnd[1] << 16) | get_be16(&fsg->cmnd[2]);
+ lba = get_unaligned_be24(&fsg->cmnd[1]);
else {
- lba = get_be32(&fsg->cmnd[2]);
+ lba = get_unaligned_be32(&fsg->cmnd[2]);
/* We allow DPO (Disable Page Out = don't save data in the
* cache) and FUA (Force Unit Access = write directly to the
@@ -1940,7 +1922,7 @@ static int do_verify(struct fsg_dev *fsg)
/* Get the starting Logical Block Address and check that it's
* not too big */
- lba = get_be32(&fsg->cmnd[2]);
+ lba = get_unaligned_be32(&fsg->cmnd[2]);
if (lba >= curlun->num_sectors) {
curlun->sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;
return -EINVAL;
@@ -1953,7 +1935,7 @@ static int do_verify(struct fsg_dev *fsg)
return -EINVAL;
}
- verification_length = get_be16(&fsg->cmnd[7]);
+ verification_length = get_unaligned_be16(&fsg->cmnd[7]);
if (unlikely(verification_length == 0))
return -EIO; // No default reply
@@ -2103,7 +2085,7 @@ static int do_request_sense(struct fsg_dev *fsg, struct fsg_buffhd *bh)
memset(buf, 0, 18);
buf[0] = valid | 0x70; // Valid, current error
buf[2] = SK(sd);
- put_be32(&buf[3], sdinfo); // Sense information
+ put_unaligned_be32(sdinfo, &buf[3]); /* Sense information */
buf[7] = 18 - 8; // Additional sense length
buf[12] = ASC(sd);
buf[13] = ASCQ(sd);
@@ -2114,7 +2096,7 @@ static int do_request_sense(struct fsg_dev *fsg, struct fsg_buffhd *bh)
static int do_read_capacity(struct fsg_dev *fsg, struct fsg_buffhd *bh)
{
struct lun *curlun = fsg->curlun;
- u32 lba = get_be32(&fsg->cmnd[2]);
+ u32 lba = get_unaligned_be32(&fsg->cmnd[2]);
int pmi = fsg->cmnd[8];
u8 *buf = (u8 *) bh->buf;
@@ -2124,8 +2106,9 @@ static int do_read_capacity(struct fsg_dev *fsg, struct fsg_buffhd *bh)
return -EINVAL;
}
- put_be32(&buf[0], curlun->num_sectors - 1); // Max logical block
- put_be32(&buf[4], 512); // Block length
+ put_unaligned_be32(curlun->num_sectors - 1, &buf[0]);
+ /* Max logical block */
+ put_unaligned_be32(512, &buf[4]); /* Block length */
return 8;
}
@@ -2144,7 +2127,7 @@ static void store_cdrom_address(u8 *dest, int msf, u32 addr)
dest[0] = 0; /* Reserved */
} else {
/* Absolute sector */
- put_be32(dest, addr);
+ put_unaligned_be32(addr, dest);
}
}
@@ -2152,7 +2135,7 @@ static int do_read_header(struct fsg_dev *fsg, struct fsg_buffhd *bh)
{
struct lun *curlun = fsg->curlun;
int msf = fsg->cmnd[1] & 0x02;
- u32 lba = get_be32(&fsg->cmnd[2]);
+ u32 lba = get_unaligned_be32(&fsg->cmnd[2]);
u8 *buf = (u8 *) bh->buf;
if ((fsg->cmnd[1] & ~0x02) != 0) { /* Mask away MSF */
@@ -2252,10 +2235,13 @@ static int do_mode_sense(struct fsg_dev *fsg, struct fsg_buffhd *bh)
buf[2] = 0x04; // Write cache enable,
// Read cache not disabled
// No cache retention priorities
- put_be16(&buf[4], 0xffff); // Don't disable prefetch
- // Minimum prefetch = 0
- put_be16(&buf[8], 0xffff); // Maximum prefetch
- put_be16(&buf[10], 0xffff); // Maximum prefetch ceiling
+ put_unaligned_be16(0xffff, &buf[4]);
+ /* Don't disable prefetch */
+ /* Minimum prefetch = 0 */
+ put_unaligned_be16(0xffff, &buf[8]);
+ /* Maximum prefetch */
+ put_unaligned_be16(0xffff, &buf[10]);
+ /* Maximum prefetch ceiling */
}
buf += 12;
}
@@ -2272,7 +2258,7 @@ static int do_mode_sense(struct fsg_dev *fsg, struct fsg_buffhd *bh)
if (mscmnd == SC_MODE_SENSE_6)
buf0[0] = len - 1;
else
- put_be16(buf0, len - 2);
+ put_unaligned_be16(len - 2, buf0);
return len;
}
@@ -2360,9 +2346,10 @@ static int do_read_format_capacities(struct fsg_dev *fsg,
buf[3] = 8; // Only the Current/Maximum Capacity Descriptor
buf += 4;
- put_be32(&buf[0], curlun->num_sectors); // Number of blocks
- put_be32(&buf[4], 512); // Block length
- buf[4] = 0x02; // Current capacity
+ put_unaligned_be32(curlun->num_sectors, &buf[0]);
+ /* Number of blocks */
+ put_unaligned_be32(512, &buf[4]); /* Block length */
+ buf[4] = 0x02; /* Current capacity */
return 12;
}
@@ -2882,7 +2869,7 @@ static int do_scsi_command(struct fsg_dev *fsg)
break;
case SC_MODE_SELECT_10:
- fsg->data_size_from_cmnd = get_be16(&fsg->cmnd[7]);
+ fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);
if ((reply = check_command(fsg, 10, DATA_DIR_FROM_HOST,
(1<<1) | (3<<7), 0,
"MODE SELECT(10)")) == 0)
@@ -2898,7 +2885,7 @@ static int do_scsi_command(struct fsg_dev *fsg)
break;
case SC_MODE_SENSE_10:
- fsg->data_size_from_cmnd = get_be16(&fsg->cmnd[7]);
+ fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);
if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST,
(1<<1) | (1<<2) | (3<<7), 0,
"MODE SENSE(10)")) == 0)
@@ -2923,7 +2910,8 @@ static int do_scsi_command(struct fsg_dev *fsg)
break;
case SC_READ_10:
- fsg->data_size_from_cmnd = get_be16(&fsg->cmnd[7]) << 9;
+ fsg->data_size_from_cmnd =
+ get_unaligned_be16(&fsg->cmnd[7]) << 9;
if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST,
(1<<1) | (0xf<<2) | (3<<7), 1,
"READ(10)")) == 0)
@@ -2931,7 +2919,8 @@ static int do_scsi_command(struct fsg_dev *fsg)
break;
case SC_READ_12:
- fsg->data_size_from_cmnd = get_be32(&fsg->cmnd[6]) << 9;
+ fsg->data_size_from_cmnd =
+ get_unaligned_be32(&fsg->cmnd[6]) << 9;
if ((reply = check_command(fsg, 12, DATA_DIR_TO_HOST,
(1<<1) | (0xf<<2) | (0xf<<6), 1,
"READ(12)")) == 0)
@@ -2949,7 +2938,7 @@ static int do_scsi_command(struct fsg_dev *fsg)
case SC_READ_HEADER:
if (!mod_data.cdrom)
goto unknown_cmnd;
- fsg->data_size_from_cmnd = get_be16(&fsg->cmnd[7]);
+ fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);
if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST,
(3<<7) | (0x1f<<1), 1,
"READ HEADER")) == 0)
@@ -2959,7 +2948,7 @@ static int do_scsi_command(struct fsg_dev *fsg)
case SC_READ_TOC:
if (!mod_data.cdrom)
goto unknown_cmnd;
- fsg->data_size_from_cmnd = get_be16(&fsg->cmnd[7]);
+ fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);
if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST,
(7<<6) | (1<<1), 1,
"READ TOC")) == 0)
@@ -2967,7 +2956,7 @@ static int do_scsi_command(struct fsg_dev *fsg)
break;
case SC_READ_FORMAT_CAPACITIES:
- fsg->data_size_from_cmnd = get_be16(&fsg->cmnd[7]);
+ fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);
if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST,
(3<<7), 1,
"READ FORMAT CAPACITIES")) == 0)
@@ -3025,7 +3014,8 @@ static int do_scsi_command(struct fsg_dev *fsg)
break;
case SC_WRITE_10:
- fsg->data_size_from_cmnd = get_be16(&fsg->cmnd[7]) << 9;
+ fsg->data_size_from_cmnd =
+ get_unaligned_be16(&fsg->cmnd[7]) << 9;
if ((reply = check_command(fsg, 10, DATA_DIR_FROM_HOST,
(1<<1) | (0xf<<2) | (3<<7), 1,
"WRITE(10)")) == 0)
@@ -3033,7 +3023,8 @@ static int do_scsi_command(struct fsg_dev *fsg)
break;
case SC_WRITE_12:
- fsg->data_size_from_cmnd = get_be32(&fsg->cmnd[6]) << 9;
+ fsg->data_size_from_cmnd =
+ get_unaligned_be32(&fsg->cmnd[6]) << 9;
if ((reply = check_command(fsg, 12, DATA_DIR_FROM_HOST,
(1<<1) | (0xf<<2) | (0xf<<6), 1,
"WRITE(12)")) == 0)
diff --git a/drivers/usb/gadget/fsl_mx3_udc.c b/drivers/usb/gadget/fsl_mx3_udc.c
new file mode 100644
index 00000000000..4bc2bf3d602
--- /dev/null
+++ b/drivers/usb/gadget/fsl_mx3_udc.c
@@ -0,0 +1,95 @@
+/*
+ * Copyright (C) 2009
+ * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
+ *
+ * Description:
+ * Helper routines for i.MX3x SoCs from Freescale, needed by the fsl_usb2_udc.c
+ * driver to function correctly on these systems.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/fsl_devices.h>
+#include <linux/platform_device.h>
+
+static struct clk *mxc_ahb_clk;
+static struct clk *mxc_usb_clk;
+
+int fsl_udc_clk_init(struct platform_device *pdev)
+{
+ struct fsl_usb2_platform_data *pdata;
+ unsigned long freq;
+ int ret;
+
+ pdata = pdev->dev.platform_data;
+
+ mxc_ahb_clk = clk_get(&pdev->dev, "usb_ahb");
+ if (IS_ERR(mxc_ahb_clk))
+ return PTR_ERR(mxc_ahb_clk);
+
+ ret = clk_enable(mxc_ahb_clk);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "clk_enable(\"usb_ahb\") failed\n");
+ goto eenahb;
+ }
+
+ /* make sure USB_CLK is running at 60 MHz +/- 1000 Hz */
+ mxc_usb_clk = clk_get(&pdev->dev, "usb");
+ if (IS_ERR(mxc_usb_clk)) {
+ dev_err(&pdev->dev, "clk_get(\"usb\") failed\n");
+ ret = PTR_ERR(mxc_usb_clk);
+ goto egusb;
+ }
+
+ freq = clk_get_rate(mxc_usb_clk);
+ if (pdata->phy_mode != FSL_USB2_PHY_ULPI &&
+ (freq < 59999000 || freq > 60001000)) {
+ dev_err(&pdev->dev, "USB_CLK=%lu, should be 60MHz\n", freq);
+ goto eclkrate;
+ }
+
+ ret = clk_enable(mxc_usb_clk);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "clk_enable(\"usb_clk\") failed\n");
+ goto eenusb;
+ }
+
+ return 0;
+
+eenusb:
+eclkrate:
+ clk_put(mxc_usb_clk);
+ mxc_usb_clk = NULL;
+egusb:
+ clk_disable(mxc_ahb_clk);
+eenahb:
+ clk_put(mxc_ahb_clk);
+ return ret;
+}
+
+void fsl_udc_clk_finalize(struct platform_device *pdev)
+{
+ struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
+
+ /* ULPI transceivers don't need usbpll */
+ if (pdata->phy_mode == FSL_USB2_PHY_ULPI) {
+ clk_disable(mxc_usb_clk);
+ clk_put(mxc_usb_clk);
+ mxc_usb_clk = NULL;
+ }
+}
+
+void fsl_udc_clk_release(void)
+{
+ if (mxc_usb_clk) {
+ clk_disable(mxc_usb_clk);
+ clk_put(mxc_usb_clk);
+ }
+ clk_disable(mxc_ahb_clk);
+ clk_put(mxc_ahb_clk);
+}
diff --git a/drivers/usb/gadget/fsl_usb2_udc.c b/drivers/usb/gadget/fsl_udc_core.c
index 9d7b95d4e3d..42a74b8a0bb 100644
--- a/drivers/usb/gadget/fsl_usb2_udc.c
+++ b/drivers/usb/gadget/fsl_udc_core.c
@@ -38,6 +38,7 @@
#include <linux/platform_device.h>
#include <linux/fsl_devices.h>
#include <linux/dmapool.h>
+#include <linux/delay.h>
#include <asm/byteorder.h>
#include <asm/io.h>
@@ -57,7 +58,9 @@ static const char driver_name[] = "fsl-usb2-udc";
static const char driver_desc[] = DRIVER_DESC;
static struct usb_dr_device *dr_regs;
+#ifndef CONFIG_ARCH_MXC
static struct usb_sys_interface *usb_sys_regs;
+#endif
/* it is initialized in probe() */
static struct fsl_udc *udc_controller = NULL;
@@ -174,10 +177,34 @@ static void nuke(struct fsl_ep *ep, int status)
static int dr_controller_setup(struct fsl_udc *udc)
{
- unsigned int tmp = 0, portctrl = 0, ctrl = 0;
+ unsigned int tmp, portctrl;
+#ifndef CONFIG_ARCH_MXC
+ unsigned int ctrl;
+#endif
unsigned long timeout;
#define FSL_UDC_RESET_TIMEOUT 1000
+ /* Config PHY interface */
+ portctrl = fsl_readl(&dr_regs->portsc1);
+ portctrl &= ~(PORTSCX_PHY_TYPE_SEL | PORTSCX_PORT_WIDTH);
+ switch (udc->phy_mode) {
+ case FSL_USB2_PHY_ULPI:
+ portctrl |= PORTSCX_PTS_ULPI;
+ break;
+ case FSL_USB2_PHY_UTMI_WIDE:
+ portctrl |= PORTSCX_PTW_16BIT;
+ /* fall through */
+ case FSL_USB2_PHY_UTMI:
+ portctrl |= PORTSCX_PTS_UTMI;
+ break;
+ case FSL_USB2_PHY_SERIAL:
+ portctrl |= PORTSCX_PTS_FSLS;
+ break;
+ default:
+ return -EINVAL;
+ }
+ fsl_writel(portctrl, &dr_regs->portsc1);
+
/* Stop and reset the usb controller */
tmp = fsl_readl(&dr_regs->usbcmd);
tmp &= ~USB_CMD_RUN_STOP;
@@ -215,31 +242,12 @@ static int dr_controller_setup(struct fsl_udc *udc)
udc->ep_qh, (int)tmp,
fsl_readl(&dr_regs->endpointlistaddr));
- /* Config PHY interface */
- portctrl = fsl_readl(&dr_regs->portsc1);
- portctrl &= ~(PORTSCX_PHY_TYPE_SEL | PORTSCX_PORT_WIDTH);
- switch (udc->phy_mode) {
- case FSL_USB2_PHY_ULPI:
- portctrl |= PORTSCX_PTS_ULPI;
- break;
- case FSL_USB2_PHY_UTMI_WIDE:
- portctrl |= PORTSCX_PTW_16BIT;
- /* fall through */
- case FSL_USB2_PHY_UTMI:
- portctrl |= PORTSCX_PTS_UTMI;
- break;
- case FSL_USB2_PHY_SERIAL:
- portctrl |= PORTSCX_PTS_FSLS;
- break;
- default:
- return -EINVAL;
- }
- fsl_writel(portctrl, &dr_regs->portsc1);
-
/* Config control enable i/o output, cpu endian register */
+#ifndef CONFIG_ARCH_MXC
ctrl = __raw_readl(&usb_sys_regs->control);
ctrl |= USB_CTRL_IOENB;
__raw_writel(ctrl, &usb_sys_regs->control);
+#endif
#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
/* Turn on cache snooping hardware, since some PowerPC platforms
@@ -2043,6 +2051,7 @@ static int fsl_proc_read(char *page, char **start, off_t off, int count,
size -= t;
next += t;
+#ifndef CONFIG_ARCH_MXC
tmp_reg = usb_sys_regs->snoop1;
t = scnprintf(next, size, "Snoop1 Reg : = [0x%x]\n\n", tmp_reg);
size -= t;
@@ -2053,6 +2062,7 @@ static int fsl_proc_read(char *page, char **start, off_t off, int count,
tmp_reg);
size -= t;
next += t;
+#endif
/* ------fsl_udc, fsl_ep, fsl_request structure information ----- */
ep = &udc->eps[0];
@@ -2263,14 +2273,21 @@ static int __init fsl_udc_probe(struct platform_device *pdev)
goto err_kfree;
}
- dr_regs = ioremap(res->start, res->end - res->start + 1);
+ dr_regs = ioremap(res->start, resource_size(res));
if (!dr_regs) {
ret = -ENOMEM;
goto err_release_mem_region;
}
+#ifndef CONFIG_ARCH_MXC
usb_sys_regs = (struct usb_sys_interface *)
((u32)dr_regs + USB_DR_SYS_OFFSET);
+#endif
+
+ /* Initialize USB clocks */
+ ret = fsl_udc_clk_init(pdev);
+ if (ret < 0)
+ goto err_iounmap_noclk;
/* Read Device Controller Capability Parameters register */
dccparams = fsl_readl(&dr_regs->dccparams);
@@ -2308,6 +2325,8 @@ static int __init fsl_udc_probe(struct platform_device *pdev)
* leave usbintr reg untouched */
dr_controller_setup(udc_controller);
+ fsl_udc_clk_finalize(pdev);
+
/* Setup gadget structure */
udc_controller->gadget.ops = &fsl_gadget_ops;
udc_controller->gadget.is_dualspeed = 1;
@@ -2362,6 +2381,8 @@ err_unregister:
err_free_irq:
free_irq(udc_controller->irq, udc_controller);
err_iounmap:
+ fsl_udc_clk_release();
+err_iounmap_noclk:
iounmap(dr_regs);
err_release_mem_region:
release_mem_region(res->start, res->end - res->start + 1);
@@ -2384,6 +2405,8 @@ static int __exit fsl_udc_remove(struct platform_device *pdev)
return -ENODEV;
udc_controller->done = &done;
+ fsl_udc_clk_release();
+
/* DR has been stopped in usb_gadget_unregister_driver() */
remove_proc_file();
diff --git a/drivers/usb/gadget/fsl_usb2_udc.h b/drivers/usb/gadget/fsl_usb2_udc.h
index e63ef12645f..20aeceed48c 100644
--- a/drivers/usb/gadget/fsl_usb2_udc.h
+++ b/drivers/usb/gadget/fsl_usb2_udc.h
@@ -563,4 +563,22 @@ static void dump_msg(const char *label, const u8 * buf, unsigned int length)
* 2 + ((windex & USB_DIR_IN) ? 1 : 0))
#define get_pipe_by_ep(EP) (ep_index(EP) * 2 + ep_is_in(EP))
+struct platform_device;
+#ifdef CONFIG_ARCH_MXC
+int fsl_udc_clk_init(struct platform_device *pdev);
+void fsl_udc_clk_finalize(struct platform_device *pdev);
+void fsl_udc_clk_release(void);
+#else
+static inline int fsl_udc_clk_init(struct platform_device *pdev)
+{
+ return 0;
+}
+static inline void fsl_udc_clk_finalize(struct platform_device *pdev)
+{
+}
+static inline void fsl_udc_clk_release(void)
+{
+}
+#endif
+
#endif
diff --git a/drivers/usb/gadget/gadget_chips.h b/drivers/usb/gadget/gadget_chips.h
index ec6d439a2aa..8e0e9a0b736 100644
--- a/drivers/usb/gadget/gadget_chips.h
+++ b/drivers/usb/gadget/gadget_chips.h
@@ -137,6 +137,12 @@
#define gadget_is_musbhdrc(g) 0
#endif
+#ifdef CONFIG_USB_GADGET_LANGWELL
+#define gadget_is_langwell(g) (!strcmp("langwell_udc", (g)->name))
+#else
+#define gadget_is_langwell(g) 0
+#endif
+
/* from Montavista kernel (?) */
#ifdef CONFIG_USB_GADGET_MPC8272
#define gadget_is_mpc8272(g) !strcmp("mpc8272_udc", (g)->name)
@@ -231,6 +237,8 @@ static inline int usb_gadget_controller_number(struct usb_gadget *gadget)
return 0x22;
else if (gadget_is_ci13xxx(gadget))
return 0x23;
+ else if (gadget_is_langwell(gadget))
+ return 0x24;
return -ENOENT;
}
diff --git a/drivers/usb/gadget/goku_udc.c b/drivers/usb/gadget/goku_udc.c
index de010c939db..112bb40a427 100644
--- a/drivers/usb/gadget/goku_udc.c
+++ b/drivers/usb/gadget/goku_udc.c
@@ -110,10 +110,10 @@ goku_ep_enable(struct usb_ep *_ep, const struct usb_endpoint_descriptor *desc)
return -EINVAL;
if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
return -ESHUTDOWN;
- if (ep->num != (desc->bEndpointAddress & 0x0f))
+ if (ep->num != usb_endpoint_num(desc))
return -EINVAL;
- switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
+ switch (usb_endpoint_type(desc)) {
case USB_ENDPOINT_XFER_BULK:
case USB_ENDPOINT_XFER_INT:
break;
@@ -142,7 +142,7 @@ goku_ep_enable(struct usb_ep *_ep, const struct usb_endpoint_descriptor *desc)
/* ep1/ep2 dma direction is chosen early; it works in the other
* direction, with pio. be cautious with out-dma.
*/
- ep->is_in = (USB_DIR_IN & desc->bEndpointAddress) != 0;
+ ep->is_in = usb_endpoint_dir_in(desc);
if (ep->is_in) {
mode |= 1;
ep->dma = (use_dma != 0) && (ep->num == UDC_MSTRD_ENDPOINT);
diff --git a/drivers/usb/gadget/imx_udc.c b/drivers/usb/gadget/imx_udc.c
index 168658b4b4e..c52a681f376 100644
--- a/drivers/usb/gadget/imx_udc.c
+++ b/drivers/usb/gadget/imx_udc.c
@@ -415,6 +415,13 @@ static int write_packet(struct imx_ep_struct *imx_ep, struct imx_request *req)
u8 *buf;
int length, count, temp;
+ if (unlikely(__raw_readl(imx_ep->imx_usb->base +
+ USB_EP_STAT(EP_NO(imx_ep))) & EPSTAT_ZLPS)) {
+ D_TRX(imx_ep->imx_usb->dev, "<%s> zlp still queued in EP %s\n",
+ __func__, imx_ep->ep.name);
+ return -1;
+ }
+
buf = req->req.buf + req->req.actual;
prefetch(buf);
@@ -734,9 +741,12 @@ static struct usb_request *imx_ep_alloc_request
{
struct imx_request *req;
+ if (!usb_ep)
+ return NULL;
+
req = kzalloc(sizeof *req, gfp_flags);
- if (!req || !usb_ep)
- return 0;
+ if (!req)
+ return NULL;
INIT_LIST_HEAD(&req->queue);
req->in_use = 0;
diff --git a/drivers/usb/gadget/inode.c b/drivers/usb/gadget/inode.c
index d20937f28a1..7d33f50b587 100644
--- a/drivers/usb/gadget/inode.c
+++ b/drivers/usb/gadget/inode.c
@@ -384,9 +384,8 @@ ep_read (struct file *fd, char __user *buf, size_t len, loff_t *ptr)
return value;
/* halt any endpoint by doing a "wrong direction" i/o call */
- if (data->desc.bEndpointAddress & USB_DIR_IN) {
- if ((data->desc.bmAttributes & USB_ENDPOINT_XFERTYPE_MASK)
- == USB_ENDPOINT_XFER_ISOC)
+ if (usb_endpoint_dir_in(&data->desc)) {
+ if (usb_endpoint_xfer_isoc(&data->desc))
return -EINVAL;
DBG (data->dev, "%s halt\n", data->name);
spin_lock_irq (&data->dev->lock);
@@ -428,9 +427,8 @@ ep_write (struct file *fd, const char __user *buf, size_t len, loff_t *ptr)
return value;
/* halt any endpoint by doing a "wrong direction" i/o call */
- if (!(data->desc.bEndpointAddress & USB_DIR_IN)) {
- if ((data->desc.bmAttributes & USB_ENDPOINT_XFERTYPE_MASK)
- == USB_ENDPOINT_XFER_ISOC)
+ if (!usb_endpoint_dir_in(&data->desc)) {
+ if (usb_endpoint_xfer_isoc(&data->desc))
return -EINVAL;
DBG (data->dev, "%s halt\n", data->name);
spin_lock_irq (&data->dev->lock);
@@ -691,7 +689,7 @@ ep_aio_read(struct kiocb *iocb, const struct iovec *iov,
struct ep_data *epdata = iocb->ki_filp->private_data;
char *buf;
- if (unlikely(epdata->desc.bEndpointAddress & USB_DIR_IN))
+ if (unlikely(usb_endpoint_dir_in(&epdata->desc)))
return -EINVAL;
buf = kmalloc(iocb->ki_left, GFP_KERNEL);
@@ -711,7 +709,7 @@ ep_aio_write(struct kiocb *iocb, const struct iovec *iov,
size_t len = 0;
int i = 0;
- if (unlikely(!(epdata->desc.bEndpointAddress & USB_DIR_IN)))
+ if (unlikely(!usb_endpoint_dir_in(&epdata->desc)))
return -EINVAL;
buf = kmalloc(iocb->ki_left, GFP_KERNEL);
diff --git a/drivers/usb/gadget/langwell_udc.c b/drivers/usb/gadget/langwell_udc.c
new file mode 100644
index 00000000000..6829d596135
--- /dev/null
+++ b/drivers/usb/gadget/langwell_udc.c
@@ -0,0 +1,3373 @@
+/*
+ * Intel Langwell USB Device Controller driver
+ * Copyright (C) 2008-2009, Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ */
+
+
+/* #undef DEBUG */
+/* #undef VERBOSE */
+
+#if defined(CONFIG_USB_LANGWELL_OTG)
+#define OTG_TRANSCEIVER
+#endif
+
+
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/dma-mapping.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/ioport.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/smp_lock.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/timer.h>
+#include <linux/list.h>
+#include <linux/interrupt.h>
+#include <linux/moduleparam.h>
+#include <linux/device.h>
+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+#include <linux/usb/otg.h>
+#include <linux/pm.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <asm/system.h>
+#include <asm/unaligned.h>
+
+#include "langwell_udc.h"
+
+
+#define DRIVER_DESC "Intel Langwell USB Device Controller driver"
+#define DRIVER_VERSION "16 May 2009"
+
+static const char driver_name[] = "langwell_udc";
+static const char driver_desc[] = DRIVER_DESC;
+
+
+/* controller device global variable */
+static struct langwell_udc *the_controller;
+
+/* for endpoint 0 operations */
+static const struct usb_endpoint_descriptor
+langwell_ep0_desc = {
+ .bLength = USB_DT_ENDPOINT_SIZE,
+ .bDescriptorType = USB_DT_ENDPOINT,
+ .bEndpointAddress = 0,
+ .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
+ .wMaxPacketSize = EP0_MAX_PKT_SIZE,
+};
+
+
+/*-------------------------------------------------------------------------*/
+/* debugging */
+
+#ifdef DEBUG
+#define DBG(dev, fmt, args...) \
+ pr_debug("%s %s: " fmt , driver_name, \
+ pci_name(dev->pdev), ## args)
+#else
+#define DBG(dev, fmt, args...) \
+ do { } while (0)
+#endif /* DEBUG */
+
+
+#ifdef VERBOSE
+#define VDBG DBG
+#else
+#define VDBG(dev, fmt, args...) \
+ do { } while (0)
+#endif /* VERBOSE */
+
+
+#define ERROR(dev, fmt, args...) \
+ pr_err("%s %s: " fmt , driver_name, \
+ pci_name(dev->pdev), ## args)
+
+#define WARNING(dev, fmt, args...) \
+ pr_warning("%s %s: " fmt , driver_name, \
+ pci_name(dev->pdev), ## args)
+
+#define INFO(dev, fmt, args...) \
+ pr_info("%s %s: " fmt , driver_name, \
+ pci_name(dev->pdev), ## args)
+
+
+#ifdef VERBOSE
+static inline void print_all_registers(struct langwell_udc *dev)
+{
+ int i;
+
+ /* Capability Registers */
+ printk(KERN_DEBUG "Capability Registers (offset: "
+ "0x%04x, length: 0x%08x)\n",
+ CAP_REG_OFFSET,
+ (u32)sizeof(struct langwell_cap_regs));
+ printk(KERN_DEBUG "caplength=0x%02x\n",
+ readb(&dev->cap_regs->caplength));
+ printk(KERN_DEBUG "hciversion=0x%04x\n",
+ readw(&dev->cap_regs->hciversion));
+ printk(KERN_DEBUG "hcsparams=0x%08x\n",
+ readl(&dev->cap_regs->hcsparams));
+ printk(KERN_DEBUG "hccparams=0x%08x\n",
+ readl(&dev->cap_regs->hccparams));
+ printk(KERN_DEBUG "dciversion=0x%04x\n",
+ readw(&dev->cap_regs->dciversion));
+ printk(KERN_DEBUG "dccparams=0x%08x\n",
+ readl(&dev->cap_regs->dccparams));
+
+ /* Operational Registers */
+ printk(KERN_DEBUG "Operational Registers (offset: "
+ "0x%04x, length: 0x%08x)\n",
+ OP_REG_OFFSET,
+ (u32)sizeof(struct langwell_op_regs));
+ printk(KERN_DEBUG "extsts=0x%08x\n",
+ readl(&dev->op_regs->extsts));
+ printk(KERN_DEBUG "extintr=0x%08x\n",
+ readl(&dev->op_regs->extintr));
+ printk(KERN_DEBUG "usbcmd=0x%08x\n",
+ readl(&dev->op_regs->usbcmd));
+ printk(KERN_DEBUG "usbsts=0x%08x\n",
+ readl(&dev->op_regs->usbsts));
+ printk(KERN_DEBUG "usbintr=0x%08x\n",
+ readl(&dev->op_regs->usbintr));
+ printk(KERN_DEBUG "frindex=0x%08x\n",
+ readl(&dev->op_regs->frindex));
+ printk(KERN_DEBUG "ctrldssegment=0x%08x\n",
+ readl(&dev->op_regs->ctrldssegment));
+ printk(KERN_DEBUG "deviceaddr=0x%08x\n",
+ readl(&dev->op_regs->deviceaddr));
+ printk(KERN_DEBUG "endpointlistaddr=0x%08x\n",
+ readl(&dev->op_regs->endpointlistaddr));
+ printk(KERN_DEBUG "ttctrl=0x%08x\n",
+ readl(&dev->op_regs->ttctrl));
+ printk(KERN_DEBUG "burstsize=0x%08x\n",
+ readl(&dev->op_regs->burstsize));
+ printk(KERN_DEBUG "txfilltuning=0x%08x\n",
+ readl(&dev->op_regs->txfilltuning));
+ printk(KERN_DEBUG "txttfilltuning=0x%08x\n",
+ readl(&dev->op_regs->txttfilltuning));
+ printk(KERN_DEBUG "ic_usb=0x%08x\n",
+ readl(&dev->op_regs->ic_usb));
+ printk(KERN_DEBUG "ulpi_viewport=0x%08x\n",
+ readl(&dev->op_regs->ulpi_viewport));
+ printk(KERN_DEBUG "configflag=0x%08x\n",
+ readl(&dev->op_regs->configflag));
+ printk(KERN_DEBUG "portsc1=0x%08x\n",
+ readl(&dev->op_regs->portsc1));
+ printk(KERN_DEBUG "devlc=0x%08x\n",
+ readl(&dev->op_regs->devlc));
+ printk(KERN_DEBUG "otgsc=0x%08x\n",
+ readl(&dev->op_regs->otgsc));
+ printk(KERN_DEBUG "usbmode=0x%08x\n",
+ readl(&dev->op_regs->usbmode));
+ printk(KERN_DEBUG "endptnak=0x%08x\n",
+ readl(&dev->op_regs->endptnak));
+ printk(KERN_DEBUG "endptnaken=0x%08x\n",
+ readl(&dev->op_regs->endptnaken));
+ printk(KERN_DEBUG "endptsetupstat=0x%08x\n",
+ readl(&dev->op_regs->endptsetupstat));
+ printk(KERN_DEBUG "endptprime=0x%08x\n",
+ readl(&dev->op_regs->endptprime));
+ printk(KERN_DEBUG "endptflush=0x%08x\n",
+ readl(&dev->op_regs->endptflush));
+ printk(KERN_DEBUG "endptstat=0x%08x\n",
+ readl(&dev->op_regs->endptstat));
+ printk(KERN_DEBUG "endptcomplete=0x%08x\n",
+ readl(&dev->op_regs->endptcomplete));
+
+ for (i = 0; i < dev->ep_max / 2; i++) {
+ printk(KERN_DEBUG "endptctrl[%d]=0x%08x\n",
+ i, readl(&dev->op_regs->endptctrl[i]));
+ }
+}
+#endif /* VERBOSE */
+
+
+/*-------------------------------------------------------------------------*/
+
+#define DIR_STRING(bAddress) (((bAddress) & USB_DIR_IN) ? "in" : "out")
+
+#define is_in(ep) (((ep)->ep_num == 0) ? ((ep)->dev->ep0_dir == \
+ USB_DIR_IN) : ((ep)->desc->bEndpointAddress \
+ & USB_DIR_IN) == USB_DIR_IN)
+
+
+#ifdef DEBUG
+static char *type_string(u8 bmAttributes)
+{
+ switch ((bmAttributes) & USB_ENDPOINT_XFERTYPE_MASK) {
+ case USB_ENDPOINT_XFER_BULK:
+ return "bulk";
+ case USB_ENDPOINT_XFER_ISOC:
+ return "iso";
+ case USB_ENDPOINT_XFER_INT:
+ return "int";
+ };
+
+ return "control";
+}
+#endif
+
+
+/* configure endpoint control registers */
+static void ep_reset(struct langwell_ep *ep, unsigned char ep_num,
+ unsigned char is_in, unsigned char ep_type)
+{
+ struct langwell_udc *dev;
+ u32 endptctrl;
+
+ dev = ep->dev;
+ VDBG(dev, "---> %s()\n", __func__);
+
+ endptctrl = readl(&dev->op_regs->endptctrl[ep_num]);
+ if (is_in) { /* TX */
+ if (ep_num)
+ endptctrl |= EPCTRL_TXR;
+ endptctrl |= EPCTRL_TXE;
+ endptctrl |= ep_type << EPCTRL_TXT_SHIFT;
+ } else { /* RX */
+ if (ep_num)
+ endptctrl |= EPCTRL_RXR;
+ endptctrl |= EPCTRL_RXE;
+ endptctrl |= ep_type << EPCTRL_RXT_SHIFT;
+ }
+
+ writel(endptctrl, &dev->op_regs->endptctrl[ep_num]);
+
+ VDBG(dev, "<--- %s()\n", __func__);
+}
+
+
+/* reset ep0 dQH and endptctrl */
+static void ep0_reset(struct langwell_udc *dev)
+{
+ struct langwell_ep *ep;
+ int i;
+
+ VDBG(dev, "---> %s()\n", __func__);
+
+ /* ep0 in and out */
+ for (i = 0; i < 2; i++) {
+ ep = &dev->ep[i];
+ ep->dev = dev;
+
+ /* ep0 dQH */
+ ep->dqh = &dev->ep_dqh[i];
+
+ /* configure ep0 endpoint capabilities in dQH */
+ ep->dqh->dqh_ios = 1;
+ ep->dqh->dqh_mpl = EP0_MAX_PKT_SIZE;
+
+ /* FIXME: enable ep0-in HW zero length termination select */
+ if (is_in(ep))
+ ep->dqh->dqh_zlt = 0;
+ ep->dqh->dqh_mult = 0;
+
+ /* configure ep0 control registers */
+ ep_reset(&dev->ep[0], 0, i, USB_ENDPOINT_XFER_CONTROL);
+ }
+
+ VDBG(dev, "<--- %s()\n", __func__);
+ return;
+}
+
+
+/*-------------------------------------------------------------------------*/
+
+/* endpoints operations */
+
+/* configure endpoint, making it usable */
+static int langwell_ep_enable(struct usb_ep *_ep,
+ const struct usb_endpoint_descriptor *desc)
+{
+ struct langwell_udc *dev;
+ struct langwell_ep *ep;
+ u16 max = 0;
+ unsigned long flags;
+ int retval = 0;
+ unsigned char zlt, ios = 0, mult = 0;
+
+ ep = container_of(_ep, struct langwell_ep, ep);
+ dev = ep->dev;
+ VDBG(dev, "---> %s()\n", __func__);
+
+ if (!_ep || !desc || ep->desc
+ || desc->bDescriptorType != USB_DT_ENDPOINT)
+ return -EINVAL;
+
+ if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
+ return -ESHUTDOWN;
+
+ max = le16_to_cpu(desc->wMaxPacketSize);
+
+ /*
+ * disable HW zero length termination select
+ * driver handles zero length packet through req->req.zero
+ */
+ zlt = 1;
+
+ /*
+ * sanity check type, direction, address, and then
+ * initialize the endpoint capabilities fields in dQH
+ */
+ switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
+ case USB_ENDPOINT_XFER_CONTROL:
+ ios = 1;
+ break;
+ case USB_ENDPOINT_XFER_BULK:
+ if ((dev->gadget.speed == USB_SPEED_HIGH
+ && max != 512)
+ || (dev->gadget.speed == USB_SPEED_FULL
+ && max > 64)) {
+ goto done;
+ }
+ break;
+ case USB_ENDPOINT_XFER_INT:
+ if (strstr(ep->ep.name, "-iso")) /* bulk is ok */
+ goto done;
+
+ switch (dev->gadget.speed) {
+ case USB_SPEED_HIGH:
+ if (max <= 1024)
+ break;
+ case USB_SPEED_FULL:
+ if (max <= 64)
+ break;
+ default:
+ if (max <= 8)
+ break;
+ goto done;
+ }
+ break;
+ case USB_ENDPOINT_XFER_ISOC:
+ if (strstr(ep->ep.name, "-bulk")
+ || strstr(ep->ep.name, "-int"))
+ goto done;
+
+ switch (dev->gadget.speed) {
+ case USB_SPEED_HIGH:
+ if (max <= 1024)
+ break;
+ case USB_SPEED_FULL:
+ if (max <= 1023)
+ break;
+ default:
+ goto done;
+ }
+ /*
+ * FIXME:
+ * calculate transactions needed for high bandwidth iso
+ */
+ mult = (unsigned char)(1 + ((max >> 11) & 0x03));
+ max = max & 0x8ff; /* bit 0~10 */
+ /* 3 transactions at most */
+ if (mult > 3)
+ goto done;
+ break;
+ default:
+ goto done;
+ }
+
+ spin_lock_irqsave(&dev->lock, flags);
+
+ /* configure endpoint capabilities in dQH */
+ ep->dqh->dqh_ios = ios;
+ ep->dqh->dqh_mpl = cpu_to_le16(max);
+ ep->dqh->dqh_zlt = zlt;
+ ep->dqh->dqh_mult = mult;
+
+ ep->ep.maxpacket = max;
+ ep->desc = desc;
+ ep->stopped = 0;
+ ep->ep_num = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
+
+ /* ep_type */
+ ep->ep_type = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
+
+ /* configure endpoint control registers */
+ ep_reset(ep, ep->ep_num, is_in(ep), ep->ep_type);
+
+ DBG(dev, "enabled %s (ep%d%s-%s), max %04x\n",
+ _ep->name,
+ ep->ep_num,
+ DIR_STRING(desc->bEndpointAddress),
+ type_string(desc->bmAttributes),
+ max);
+
+ spin_unlock_irqrestore(&dev->lock, flags);
+done:
+ VDBG(dev, "<--- %s()\n", __func__);
+ return retval;
+}
+
+
+/*-------------------------------------------------------------------------*/
+
+/* retire a request */
+static void done(struct langwell_ep *ep, struct langwell_request *req,
+ int status)
+{
+ struct langwell_udc *dev = ep->dev;
+ unsigned stopped = ep->stopped;
+ struct langwell_dtd *curr_dtd, *next_dtd;
+ int i;
+
+ VDBG(dev, "---> %s()\n", __func__);
+
+ /* remove the req from ep->queue */
+ list_del_init(&req->queue);
+
+ if (req->req.status == -EINPROGRESS)
+ req->req.status = status;
+ else
+ status = req->req.status;
+
+ /* free dTD for the request */
+ next_dtd = req->head;
+ for (i = 0; i < req->dtd_count; i++) {
+ curr_dtd = next_dtd;
+ if (i != req->dtd_count - 1)
+ next_dtd = curr_dtd->next_dtd_virt;
+ dma_pool_free(dev->dtd_pool, curr_dtd, curr_dtd->dtd_dma);
+ }
+
+ if (req->mapped) {
+ dma_unmap_single(&dev->pdev->dev, req->req.dma, req->req.length,
+ is_in(ep) ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
+ req->req.dma = DMA_ADDR_INVALID;
+ req->mapped = 0;
+ } else
+ dma_sync_single_for_cpu(&dev->pdev->dev, req->req.dma,
+ req->req.length,
+ is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
+
+ if (status != -ESHUTDOWN)
+ DBG(dev, "complete %s, req %p, stat %d, len %u/%u\n",
+ ep->ep.name, &req->req, status,
+ req->req.actual, req->req.length);
+
+ /* don't modify queue heads during completion callback */
+ ep->stopped = 1;
+
+ spin_unlock(&dev->lock);
+ /* complete routine from gadget driver */
+ if (req->req.complete)
+ req->req.complete(&ep->ep, &req->req);
+
+ spin_lock(&dev->lock);
+ ep->stopped = stopped;
+
+ VDBG(dev, "<--- %s()\n", __func__);
+}
+
+
+static void langwell_ep_fifo_flush(struct usb_ep *_ep);
+
+/* delete all endpoint requests, called with spinlock held */
+static void nuke(struct langwell_ep *ep, int status)
+{
+ /* called with spinlock held */
+ ep->stopped = 1;
+
+ /* endpoint fifo flush */
+ if (&ep->ep && ep->desc)
+ langwell_ep_fifo_flush(&ep->ep);
+
+ while (!list_empty(&ep->queue)) {
+ struct langwell_request *req = NULL;
+ req = list_entry(ep->queue.next, struct langwell_request,
+ queue);
+ done(ep, req, status);
+ }
+}
+
+
+/*-------------------------------------------------------------------------*/
+
+/* endpoint is no longer usable */
+static int langwell_ep_disable(struct usb_ep *_ep)
+{
+ struct langwell_ep *ep;
+ unsigned long flags;
+ struct langwell_udc *dev;
+ int ep_num;
+ u32 endptctrl;
+
+ ep = container_of(_ep, struct langwell_ep, ep);
+ dev = ep->dev;
+ VDBG(dev, "---> %s()\n", __func__);
+
+ if (!_ep || !ep->desc)
+ return -EINVAL;
+
+ spin_lock_irqsave(&dev->lock, flags);
+
+ /* disable endpoint control register */
+ ep_num = ep->ep_num;
+ endptctrl = readl(&dev->op_regs->endptctrl[ep_num]);
+ if (is_in(ep))
+ endptctrl &= ~EPCTRL_TXE;
+ else
+ endptctrl &= ~EPCTRL_RXE;
+ writel(endptctrl, &dev->op_regs->endptctrl[ep_num]);
+
+ /* nuke all pending requests (does flush) */
+ nuke(ep, -ESHUTDOWN);
+
+ ep->desc = NULL;
+ ep->stopped = 1;
+
+ spin_unlock_irqrestore(&dev->lock, flags);
+
+ DBG(dev, "disabled %s\n", _ep->name);
+ VDBG(dev, "<--- %s()\n", __func__);
+
+ return 0;
+}
+
+
+/* allocate a request object to use with this endpoint */
+static struct usb_request *langwell_alloc_request(struct usb_ep *_ep,
+ gfp_t gfp_flags)
+{
+ struct langwell_ep *ep;
+ struct langwell_udc *dev;
+ struct langwell_request *req = NULL;
+
+ if (!_ep)
+ return NULL;
+
+ ep = container_of(_ep, struct langwell_ep, ep);
+ dev = ep->dev;
+ VDBG(dev, "---> %s()\n", __func__);
+
+ req = kzalloc(sizeof(*req), gfp_flags);
+ if (!req)
+ return NULL;
+
+ req->req.dma = DMA_ADDR_INVALID;
+ INIT_LIST_HEAD(&req->queue);
+
+ VDBG(dev, "alloc request for %s\n", _ep->name);
+ VDBG(dev, "<--- %s()\n", __func__);
+ return &req->req;
+}
+
+
+/* free a request object */
+static void langwell_free_request(struct usb_ep *_ep,
+ struct usb_request *_req)
+{
+ struct langwell_ep *ep;
+ struct langwell_udc *dev;
+ struct langwell_request *req = NULL;
+
+ ep = container_of(_ep, struct langwell_ep, ep);
+ dev = ep->dev;
+ VDBG(dev, "---> %s()\n", __func__);
+
+ if (!_ep || !_req)
+ return;
+
+ req = container_of(_req, struct langwell_request, req);
+ WARN_ON(!list_empty(&req->queue));
+
+ if (_req)
+ kfree(req);
+
+ VDBG(dev, "free request for %s\n", _ep->name);
+ VDBG(dev, "<--- %s()\n", __func__);
+}
+
+
+/*-------------------------------------------------------------------------*/
+
+/* queue dTD and PRIME endpoint */
+static int queue_dtd(struct langwell_ep *ep, struct langwell_request *req)
+{
+ u32 bit_mask, usbcmd, endptstat, dtd_dma;
+ u8 dtd_status;
+ int i;
+ struct langwell_dqh *dqh;
+ struct langwell_udc *dev;
+
+ dev = ep->dev;
+ VDBG(dev, "---> %s()\n", __func__);
+
+ i = ep->ep_num * 2 + is_in(ep);
+ dqh = &dev->ep_dqh[i];
+
+ if (ep->ep_num)
+ VDBG(dev, "%s\n", ep->name);
+ else
+ /* ep0 */
+ VDBG(dev, "%s-%s\n", ep->name, is_in(ep) ? "in" : "out");
+
+ VDBG(dev, "ep_dqh[%d] addr: 0x%08x\n", i, (u32)&(dev->ep_dqh[i]));
+
+ bit_mask = is_in(ep) ?
+ (1 << (ep->ep_num + 16)) : (1 << (ep->ep_num));
+
+ VDBG(dev, "bit_mask = 0x%08x\n", bit_mask);
+
+ /* check if the pipe is empty */
+ if (!(list_empty(&ep->queue))) {
+ /* add dTD to the end of linked list */
+ struct langwell_request *lastreq;
+ lastreq = list_entry(ep->queue.prev,
+ struct langwell_request, queue);
+
+ lastreq->tail->dtd_next =
+ cpu_to_le32(req->head->dtd_dma & DTD_NEXT_MASK);
+
+ /* read prime bit, if 1 goto out */
+ if (readl(&dev->op_regs->endptprime) & bit_mask)
+ goto out;
+
+ do {
+ /* set ATDTW bit in USBCMD */
+ usbcmd = readl(&dev->op_regs->usbcmd);
+ writel(usbcmd | CMD_ATDTW, &dev->op_regs->usbcmd);
+
+ /* read correct status bit */
+ endptstat = readl(&dev->op_regs->endptstat) & bit_mask;
+
+ } while (!(readl(&dev->op_regs->usbcmd) & CMD_ATDTW));
+
+ /* write ATDTW bit to 0 */
+ usbcmd = readl(&dev->op_regs->usbcmd);
+ writel(usbcmd & ~CMD_ATDTW, &dev->op_regs->usbcmd);
+
+ if (endptstat)
+ goto out;
+ }
+
+ /* write dQH next pointer and terminate bit to 0 */
+ dtd_dma = req->head->dtd_dma & DTD_NEXT_MASK;
+ dqh->dtd_next = cpu_to_le32(dtd_dma);
+
+ /* clear active and halt bit */
+ dtd_status = (u8) ~(DTD_STS_ACTIVE | DTD_STS_HALTED);
+ dqh->dtd_status &= dtd_status;
+ VDBG(dev, "dqh->dtd_status = 0x%x\n", dqh->dtd_status);
+
+ /* write 1 to endptprime register to PRIME endpoint */
+ bit_mask = is_in(ep) ? (1 << (ep->ep_num + 16)) : (1 << ep->ep_num);
+ VDBG(dev, "endprime bit_mask = 0x%08x\n", bit_mask);
+ writel(bit_mask, &dev->op_regs->endptprime);
+out:
+ VDBG(dev, "<--- %s()\n", __func__);
+ return 0;
+}
+
+
+/* fill in the dTD structure to build a transfer descriptor */
+static struct langwell_dtd *build_dtd(struct langwell_request *req,
+ unsigned *length, dma_addr_t *dma, int *is_last)
+{
+ u32 buf_ptr;
+ struct langwell_dtd *dtd;
+ struct langwell_udc *dev;
+ int i;
+
+ dev = req->ep->dev;
+ VDBG(dev, "---> %s()\n", __func__);
+
+ /* the maximum transfer length, up to 16k bytes */
+ *length = min(req->req.length - req->req.actual,
+ (unsigned)DTD_MAX_TRANSFER_LENGTH);
+
+ /* create dTD dma_pool resource */
+ dtd = dma_pool_alloc(dev->dtd_pool, GFP_KERNEL, dma);
+ if (dtd == NULL)
+ return dtd;
+ dtd->dtd_dma = *dma;
+
+ /* initialize buffer page pointers */
+ buf_ptr = (u32)(req->req.dma + req->req.actual);
+ for (i = 0; i < 5; i++)
+ dtd->dtd_buf[i] = cpu_to_le32(buf_ptr + i * PAGE_SIZE);
+
+ req->req.actual += *length;
+
+ /* fill in total bytes with transfer size */
+ dtd->dtd_total = cpu_to_le16(*length);
+ VDBG(dev, "dtd->dtd_total = %d\n", dtd->dtd_total);
+
+ /* set is_last flag if req->req.zero is set or not */
+ if (req->req.zero) {
+ if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0)
+ *is_last = 1;
+ else
+ *is_last = 0;
+ } else if (req->req.length == req->req.actual) {
+ *is_last = 1;
+ } else
+ *is_last = 0;
+
+ if (*is_last == 0)
+ VDBG(dev, "multi-dtd request!\n");
+
+ /* set interrupt on complete bit for the last dTD */
+ if (*is_last && !req->req.no_interrupt)
+ dtd->dtd_ioc = 1;
+
+ /* set multiplier override 0 for non-ISO and non-TX endpoint */
+ dtd->dtd_multo = 0;
+
+ /* set the active bit of status field to 1 */
+ dtd->dtd_status = DTD_STS_ACTIVE;
+ VDBG(dev, "dtd->dtd_status = 0x%02x\n", dtd->dtd_status);
+
+ VDBG(dev, "length = %d, dma addr= 0x%08x\n", *length, (int)*dma);
+ VDBG(dev, "<--- %s()\n", __func__);
+ return dtd;
+}
+
+
+/* generate dTD linked list for a request */
+static int req_to_dtd(struct langwell_request *req)
+{
+ unsigned count;
+ int is_last, is_first = 1;
+ struct langwell_dtd *dtd, *last_dtd = NULL;
+ struct langwell_udc *dev;
+ dma_addr_t dma;
+
+ dev = req->ep->dev;
+ VDBG(dev, "---> %s()\n", __func__);
+ do {
+ dtd = build_dtd(req, &count, &dma, &is_last);
+ if (dtd == NULL)
+ return -ENOMEM;
+
+ if (is_first) {
+ is_first = 0;
+ req->head = dtd;
+ } else {
+ last_dtd->dtd_next = cpu_to_le32(dma);
+ last_dtd->next_dtd_virt = dtd;
+ }
+ last_dtd = dtd;
+ req->dtd_count++;
+ } while (!is_last);
+
+ /* set terminate bit to 1 for the last dTD */
+ dtd->dtd_next = DTD_TERM;
+
+ req->tail = dtd;
+
+ VDBG(dev, "<--- %s()\n", __func__);
+ return 0;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* queue (submits) an I/O requests to an endpoint */
+static int langwell_ep_queue(struct usb_ep *_ep, struct usb_request *_req,
+ gfp_t gfp_flags)
+{
+ struct langwell_request *req;
+ struct langwell_ep *ep;
+ struct langwell_udc *dev;
+ unsigned long flags;
+ int is_iso = 0, zlflag = 0;
+
+ /* always require a cpu-view buffer */
+ req = container_of(_req, struct langwell_request, req);
+ ep = container_of(_ep, struct langwell_ep, ep);
+
+ if (!_req || !_req->complete || !_req->buf
+ || !list_empty(&req->queue)) {
+ return -EINVAL;
+ }
+
+ if (unlikely(!_ep || !ep->desc))
+ return -EINVAL;
+
+ dev = ep->dev;
+ req->ep = ep;
+ VDBG(dev, "---> %s()\n", __func__);
+
+ if (ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
+ if (req->req.length > ep->ep.maxpacket)
+ return -EMSGSIZE;
+ is_iso = 1;
+ }
+
+ if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN))
+ return -ESHUTDOWN;
+
+ /* set up dma mapping in case the caller didn't */
+ if (_req->dma == DMA_ADDR_INVALID) {
+ /* WORKAROUND: WARN_ON(size == 0) */
+ if (_req->length == 0) {
+ VDBG(dev, "req->length: 0->1\n");
+ zlflag = 1;
+ _req->length++;
+ }
+
+ _req->dma = dma_map_single(&dev->pdev->dev,
+ _req->buf, _req->length,
+ is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
+ if (zlflag && (_req->length == 1)) {
+ VDBG(dev, "req->length: 1->0\n");
+ zlflag = 0;
+ _req->length = 0;
+ }
+
+ req->mapped = 1;
+ VDBG(dev, "req->mapped = 1\n");
+ } else {
+ dma_sync_single_for_device(&dev->pdev->dev,
+ _req->dma, _req->length,
+ is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
+ req->mapped = 0;
+ VDBG(dev, "req->mapped = 0\n");
+ }
+
+ DBG(dev, "%s queue req %p, len %u, buf %p, dma 0x%08x\n",
+ _ep->name,
+ _req, _req->length, _req->buf, _req->dma);
+
+ _req->status = -EINPROGRESS;
+ _req->actual = 0;
+ req->dtd_count = 0;
+
+ spin_lock_irqsave(&dev->lock, flags);
+
+ /* build and put dTDs to endpoint queue */
+ if (!req_to_dtd(req)) {
+ queue_dtd(ep, req);
+ } else {
+ spin_unlock_irqrestore(&dev->lock, flags);
+ return -ENOMEM;
+ }
+
+ /* update ep0 state */
+ if (ep->ep_num == 0)
+ dev->ep0_state = DATA_STATE_XMIT;
+
+ if (likely(req != NULL)) {
+ list_add_tail(&req->queue, &ep->queue);
+ VDBG(dev, "list_add_tail() \n");
+ }
+
+ spin_unlock_irqrestore(&dev->lock, flags);
+
+ VDBG(dev, "<--- %s()\n", __func__);
+ return 0;
+}
+
+
+/* dequeue (cancels, unlinks) an I/O request from an endpoint */
+static int langwell_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
+{
+ struct langwell_ep *ep;
+ struct langwell_udc *dev;
+ struct langwell_request *req;
+ unsigned long flags;
+ int stopped, ep_num, retval = 0;
+ u32 endptctrl;
+
+ ep = container_of(_ep, struct langwell_ep, ep);
+ dev = ep->dev;
+ VDBG(dev, "---> %s()\n", __func__);
+
+ if (!_ep || !ep->desc || !_req)
+ return -EINVAL;
+
+ if (!dev->driver)
+ return -ESHUTDOWN;
+
+ spin_lock_irqsave(&dev->lock, flags);
+ stopped = ep->stopped;
+
+ /* quiesce dma while we patch the queue */
+ ep->stopped = 1;
+ ep_num = ep->ep_num;
+
+ /* disable endpoint control register */
+ endptctrl = readl(&dev->op_regs->endptctrl[ep_num]);
+ if (is_in(ep))
+ endptctrl &= ~EPCTRL_TXE;
+ else
+ endptctrl &= ~EPCTRL_RXE;
+ writel(endptctrl, &dev->op_regs->endptctrl[ep_num]);
+
+ /* make sure it's still queued on this endpoint */
+ list_for_each_entry(req, &ep->queue, queue) {
+ if (&req->req == _req)
+ break;
+ }
+
+ if (&req->req != _req) {
+ retval = -EINVAL;
+ goto done;
+ }
+
+ /* queue head may be partially complete. */
+ if (ep->queue.next == &req->queue) {
+ DBG(dev, "unlink (%s) dma\n", _ep->name);
+ _req->status = -ECONNRESET;
+ langwell_ep_fifo_flush(&ep->ep);
+
+ /* not the last request in endpoint queue */
+ if (likely(ep->queue.next == &req->queue)) {
+ struct langwell_dqh *dqh;
+ struct langwell_request *next_req;
+
+ dqh = ep->dqh;
+ next_req = list_entry(req->queue.next,
+ struct langwell_request, queue);
+
+ /* point the dQH to the first dTD of next request */
+ writel((u32) next_req->head, &dqh->dqh_current);
+ }
+ } else {
+ struct langwell_request *prev_req;
+
+ prev_req = list_entry(req->queue.prev,
+ struct langwell_request, queue);
+ writel(readl(&req->tail->dtd_next),
+ &prev_req->tail->dtd_next);
+ }
+
+ done(ep, req, -ECONNRESET);
+
+done:
+ /* enable endpoint again */
+ endptctrl = readl(&dev->op_regs->endptctrl[ep_num]);
+ if (is_in(ep))
+ endptctrl |= EPCTRL_TXE;
+ else
+ endptctrl |= EPCTRL_RXE;
+ writel(endptctrl, &dev->op_regs->endptctrl[ep_num]);
+
+ ep->stopped = stopped;
+ spin_unlock_irqrestore(&dev->lock, flags);
+
+ VDBG(dev, "<--- %s()\n", __func__);
+ return retval;
+}
+
+
+/*-------------------------------------------------------------------------*/
+
+/* endpoint set/clear halt */
+static void ep_set_halt(struct langwell_ep *ep, int value)
+{
+ u32 endptctrl = 0;
+ int ep_num;
+ struct langwell_udc *dev = ep->dev;
+ VDBG(dev, "---> %s()\n", __func__);
+
+ ep_num = ep->ep_num;
+ endptctrl = readl(&dev->op_regs->endptctrl[ep_num]);
+
+ /* value: 1 - set halt, 0 - clear halt */
+ if (value) {
+ /* set the stall bit */
+ if (is_in(ep))
+ endptctrl |= EPCTRL_TXS;
+ else
+ endptctrl |= EPCTRL_RXS;
+ } else {
+ /* clear the stall bit and reset data toggle */
+ if (is_in(ep)) {
+ endptctrl &= ~EPCTRL_TXS;
+ endptctrl |= EPCTRL_TXR;
+ } else {
+ endptctrl &= ~EPCTRL_RXS;
+ endptctrl |= EPCTRL_RXR;
+ }
+ }
+
+ writel(endptctrl, &dev->op_regs->endptctrl[ep_num]);
+
+ VDBG(dev, "<--- %s()\n", __func__);
+}
+
+
+/* set the endpoint halt feature */
+static int langwell_ep_set_halt(struct usb_ep *_ep, int value)
+{
+ struct langwell_ep *ep;
+ struct langwell_udc *dev;
+ unsigned long flags;
+ int retval = 0;
+
+ ep = container_of(_ep, struct langwell_ep, ep);
+ dev = ep->dev;
+
+ VDBG(dev, "---> %s()\n", __func__);
+
+ if (!_ep || !ep->desc)
+ return -EINVAL;
+
+ if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
+ return -ESHUTDOWN;
+
+ if (ep->desc && (ep->desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK)
+ == USB_ENDPOINT_XFER_ISOC)
+ return -EOPNOTSUPP;
+
+ spin_lock_irqsave(&dev->lock, flags);
+
+ /*
+ * attempt to halt IN ep will fail if any transfer requests
+ * are still queue
+ */
+ if (!list_empty(&ep->queue) && is_in(ep) && value) {
+ /* IN endpoint FIFO holds bytes */
+ DBG(dev, "%s FIFO holds bytes\n", _ep->name);
+ retval = -EAGAIN;
+ goto done;
+ }
+
+ /* endpoint set/clear halt */
+ if (ep->ep_num) {
+ ep_set_halt(ep, value);
+ } else { /* endpoint 0 */
+ dev->ep0_state = WAIT_FOR_SETUP;
+ dev->ep0_dir = USB_DIR_OUT;
+ }
+done:
+ spin_unlock_irqrestore(&dev->lock, flags);
+ DBG(dev, "%s %s halt\n", _ep->name, value ? "set" : "clear");
+ VDBG(dev, "<--- %s()\n", __func__);
+ return retval;
+}
+
+
+/* set the halt feature and ignores clear requests */
+static int langwell_ep_set_wedge(struct usb_ep *_ep)
+{
+ struct langwell_ep *ep;
+ struct langwell_udc *dev;
+
+ ep = container_of(_ep, struct langwell_ep, ep);
+ dev = ep->dev;
+
+ VDBG(dev, "---> %s()\n", __func__);
+
+ if (!_ep || !ep->desc)
+ return -EINVAL;
+
+ VDBG(dev, "<--- %s()\n", __func__);
+ return usb_ep_set_halt(_ep);
+}
+
+
+/* flush contents of a fifo */
+static void langwell_ep_fifo_flush(struct usb_ep *_ep)
+{
+ struct langwell_ep *ep;
+ struct langwell_udc *dev;
+ u32 flush_bit;
+ unsigned long timeout;
+
+ ep = container_of(_ep, struct langwell_ep, ep);
+ dev = ep->dev;
+
+ VDBG(dev, "---> %s()\n", __func__);
+
+ if (!_ep || !ep->desc) {
+ VDBG(dev, "ep or ep->desc is NULL\n");
+ VDBG(dev, "<--- %s()\n", __func__);
+ return;
+ }
+
+ VDBG(dev, "%s-%s fifo flush\n", _ep->name, is_in(ep) ? "in" : "out");
+
+ /* flush endpoint buffer */
+ if (ep->ep_num == 0)
+ flush_bit = (1 << 16) | 1;
+ else if (is_in(ep))
+ flush_bit = 1 << (ep->ep_num + 16); /* TX */
+ else
+ flush_bit = 1 << ep->ep_num; /* RX */
+
+ /* wait until flush complete */
+ timeout = jiffies + FLUSH_TIMEOUT;
+ do {
+ writel(flush_bit, &dev->op_regs->endptflush);
+ while (readl(&dev->op_regs->endptflush)) {
+ if (time_after(jiffies, timeout)) {
+ ERROR(dev, "ep flush timeout\n");
+ goto done;
+ }
+ cpu_relax();
+ }
+ } while (readl(&dev->op_regs->endptstat) & flush_bit);
+done:
+ VDBG(dev, "<--- %s()\n", __func__);
+}
+
+
+/* endpoints operations structure */
+static const struct usb_ep_ops langwell_ep_ops = {
+
+ /* configure endpoint, making it usable */
+ .enable = langwell_ep_enable,
+
+ /* endpoint is no longer usable */
+ .disable = langwell_ep_disable,
+
+ /* allocate a request object to use with this endpoint */
+ .alloc_request = langwell_alloc_request,
+
+ /* free a request object */
+ .free_request = langwell_free_request,
+
+ /* queue (submits) an I/O requests to an endpoint */
+ .queue = langwell_ep_queue,
+
+ /* dequeue (cancels, unlinks) an I/O request from an endpoint */
+ .dequeue = langwell_ep_dequeue,
+
+ /* set the endpoint halt feature */
+ .set_halt = langwell_ep_set_halt,
+
+ /* set the halt feature and ignores clear requests */
+ .set_wedge = langwell_ep_set_wedge,
+
+ /* flush contents of a fifo */
+ .fifo_flush = langwell_ep_fifo_flush,
+};
+
+
+/*-------------------------------------------------------------------------*/
+
+/* device controller usb_gadget_ops structure */
+
+/* returns the current frame number */
+static int langwell_get_frame(struct usb_gadget *_gadget)
+{
+ struct langwell_udc *dev;
+ u16 retval;
+
+ if (!_gadget)
+ return -ENODEV;
+
+ dev = container_of(_gadget, struct langwell_udc, gadget);
+ VDBG(dev, "---> %s()\n", __func__);
+
+ retval = readl(&dev->op_regs->frindex) & FRINDEX_MASK;
+
+ VDBG(dev, "<--- %s()\n", __func__);
+ return retval;
+}
+
+
+/* tries to wake up the host connected to this gadget */
+static int langwell_wakeup(struct usb_gadget *_gadget)
+{
+ struct langwell_udc *dev;
+ u32 portsc1, devlc;
+ unsigned long flags;
+
+ if (!_gadget)
+ return 0;
+
+ dev = container_of(_gadget, struct langwell_udc, gadget);
+ VDBG(dev, "---> %s()\n", __func__);
+
+ /* Remote Wakeup feature not enabled by host */
+ if (!dev->remote_wakeup)
+ return -ENOTSUPP;
+
+ spin_lock_irqsave(&dev->lock, flags);
+
+ portsc1 = readl(&dev->op_regs->portsc1);
+ if (!(portsc1 & PORTS_SUSP)) {
+ spin_unlock_irqrestore(&dev->lock, flags);
+ return 0;
+ }
+
+ /* LPM L1 to L0, remote wakeup */
+ if (dev->lpm && dev->lpm_state == LPM_L1) {
+ portsc1 |= PORTS_SLP;
+ writel(portsc1, &dev->op_regs->portsc1);
+ }
+
+ /* force port resume */
+ if (dev->usb_state == USB_STATE_SUSPENDED) {
+ portsc1 |= PORTS_FPR;
+ writel(portsc1, &dev->op_regs->portsc1);
+ }
+
+ /* exit PHY low power suspend */
+ devlc = readl(&dev->op_regs->devlc);
+ VDBG(dev, "devlc = 0x%08x\n", devlc);
+ devlc &= ~LPM_PHCD;
+ writel(devlc, &dev->op_regs->devlc);
+
+ spin_unlock_irqrestore(&dev->lock, flags);
+
+ VDBG(dev, "<--- %s()\n", __func__);
+ return 0;
+}
+
+
+/* notify controller that VBUS is powered or not */
+static int langwell_vbus_session(struct usb_gadget *_gadget, int is_active)
+{
+ struct langwell_udc *dev;
+ unsigned long flags;
+ u32 usbcmd;
+
+ if (!_gadget)
+ return -ENODEV;
+
+ dev = container_of(_gadget, struct langwell_udc, gadget);
+ VDBG(dev, "---> %s()\n", __func__);
+
+ spin_lock_irqsave(&dev->lock, flags);
+ VDBG(dev, "VBUS status: %s\n", is_active ? "on" : "off");
+
+ dev->vbus_active = (is_active != 0);
+ if (dev->driver && dev->softconnected && dev->vbus_active) {
+ usbcmd = readl(&dev->op_regs->usbcmd);
+ usbcmd |= CMD_RUNSTOP;
+ writel(usbcmd, &dev->op_regs->usbcmd);
+ } else {
+ usbcmd = readl(&dev->op_regs->usbcmd);
+ usbcmd &= ~CMD_RUNSTOP;
+ writel(usbcmd, &dev->op_regs->usbcmd);
+ }
+
+ spin_unlock_irqrestore(&dev->lock, flags);
+
+ VDBG(dev, "<--- %s()\n", __func__);
+ return 0;
+}
+
+
+/* constrain controller's VBUS power usage */
+static int langwell_vbus_draw(struct usb_gadget *_gadget, unsigned mA)
+{
+ struct langwell_udc *dev;
+
+ if (!_gadget)
+ return -ENODEV;
+
+ dev = container_of(_gadget, struct langwell_udc, gadget);
+ VDBG(dev, "---> %s()\n", __func__);
+
+ if (dev->transceiver) {
+ VDBG(dev, "otg_set_power\n");
+ VDBG(dev, "<--- %s()\n", __func__);
+ return otg_set_power(dev->transceiver, mA);
+ }
+
+ VDBG(dev, "<--- %s()\n", __func__);
+ return -ENOTSUPP;
+}
+
+
+/* D+ pullup, software-controlled connect/disconnect to USB host */
+static int langwell_pullup(struct usb_gadget *_gadget, int is_on)
+{
+ struct langwell_udc *dev;
+ u32 usbcmd;
+ unsigned long flags;
+
+ if (!_gadget)
+ return -ENODEV;
+
+ dev = container_of(_gadget, struct langwell_udc, gadget);
+
+ VDBG(dev, "---> %s()\n", __func__);
+
+ spin_lock_irqsave(&dev->lock, flags);
+ dev->softconnected = (is_on != 0);
+
+ if (dev->driver && dev->softconnected && dev->vbus_active) {
+ usbcmd = readl(&dev->op_regs->usbcmd);
+ usbcmd |= CMD_RUNSTOP;
+ writel(usbcmd, &dev->op_regs->usbcmd);
+ } else {
+ usbcmd = readl(&dev->op_regs->usbcmd);
+ usbcmd &= ~CMD_RUNSTOP;
+ writel(usbcmd, &dev->op_regs->usbcmd);
+ }
+ spin_unlock_irqrestore(&dev->lock, flags);
+
+ VDBG(dev, "<--- %s()\n", __func__);
+ return 0;
+}
+
+
+/* device controller usb_gadget_ops structure */
+static const struct usb_gadget_ops langwell_ops = {
+
+ /* returns the current frame number */
+ .get_frame = langwell_get_frame,
+
+ /* tries to wake up the host connected to this gadget */
+ .wakeup = langwell_wakeup,
+
+ /* set the device selfpowered feature, always selfpowered */
+ /* .set_selfpowered = langwell_set_selfpowered, */
+
+ /* notify controller that VBUS is powered or not */
+ .vbus_session = langwell_vbus_session,
+
+ /* constrain controller's VBUS power usage */
+ .vbus_draw = langwell_vbus_draw,
+
+ /* D+ pullup, software-controlled connect/disconnect to USB host */
+ .pullup = langwell_pullup,
+};
+
+
+/*-------------------------------------------------------------------------*/
+
+/* device controller operations */
+
+/* reset device controller */
+static int langwell_udc_reset(struct langwell_udc *dev)
+{
+ u32 usbcmd, usbmode, devlc, endpointlistaddr;
+ unsigned long timeout;
+
+ if (!dev)
+ return -EINVAL;
+
+ DBG(dev, "---> %s()\n", __func__);
+
+ /* set controller to stop state */
+ usbcmd = readl(&dev->op_regs->usbcmd);
+ usbcmd &= ~CMD_RUNSTOP;
+ writel(usbcmd, &dev->op_regs->usbcmd);
+
+ /* reset device controller */
+ usbcmd = readl(&dev->op_regs->usbcmd);
+ usbcmd |= CMD_RST;
+ writel(usbcmd, &dev->op_regs->usbcmd);
+
+ /* wait for reset to complete */
+ timeout = jiffies + RESET_TIMEOUT;
+ while (readl(&dev->op_regs->usbcmd) & CMD_RST) {
+ if (time_after(jiffies, timeout)) {
+ ERROR(dev, "device reset timeout\n");
+ return -ETIMEDOUT;
+ }
+ cpu_relax();
+ }
+
+ /* set controller to device mode */
+ usbmode = readl(&dev->op_regs->usbmode);
+ usbmode |= MODE_DEVICE;
+
+ /* turn setup lockout off, require setup tripwire in usbcmd */
+ usbmode |= MODE_SLOM;
+
+ writel(usbmode, &dev->op_regs->usbmode);
+ usbmode = readl(&dev->op_regs->usbmode);
+ VDBG(dev, "usbmode=0x%08x\n", usbmode);
+
+ /* Write-Clear setup status */
+ writel(0, &dev->op_regs->usbsts);
+
+ /* if support USB LPM, ACK all LPM token */
+ if (dev->lpm) {
+ devlc = readl(&dev->op_regs->devlc);
+ devlc &= ~LPM_STL; /* don't STALL LPM token */
+ devlc &= ~LPM_NYT_ACK; /* ACK LPM token */
+ writel(devlc, &dev->op_regs->devlc);
+ }
+
+ /* fill endpointlistaddr register */
+ endpointlistaddr = dev->ep_dqh_dma;
+ endpointlistaddr &= ENDPOINTLISTADDR_MASK;
+ writel(endpointlistaddr, &dev->op_regs->endpointlistaddr);
+
+ VDBG(dev, "dQH base (vir: %p, phy: 0x%08x), endpointlistaddr=0x%08x\n",
+ dev->ep_dqh, endpointlistaddr,
+ readl(&dev->op_regs->endpointlistaddr));
+ DBG(dev, "<--- %s()\n", __func__);
+ return 0;
+}
+
+
+/* reinitialize device controller endpoints */
+static int eps_reinit(struct langwell_udc *dev)
+{
+ struct langwell_ep *ep;
+ char name[14];
+ int i;
+
+ VDBG(dev, "---> %s()\n", __func__);
+
+ /* initialize ep0 */
+ ep = &dev->ep[0];
+ ep->dev = dev;
+ strncpy(ep->name, "ep0", sizeof(ep->name));
+ ep->ep.name = ep->name;
+ ep->ep.ops = &langwell_ep_ops;
+ ep->stopped = 0;
+ ep->ep.maxpacket = EP0_MAX_PKT_SIZE;
+ ep->ep_num = 0;
+ ep->desc = &langwell_ep0_desc;
+ INIT_LIST_HEAD(&ep->queue);
+
+ ep->ep_type = USB_ENDPOINT_XFER_CONTROL;
+
+ /* initialize other endpoints */
+ for (i = 2; i < dev->ep_max; i++) {
+ ep = &dev->ep[i];
+ if (i % 2)
+ snprintf(name, sizeof(name), "ep%din", i / 2);
+ else
+ snprintf(name, sizeof(name), "ep%dout", i / 2);
+ ep->dev = dev;
+ strncpy(ep->name, name, sizeof(ep->name));
+ ep->ep.name = ep->name;
+
+ ep->ep.ops = &langwell_ep_ops;
+ ep->stopped = 0;
+ ep->ep.maxpacket = (unsigned short) ~0;
+ ep->ep_num = i / 2;
+
+ INIT_LIST_HEAD(&ep->queue);
+ list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
+
+ ep->dqh = &dev->ep_dqh[i];
+ }
+
+ VDBG(dev, "<--- %s()\n", __func__);
+ return 0;
+}
+
+
+/* enable interrupt and set controller to run state */
+static void langwell_udc_start(struct langwell_udc *dev)
+{
+ u32 usbintr, usbcmd;
+ DBG(dev, "---> %s()\n", __func__);
+
+ /* enable interrupts */
+ usbintr = INTR_ULPIE /* ULPI */
+ | INTR_SLE /* suspend */
+ /* | INTR_SRE SOF received */
+ | INTR_URE /* USB reset */
+ | INTR_AAE /* async advance */
+ | INTR_SEE /* system error */
+ | INTR_FRE /* frame list rollover */
+ | INTR_PCE /* port change detect */
+ | INTR_UEE /* USB error interrupt */
+ | INTR_UE; /* USB interrupt */
+ writel(usbintr, &dev->op_regs->usbintr);
+
+ /* clear stopped bit */
+ dev->stopped = 0;
+
+ /* set controller to run */
+ usbcmd = readl(&dev->op_regs->usbcmd);
+ usbcmd |= CMD_RUNSTOP;
+ writel(usbcmd, &dev->op_regs->usbcmd);
+
+ DBG(dev, "<--- %s()\n", __func__);
+ return;
+}
+
+
+/* disable interrupt and set controller to stop state */
+static void langwell_udc_stop(struct langwell_udc *dev)
+{
+ u32 usbcmd;
+
+ DBG(dev, "---> %s()\n", __func__);
+
+ /* disable all interrupts */
+ writel(0, &dev->op_regs->usbintr);
+
+ /* set stopped bit */
+ dev->stopped = 1;
+
+ /* set controller to stop state */
+ usbcmd = readl(&dev->op_regs->usbcmd);
+ usbcmd &= ~CMD_RUNSTOP;
+ writel(usbcmd, &dev->op_regs->usbcmd);
+
+ DBG(dev, "<--- %s()\n", __func__);
+ return;
+}
+
+
+/* stop all USB activities */
+static void stop_activity(struct langwell_udc *dev,
+ struct usb_gadget_driver *driver)
+{
+ struct langwell_ep *ep;
+ DBG(dev, "---> %s()\n", __func__);
+
+ nuke(&dev->ep[0], -ESHUTDOWN);
+
+ list_for_each_entry(ep, &dev->gadget.ep_list, ep.ep_list) {
+ nuke(ep, -ESHUTDOWN);
+ }
+
+ /* report disconnect; the driver is already quiesced */
+ if (driver) {
+ spin_unlock(&dev->lock);
+ driver->disconnect(&dev->gadget);
+ spin_lock(&dev->lock);
+ }
+
+ DBG(dev, "<--- %s()\n", __func__);
+}
+
+
+/*-------------------------------------------------------------------------*/
+
+/* device "function" sysfs attribute file */
+static ssize_t show_function(struct device *_dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct langwell_udc *dev = the_controller;
+
+ if (!dev->driver || !dev->driver->function
+ || strlen(dev->driver->function) > PAGE_SIZE)
+ return 0;
+
+ return scnprintf(buf, PAGE_SIZE, "%s\n", dev->driver->function);
+}
+static DEVICE_ATTR(function, S_IRUGO, show_function, NULL);
+
+
+/* device "langwell_udc" sysfs attribute file */
+static ssize_t show_langwell_udc(struct device *_dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct langwell_udc *dev = the_controller;
+ struct langwell_request *req;
+ struct langwell_ep *ep = NULL;
+ char *next;
+ unsigned size;
+ unsigned t;
+ unsigned i;
+ unsigned long flags;
+ u32 tmp_reg;
+
+ next = buf;
+ size = PAGE_SIZE;
+ spin_lock_irqsave(&dev->lock, flags);
+
+ /* driver basic information */
+ t = scnprintf(next, size,
+ DRIVER_DESC "\n"
+ "%s version: %s\n"
+ "Gadget driver: %s\n\n",
+ driver_name, DRIVER_VERSION,
+ dev->driver ? dev->driver->driver.name : "(none)");
+ size -= t;
+ next += t;
+
+ /* device registers */
+ tmp_reg = readl(&dev->op_regs->usbcmd);
+ t = scnprintf(next, size,
+ "USBCMD reg:\n"
+ "SetupTW: %d\n"
+ "Run/Stop: %s\n\n",
+ (tmp_reg & CMD_SUTW) ? 1 : 0,
+ (tmp_reg & CMD_RUNSTOP) ? "Run" : "Stop");
+ size -= t;
+ next += t;
+
+ tmp_reg = readl(&dev->op_regs->usbsts);
+ t = scnprintf(next, size,
+ "USB Status Reg:\n"
+ "Device Suspend: %d\n"
+ "Reset Received: %d\n"
+ "System Error: %s\n"
+ "USB Error Interrupt: %s\n\n",
+ (tmp_reg & STS_SLI) ? 1 : 0,
+ (tmp_reg & STS_URI) ? 1 : 0,
+ (tmp_reg & STS_SEI) ? "Error" : "No error",
+ (tmp_reg & STS_UEI) ? "Error detected" : "No error");
+ size -= t;
+ next += t;
+
+ tmp_reg = readl(&dev->op_regs->usbintr);
+ t = scnprintf(next, size,
+ "USB Intrrupt Enable Reg:\n"
+ "Sleep Enable: %d\n"
+ "SOF Received Enable: %d\n"
+ "Reset Enable: %d\n"
+ "System Error Enable: %d\n"
+ "Port Change Dectected Enable: %d\n"
+ "USB Error Intr Enable: %d\n"
+ "USB Intr Enable: %d\n\n",
+ (tmp_reg & INTR_SLE) ? 1 : 0,
+ (tmp_reg & INTR_SRE) ? 1 : 0,
+ (tmp_reg & INTR_URE) ? 1 : 0,
+ (tmp_reg & INTR_SEE) ? 1 : 0,
+ (tmp_reg & INTR_PCE) ? 1 : 0,
+ (tmp_reg & INTR_UEE) ? 1 : 0,
+ (tmp_reg & INTR_UE) ? 1 : 0);
+ size -= t;
+ next += t;
+
+ tmp_reg = readl(&dev->op_regs->frindex);
+ t = scnprintf(next, size,
+ "USB Frame Index Reg:\n"
+ "Frame Number is 0x%08x\n\n",
+ (tmp_reg & FRINDEX_MASK));
+ size -= t;
+ next += t;
+
+ tmp_reg = readl(&dev->op_regs->deviceaddr);
+ t = scnprintf(next, size,
+ "USB Device Address Reg:\n"
+ "Device Addr is 0x%x\n\n",
+ USBADR(tmp_reg));
+ size -= t;
+ next += t;
+
+ tmp_reg = readl(&dev->op_regs->endpointlistaddr);
+ t = scnprintf(next, size,
+ "USB Endpoint List Address Reg:\n"
+ "Endpoint List Pointer is 0x%x\n\n",
+ EPBASE(tmp_reg));
+ size -= t;
+ next += t;
+
+ tmp_reg = readl(&dev->op_regs->portsc1);
+ t = scnprintf(next, size,
+ "USB Port Status & Control Reg:\n"
+ "Port Reset: %s\n"
+ "Port Suspend Mode: %s\n"
+ "Over-current Change: %s\n"
+ "Port Enable/Disable Change: %s\n"
+ "Port Enabled/Disabled: %s\n"
+ "Current Connect Status: %s\n\n",
+ (tmp_reg & PORTS_PR) ? "Reset" : "Not Reset",
+ (tmp_reg & PORTS_SUSP) ? "Suspend " : "Not Suspend",
+ (tmp_reg & PORTS_OCC) ? "Detected" : "No",
+ (tmp_reg & PORTS_PEC) ? "Changed" : "Not Changed",
+ (tmp_reg & PORTS_PE) ? "Enable" : "Not Correct",
+ (tmp_reg & PORTS_CCS) ? "Attached" : "Not Attached");
+ size -= t;
+ next += t;
+
+ tmp_reg = readl(&dev->op_regs->devlc);
+ t = scnprintf(next, size,
+ "Device LPM Control Reg:\n"
+ "Parallel Transceiver : %d\n"
+ "Serial Transceiver : %d\n"
+ "Port Speed: %s\n"
+ "Port Force Full Speed Connenct: %s\n"
+ "PHY Low Power Suspend Clock Disable: %s\n"
+ "BmAttributes: %d\n\n",
+ LPM_PTS(tmp_reg),
+ (tmp_reg & LPM_STS) ? 1 : 0,
+ ({
+ char *s;
+ switch (LPM_PSPD(tmp_reg)) {
+ case LPM_SPEED_FULL:
+ s = "Full Speed"; break;
+ case LPM_SPEED_LOW:
+ s = "Low Speed"; break;
+ case LPM_SPEED_HIGH:
+ s = "High Speed"; break;
+ default:
+ s = "Unknown Speed"; break;
+ }
+ s;
+ }),
+ (tmp_reg & LPM_PFSC) ? "Force Full Speed" : "Not Force",
+ (tmp_reg & LPM_PHCD) ? "Disabled" : "Enabled",
+ LPM_BA(tmp_reg));
+ size -= t;
+ next += t;
+
+ tmp_reg = readl(&dev->op_regs->usbmode);
+ t = scnprintf(next, size,
+ "USB Mode Reg:\n"
+ "Controller Mode is : %s\n\n", ({
+ char *s;
+ switch (MODE_CM(tmp_reg)) {
+ case MODE_IDLE:
+ s = "Idle"; break;
+ case MODE_DEVICE:
+ s = "Device Controller"; break;
+ case MODE_HOST:
+ s = "Host Controller"; break;
+ default:
+ s = "None"; break;
+ }
+ s;
+ }));
+ size -= t;
+ next += t;
+
+ tmp_reg = readl(&dev->op_regs->endptsetupstat);
+ t = scnprintf(next, size,
+ "Endpoint Setup Status Reg:\n"
+ "SETUP on ep 0x%04x\n\n",
+ tmp_reg & SETUPSTAT_MASK);
+ size -= t;
+ next += t;
+
+ for (i = 0; i < dev->ep_max / 2; i++) {
+ tmp_reg = readl(&dev->op_regs->endptctrl[i]);
+ t = scnprintf(next, size, "EP Ctrl Reg [%d]: 0x%08x\n",
+ i, tmp_reg);
+ size -= t;
+ next += t;
+ }
+ tmp_reg = readl(&dev->op_regs->endptprime);
+ t = scnprintf(next, size, "EP Prime Reg: 0x%08x\n\n", tmp_reg);
+ size -= t;
+ next += t;
+
+ /* langwell_udc, langwell_ep, langwell_request structure information */
+ ep = &dev->ep[0];
+ t = scnprintf(next, size, "%s MaxPacketSize: 0x%x, ep_num: %d\n",
+ ep->ep.name, ep->ep.maxpacket, ep->ep_num);
+ size -= t;
+ next += t;
+
+ if (list_empty(&ep->queue)) {
+ t = scnprintf(next, size, "its req queue is empty\n\n");
+ size -= t;
+ next += t;
+ } else {
+ list_for_each_entry(req, &ep->queue, queue) {
+ t = scnprintf(next, size,
+ "req %p actual 0x%x length 0x%x buf %p\n",
+ &req->req, req->req.actual,
+ req->req.length, req->req.buf);
+ size -= t;
+ next += t;
+ }
+ }
+ /* other gadget->eplist ep */
+ list_for_each_entry(ep, &dev->gadget.ep_list, ep.ep_list) {
+ if (ep->desc) {
+ t = scnprintf(next, size,
+ "\n%s MaxPacketSize: 0x%x, "
+ "ep_num: %d\n",
+ ep->ep.name, ep->ep.maxpacket,
+ ep->ep_num);
+ size -= t;
+ next += t;
+
+ if (list_empty(&ep->queue)) {
+ t = scnprintf(next, size,
+ "its req queue is empty\n\n");
+ size -= t;
+ next += t;
+ } else {
+ list_for_each_entry(req, &ep->queue, queue) {
+ t = scnprintf(next, size,
+ "req %p actual 0x%x length "
+ "0x%x buf %p\n",
+ &req->req, req->req.actual,
+ req->req.length, req->req.buf);
+ size -= t;
+ next += t;
+ }
+ }
+ }
+ }
+
+ spin_unlock_irqrestore(&dev->lock, flags);
+ return PAGE_SIZE - size;
+}
+static DEVICE_ATTR(langwell_udc, S_IRUGO, show_langwell_udc, NULL);
+
+
+/*-------------------------------------------------------------------------*/
+
+/*
+ * when a driver is successfully registered, it will receive
+ * control requests including set_configuration(), which enables
+ * non-control requests. then usb traffic follows until a
+ * disconnect is reported. then a host may connect again, or
+ * the driver might get unbound.
+ */
+
+int usb_gadget_register_driver(struct usb_gadget_driver *driver)
+{
+ struct langwell_udc *dev = the_controller;
+ unsigned long flags;
+ int retval;
+
+ if (!dev)
+ return -ENODEV;
+
+ DBG(dev, "---> %s()\n", __func__);
+
+ if (dev->driver)
+ return -EBUSY;
+
+ spin_lock_irqsave(&dev->lock, flags);
+
+ /* hook up the driver ... */
+ driver->driver.bus = NULL;
+ dev->driver = driver;
+ dev->gadget.dev.driver = &driver->driver;
+
+ spin_unlock_irqrestore(&dev->lock, flags);
+
+ retval = driver->bind(&dev->gadget);
+ if (retval) {
+ DBG(dev, "bind to driver %s --> %d\n",
+ driver->driver.name, retval);
+ dev->driver = NULL;
+ dev->gadget.dev.driver = NULL;
+ return retval;
+ }
+
+ retval = device_create_file(&dev->pdev->dev, &dev_attr_function);
+ if (retval)
+ goto err_unbind;
+
+ dev->usb_state = USB_STATE_ATTACHED;
+ dev->ep0_state = WAIT_FOR_SETUP;
+ dev->ep0_dir = USB_DIR_OUT;
+
+ /* enable interrupt and set controller to run state */
+ if (dev->got_irq)
+ langwell_udc_start(dev);
+
+ VDBG(dev, "After langwell_udc_start(), print all registers:\n");
+#ifdef VERBOSE
+ print_all_registers(dev);
+#endif
+
+ INFO(dev, "register driver: %s\n", driver->driver.name);
+ VDBG(dev, "<--- %s()\n", __func__);
+ return 0;
+
+err_unbind:
+ driver->unbind(&dev->gadget);
+ dev->gadget.dev.driver = NULL;
+ dev->driver = NULL;
+
+ DBG(dev, "<--- %s()\n", __func__);
+ return retval;
+}
+EXPORT_SYMBOL(usb_gadget_register_driver);
+
+
+/* unregister gadget driver */
+int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
+{
+ struct langwell_udc *dev = the_controller;
+ unsigned long flags;
+
+ if (!dev)
+ return -ENODEV;
+
+ DBG(dev, "---> %s()\n", __func__);
+
+ if (unlikely(!driver || !driver->bind || !driver->unbind))
+ return -EINVAL;
+
+ /* unbind OTG transceiver */
+ if (dev->transceiver)
+ (void)otg_set_peripheral(dev->transceiver, 0);
+
+ /* disable interrupt and set controller to stop state */
+ langwell_udc_stop(dev);
+
+ dev->usb_state = USB_STATE_ATTACHED;
+ dev->ep0_state = WAIT_FOR_SETUP;
+ dev->ep0_dir = USB_DIR_OUT;
+
+ spin_lock_irqsave(&dev->lock, flags);
+
+ /* stop all usb activities */
+ dev->gadget.speed = USB_SPEED_UNKNOWN;
+ stop_activity(dev, driver);
+ spin_unlock_irqrestore(&dev->lock, flags);
+
+ /* unbind gadget driver */
+ driver->unbind(&dev->gadget);
+ dev->gadget.dev.driver = NULL;
+ dev->driver = NULL;
+
+ device_remove_file(&dev->pdev->dev, &dev_attr_function);
+
+ INFO(dev, "unregistered driver '%s'\n", driver->driver.name);
+ DBG(dev, "<--- %s()\n", __func__);
+ return 0;
+}
+EXPORT_SYMBOL(usb_gadget_unregister_driver);
+
+
+/*-------------------------------------------------------------------------*/
+
+/*
+ * setup tripwire is used as a semaphore to ensure that the setup data
+ * payload is extracted from a dQH without being corrupted
+ */
+static void setup_tripwire(struct langwell_udc *dev)
+{
+ u32 usbcmd,
+ endptsetupstat;
+ unsigned long timeout;
+ struct langwell_dqh *dqh;
+
+ VDBG(dev, "---> %s()\n", __func__);
+
+ /* ep0 OUT dQH */
+ dqh = &dev->ep_dqh[EP_DIR_OUT];
+
+ /* Write-Clear endptsetupstat */
+ endptsetupstat = readl(&dev->op_regs->endptsetupstat);
+ writel(endptsetupstat, &dev->op_regs->endptsetupstat);
+
+ /* wait until endptsetupstat is cleared */
+ timeout = jiffies + SETUPSTAT_TIMEOUT;
+ while (readl(&dev->op_regs->endptsetupstat)) {
+ if (time_after(jiffies, timeout)) {
+ ERROR(dev, "setup_tripwire timeout\n");
+ break;
+ }
+ cpu_relax();
+ }
+
+ /* while a hazard exists when setup packet arrives */
+ do {
+ /* set setup tripwire bit */
+ usbcmd = readl(&dev->op_regs->usbcmd);
+ writel(usbcmd | CMD_SUTW, &dev->op_regs->usbcmd);
+
+ /* copy the setup packet to local buffer */
+ memcpy(&dev->local_setup_buff, &dqh->dqh_setup, 8);
+ } while (!(readl(&dev->op_regs->usbcmd) & CMD_SUTW));
+
+ /* Write-Clear setup tripwire bit */
+ usbcmd = readl(&dev->op_regs->usbcmd);
+ writel(usbcmd & ~CMD_SUTW, &dev->op_regs->usbcmd);
+
+ VDBG(dev, "<--- %s()\n", __func__);
+}
+
+
+/* protocol ep0 stall, will automatically be cleared on new transaction */
+static void ep0_stall(struct langwell_udc *dev)
+{
+ u32 endptctrl;
+
+ VDBG(dev, "---> %s()\n", __func__);
+
+ /* set TX and RX to stall */
+ endptctrl = readl(&dev->op_regs->endptctrl[0]);
+ endptctrl |= EPCTRL_TXS | EPCTRL_RXS;
+ writel(endptctrl, &dev->op_regs->endptctrl[0]);
+
+ /* update ep0 state */
+ dev->ep0_state = WAIT_FOR_SETUP;
+ dev->ep0_dir = USB_DIR_OUT;
+
+ VDBG(dev, "<--- %s()\n", __func__);
+}
+
+
+/* PRIME a status phase for ep0 */
+static int prime_status_phase(struct langwell_udc *dev, int dir)
+{
+ struct langwell_request *req;
+ struct langwell_ep *ep;
+ int status = 0;
+
+ VDBG(dev, "---> %s()\n", __func__);
+
+ if (dir == EP_DIR_IN)
+ dev->ep0_dir = USB_DIR_IN;
+ else
+ dev->ep0_dir = USB_DIR_OUT;
+
+ ep = &dev->ep[0];
+ dev->ep0_state = WAIT_FOR_OUT_STATUS;
+
+ req = dev->status_req;
+
+ req->ep = ep;
+ req->req.length = 0;
+ req->req.status = -EINPROGRESS;
+ req->req.actual = 0;
+ req->req.complete = NULL;
+ req->dtd_count = 0;
+
+ if (!req_to_dtd(req))
+ status = queue_dtd(ep, req);
+ else
+ return -ENOMEM;
+
+ if (status)
+ ERROR(dev, "can't queue ep0 status request\n");
+
+ list_add_tail(&req->queue, &ep->queue);
+
+ VDBG(dev, "<--- %s()\n", __func__);
+ return status;
+}
+
+
+/* SET_ADDRESS request routine */
+static void set_address(struct langwell_udc *dev, u16 value,
+ u16 index, u16 length)
+{
+ VDBG(dev, "---> %s()\n", __func__);
+
+ /* save the new address to device struct */
+ dev->dev_addr = (u8) value;
+ VDBG(dev, "dev->dev_addr = %d\n", dev->dev_addr);
+
+ /* update usb state */
+ dev->usb_state = USB_STATE_ADDRESS;
+
+ /* STATUS phase */
+ if (prime_status_phase(dev, EP_DIR_IN))
+ ep0_stall(dev);
+
+ VDBG(dev, "<--- %s()\n", __func__);
+}
+
+
+/* return endpoint by windex */
+static struct langwell_ep *get_ep_by_windex(struct langwell_udc *dev,
+ u16 wIndex)
+{
+ struct langwell_ep *ep;
+ VDBG(dev, "---> %s()\n", __func__);
+
+ if ((wIndex & USB_ENDPOINT_NUMBER_MASK) == 0)
+ return &dev->ep[0];
+
+ list_for_each_entry(ep, &dev->gadget.ep_list, ep.ep_list) {
+ u8 bEndpointAddress;
+ if (!ep->desc)
+ continue;
+
+ bEndpointAddress = ep->desc->bEndpointAddress;
+ if ((wIndex ^ bEndpointAddress) & USB_DIR_IN)
+ continue;
+
+ if ((wIndex & USB_ENDPOINT_NUMBER_MASK)
+ == (bEndpointAddress & USB_ENDPOINT_NUMBER_MASK))
+ return ep;
+ }
+
+ VDBG(dev, "<--- %s()\n", __func__);
+ return NULL;
+}
+
+
+/* return whether endpoint is stalled, 0: not stalled; 1: stalled */
+static int ep_is_stall(struct langwell_ep *ep)
+{
+ struct langwell_udc *dev = ep->dev;
+ u32 endptctrl;
+ int retval;
+
+ VDBG(dev, "---> %s()\n", __func__);
+
+ endptctrl = readl(&dev->op_regs->endptctrl[ep->ep_num]);
+ if (is_in(ep))
+ retval = endptctrl & EPCTRL_TXS ? 1 : 0;
+ else
+ retval = endptctrl & EPCTRL_RXS ? 1 : 0;
+
+ VDBG(dev, "<--- %s()\n", __func__);
+ return retval;
+}
+
+
+/* GET_STATUS request routine */
+static void get_status(struct langwell_udc *dev, u8 request_type, u16 value,
+ u16 index, u16 length)
+{
+ struct langwell_request *req;
+ struct langwell_ep *ep;
+ u16 status_data = 0; /* 16 bits cpu view status data */
+ int status = 0;
+
+ VDBG(dev, "---> %s()\n", __func__);
+
+ ep = &dev->ep[0];
+
+ if ((request_type & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
+ /* get device status */
+ status_data = 1 << USB_DEVICE_SELF_POWERED;
+ status_data |= dev->remote_wakeup << USB_DEVICE_REMOTE_WAKEUP;
+ } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_INTERFACE) {
+ /* get interface status */
+ status_data = 0;
+ } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_ENDPOINT) {
+ /* get endpoint status */
+ struct langwell_ep *epn;
+ epn = get_ep_by_windex(dev, index);
+ /* stall if endpoint doesn't exist */
+ if (!epn)
+ goto stall;
+
+ status_data = ep_is_stall(epn) << USB_ENDPOINT_HALT;
+ }
+
+ dev->ep0_dir = USB_DIR_IN;
+
+ /* borrow the per device status_req */
+ req = dev->status_req;
+
+ /* fill in the reqest structure */
+ *((u16 *) req->req.buf) = cpu_to_le16(status_data);
+ req->ep = ep;
+ req->req.length = 2;
+ req->req.status = -EINPROGRESS;
+ req->req.actual = 0;
+ req->req.complete = NULL;
+ req->dtd_count = 0;
+
+ /* prime the data phase */
+ if (!req_to_dtd(req))
+ status = queue_dtd(ep, req);
+ else /* no mem */
+ goto stall;
+
+ if (status) {
+ ERROR(dev, "response error on GET_STATUS request\n");
+ goto stall;
+ }
+
+ list_add_tail(&req->queue, &ep->queue);
+ dev->ep0_state = DATA_STATE_XMIT;
+
+ VDBG(dev, "<--- %s()\n", __func__);
+ return;
+stall:
+ ep0_stall(dev);
+ VDBG(dev, "<--- %s()\n", __func__);
+}
+
+
+/* setup packet interrupt handler */
+static void handle_setup_packet(struct langwell_udc *dev,
+ struct usb_ctrlrequest *setup)
+{
+ u16 wValue = le16_to_cpu(setup->wValue);
+ u16 wIndex = le16_to_cpu(setup->wIndex);
+ u16 wLength = le16_to_cpu(setup->wLength);
+
+ VDBG(dev, "---> %s()\n", __func__);
+
+ /* ep0 fifo flush */
+ nuke(&dev->ep[0], -ESHUTDOWN);
+
+ DBG(dev, "SETUP %02x.%02x v%04x i%04x l%04x\n",
+ setup->bRequestType, setup->bRequest,
+ wValue, wIndex, wLength);
+
+ /* RNDIS gadget delegate */
+ if ((setup->bRequestType == 0x21) && (setup->bRequest == 0x00)) {
+ /* USB_CDC_SEND_ENCAPSULATED_COMMAND */
+ goto delegate;
+ }
+
+ /* USB_CDC_GET_ENCAPSULATED_RESPONSE */
+ if ((setup->bRequestType == 0xa1) && (setup->bRequest == 0x01)) {
+ /* USB_CDC_GET_ENCAPSULATED_RESPONSE */
+ goto delegate;
+ }
+
+ /* We process some stardard setup requests here */
+ switch (setup->bRequest) {
+ case USB_REQ_GET_STATUS:
+ DBG(dev, "SETUP: USB_REQ_GET_STATUS\n");
+ /* get status, DATA and STATUS phase */
+ if ((setup->bRequestType & (USB_DIR_IN | USB_TYPE_MASK))
+ != (USB_DIR_IN | USB_TYPE_STANDARD))
+ break;
+ get_status(dev, setup->bRequestType, wValue, wIndex, wLength);
+ goto end;
+
+ case USB_REQ_SET_ADDRESS:
+ DBG(dev, "SETUP: USB_REQ_SET_ADDRESS\n");
+ /* STATUS phase */
+ if (setup->bRequestType != (USB_DIR_OUT | USB_TYPE_STANDARD
+ | USB_RECIP_DEVICE))
+ break;
+ set_address(dev, wValue, wIndex, wLength);
+ goto end;
+
+ case USB_REQ_CLEAR_FEATURE:
+ case USB_REQ_SET_FEATURE:
+ /* STATUS phase */
+ {
+ int rc = -EOPNOTSUPP;
+ if (setup->bRequest == USB_REQ_SET_FEATURE)
+ DBG(dev, "SETUP: USB_REQ_SET_FEATURE\n");
+ else if (setup->bRequest == USB_REQ_CLEAR_FEATURE)
+ DBG(dev, "SETUP: USB_REQ_CLEAR_FEATURE\n");
+
+ if ((setup->bRequestType & (USB_RECIP_MASK | USB_TYPE_MASK))
+ == (USB_RECIP_ENDPOINT | USB_TYPE_STANDARD)) {
+ struct langwell_ep *epn;
+ epn = get_ep_by_windex(dev, wIndex);
+ /* stall if endpoint doesn't exist */
+ if (!epn) {
+ ep0_stall(dev);
+ goto end;
+ }
+
+ if (wValue != 0 || wLength != 0
+ || epn->ep_num > dev->ep_max)
+ break;
+
+ spin_unlock(&dev->lock);
+ rc = langwell_ep_set_halt(&epn->ep,
+ (setup->bRequest == USB_REQ_SET_FEATURE)
+ ? 1 : 0);
+ spin_lock(&dev->lock);
+
+ } else if ((setup->bRequestType & (USB_RECIP_MASK
+ | USB_TYPE_MASK)) == (USB_RECIP_DEVICE
+ | USB_TYPE_STANDARD)) {
+ if (!gadget_is_otg(&dev->gadget))
+ break;
+ else if (setup->bRequest == USB_DEVICE_B_HNP_ENABLE) {
+ dev->gadget.b_hnp_enable = 1;
+#ifdef OTG_TRANSCEIVER
+ if (!dev->lotg->otg.default_a)
+ dev->lotg->hsm.b_hnp_enable = 1;
+#endif
+ } else if (setup->bRequest == USB_DEVICE_A_HNP_SUPPORT)
+ dev->gadget.a_hnp_support = 1;
+ else if (setup->bRequest ==
+ USB_DEVICE_A_ALT_HNP_SUPPORT)
+ dev->gadget.a_alt_hnp_support = 1;
+ else
+ break;
+ rc = 0;
+ } else
+ break;
+
+ if (rc == 0) {
+ if (prime_status_phase(dev, EP_DIR_IN))
+ ep0_stall(dev);
+ }
+ goto end;
+ }
+
+ case USB_REQ_GET_DESCRIPTOR:
+ DBG(dev, "SETUP: USB_REQ_GET_DESCRIPTOR\n");
+ goto delegate;
+
+ case USB_REQ_SET_DESCRIPTOR:
+ DBG(dev, "SETUP: USB_REQ_SET_DESCRIPTOR unsupported\n");
+ goto delegate;
+
+ case USB_REQ_GET_CONFIGURATION:
+ DBG(dev, "SETUP: USB_REQ_GET_CONFIGURATION\n");
+ goto delegate;
+
+ case USB_REQ_SET_CONFIGURATION:
+ DBG(dev, "SETUP: USB_REQ_SET_CONFIGURATION\n");
+ goto delegate;
+
+ case USB_REQ_GET_INTERFACE:
+ DBG(dev, "SETUP: USB_REQ_GET_INTERFACE\n");
+ goto delegate;
+
+ case USB_REQ_SET_INTERFACE:
+ DBG(dev, "SETUP: USB_REQ_SET_INTERFACE\n");
+ goto delegate;
+
+ case USB_REQ_SYNCH_FRAME:
+ DBG(dev, "SETUP: USB_REQ_SYNCH_FRAME unsupported\n");
+ goto delegate;
+
+ default:
+ /* delegate USB standard requests to the gadget driver */
+ goto delegate;
+delegate:
+ /* USB requests handled by gadget */
+ if (wLength) {
+ /* DATA phase from gadget, STATUS phase from udc */
+ dev->ep0_dir = (setup->bRequestType & USB_DIR_IN)
+ ? USB_DIR_IN : USB_DIR_OUT;
+ VDBG(dev, "dev->ep0_dir = 0x%x, wLength = %d\n",
+ dev->ep0_dir, wLength);
+ spin_unlock(&dev->lock);
+ if (dev->driver->setup(&dev->gadget,
+ &dev->local_setup_buff) < 0)
+ ep0_stall(dev);
+ spin_lock(&dev->lock);
+ dev->ep0_state = (setup->bRequestType & USB_DIR_IN)
+ ? DATA_STATE_XMIT : DATA_STATE_RECV;
+ } else {
+ /* no DATA phase, IN STATUS phase from gadget */
+ dev->ep0_dir = USB_DIR_IN;
+ VDBG(dev, "dev->ep0_dir = 0x%x, wLength = %d\n",
+ dev->ep0_dir, wLength);
+ spin_unlock(&dev->lock);
+ if (dev->driver->setup(&dev->gadget,
+ &dev->local_setup_buff) < 0)
+ ep0_stall(dev);
+ spin_lock(&dev->lock);
+ dev->ep0_state = WAIT_FOR_OUT_STATUS;
+ }
+ break;
+ }
+end:
+ VDBG(dev, "<--- %s()\n", __func__);
+ return;
+}
+
+
+/* transfer completion, process endpoint request and free the completed dTDs
+ * for this request
+ */
+static int process_ep_req(struct langwell_udc *dev, int index,
+ struct langwell_request *curr_req)
+{
+ struct langwell_dtd *curr_dtd;
+ struct langwell_dqh *curr_dqh;
+ int td_complete, actual, remaining_length;
+ int i, dir;
+ u8 dtd_status = 0;
+ int retval = 0;
+
+ curr_dqh = &dev->ep_dqh[index];
+ dir = index % 2;
+
+ curr_dtd = curr_req->head;
+ td_complete = 0;
+ actual = curr_req->req.length;
+
+ VDBG(dev, "---> %s()\n", __func__);
+
+ for (i = 0; i < curr_req->dtd_count; i++) {
+ remaining_length = le16_to_cpu(curr_dtd->dtd_total);
+ actual -= remaining_length;
+
+ /* command execution states by dTD */
+ dtd_status = curr_dtd->dtd_status;
+
+ if (!dtd_status) {
+ /* transfers completed successfully */
+ if (!remaining_length) {
+ td_complete++;
+ VDBG(dev, "dTD transmitted successfully\n");
+ } else {
+ if (dir) {
+ VDBG(dev, "TX dTD remains data\n");
+ retval = -EPROTO;
+ break;
+
+ } else {
+ td_complete++;
+ break;
+ }
+ }
+ } else {
+ /* transfers completed with errors */
+ if (dtd_status & DTD_STS_ACTIVE) {
+ DBG(dev, "request not completed\n");
+ retval = 1;
+ return retval;
+ } else if (dtd_status & DTD_STS_HALTED) {
+ ERROR(dev, "dTD error %08x dQH[%d]\n",
+ dtd_status, index);
+ /* clear the errors and halt condition */
+ curr_dqh->dtd_status = 0;
+ retval = -EPIPE;
+ break;
+ } else if (dtd_status & DTD_STS_DBE) {
+ DBG(dev, "data buffer (overflow) error\n");
+ retval = -EPROTO;
+ break;
+ } else if (dtd_status & DTD_STS_TRE) {
+ DBG(dev, "transaction(ISO) error\n");
+ retval = -EILSEQ;
+ break;
+ } else
+ ERROR(dev, "unknown error (0x%x)!\n",
+ dtd_status);
+ }
+
+ if (i != curr_req->dtd_count - 1)
+ curr_dtd = (struct langwell_dtd *)
+ curr_dtd->next_dtd_virt;
+ }
+
+ if (retval)
+ return retval;
+
+ curr_req->req.actual = actual;
+
+ VDBG(dev, "<--- %s()\n", __func__);
+ return 0;
+}
+
+
+/* complete DATA or STATUS phase of ep0 prime status phase if needed */
+static void ep0_req_complete(struct langwell_udc *dev,
+ struct langwell_ep *ep0, struct langwell_request *req)
+{
+ u32 new_addr;
+ VDBG(dev, "---> %s()\n", __func__);
+
+ if (dev->usb_state == USB_STATE_ADDRESS) {
+ /* set the new address */
+ new_addr = (u32)dev->dev_addr;
+ writel(new_addr << USBADR_SHIFT, &dev->op_regs->deviceaddr);
+
+ new_addr = USBADR(readl(&dev->op_regs->deviceaddr));
+ VDBG(dev, "new_addr = %d\n", new_addr);
+ }
+
+ done(ep0, req, 0);
+
+ switch (dev->ep0_state) {
+ case DATA_STATE_XMIT:
+ /* receive status phase */
+ if (prime_status_phase(dev, EP_DIR_OUT))
+ ep0_stall(dev);
+ break;
+ case DATA_STATE_RECV:
+ /* send status phase */
+ if (prime_status_phase(dev, EP_DIR_IN))
+ ep0_stall(dev);
+ break;
+ case WAIT_FOR_OUT_STATUS:
+ dev->ep0_state = WAIT_FOR_SETUP;
+ break;
+ case WAIT_FOR_SETUP:
+ ERROR(dev, "unexpect ep0 packets\n");
+ break;
+ default:
+ ep0_stall(dev);
+ break;
+ }
+
+ VDBG(dev, "<--- %s()\n", __func__);
+}
+
+
+/* USB transfer completion interrupt */
+static void handle_trans_complete(struct langwell_udc *dev)
+{
+ u32 complete_bits;
+ int i, ep_num, dir, bit_mask, status;
+ struct langwell_ep *epn;
+ struct langwell_request *curr_req, *temp_req;
+
+ VDBG(dev, "---> %s()\n", __func__);
+
+ complete_bits = readl(&dev->op_regs->endptcomplete);
+ VDBG(dev, "endptcomplete register: 0x%08x\n", complete_bits);
+
+ /* Write-Clear the bits in endptcomplete register */
+ writel(complete_bits, &dev->op_regs->endptcomplete);
+
+ if (!complete_bits) {
+ DBG(dev, "complete_bits = 0\n");
+ goto done;
+ }
+
+ for (i = 0; i < dev->ep_max; i++) {
+ ep_num = i / 2;
+ dir = i % 2;
+
+ bit_mask = 1 << (ep_num + 16 * dir);
+
+ if (!(complete_bits & bit_mask))
+ continue;
+
+ /* ep0 */
+ if (i == 1)
+ epn = &dev->ep[0];
+ else
+ epn = &dev->ep[i];
+
+ if (epn->name == NULL) {
+ WARNING(dev, "invalid endpoint\n");
+ continue;
+ }
+
+ if (i < 2)
+ /* ep0 in and out */
+ DBG(dev, "%s-%s transfer completed\n",
+ epn->name,
+ is_in(epn) ? "in" : "out");
+ else
+ DBG(dev, "%s transfer completed\n", epn->name);
+
+ /* process the req queue until an uncomplete request */
+ list_for_each_entry_safe(curr_req, temp_req,
+ &epn->queue, queue) {
+ status = process_ep_req(dev, i, curr_req);
+ VDBG(dev, "%s req status: %d\n", epn->name, status);
+
+ if (status)
+ break;
+
+ /* write back status to req */
+ curr_req->req.status = status;
+
+ /* ep0 request completion */
+ if (ep_num == 0) {
+ ep0_req_complete(dev, epn, curr_req);
+ break;
+ } else {
+ done(epn, curr_req, status);
+ }
+ }
+ }
+done:
+ VDBG(dev, "<--- %s()\n", __func__);
+ return;
+}
+
+
+/* port change detect interrupt handler */
+static void handle_port_change(struct langwell_udc *dev)
+{
+ u32 portsc1, devlc;
+ u32 speed;
+
+ VDBG(dev, "---> %s()\n", __func__);
+
+ if (dev->bus_reset)
+ dev->bus_reset = 0;
+
+ portsc1 = readl(&dev->op_regs->portsc1);
+ devlc = readl(&dev->op_regs->devlc);
+ VDBG(dev, "portsc1 = 0x%08x, devlc = 0x%08x\n",
+ portsc1, devlc);
+
+ /* bus reset is finished */
+ if (!(portsc1 & PORTS_PR)) {
+ /* get the speed */
+ speed = LPM_PSPD(devlc);
+ switch (speed) {
+ case LPM_SPEED_HIGH:
+ dev->gadget.speed = USB_SPEED_HIGH;
+ break;
+ case LPM_SPEED_FULL:
+ dev->gadget.speed = USB_SPEED_FULL;
+ break;
+ case LPM_SPEED_LOW:
+ dev->gadget.speed = USB_SPEED_LOW;
+ break;
+ default:
+ dev->gadget.speed = USB_SPEED_UNKNOWN;
+ break;
+ }
+ VDBG(dev, "speed = %d, dev->gadget.speed = %d\n",
+ speed, dev->gadget.speed);
+ }
+
+ /* LPM L0 to L1 */
+ if (dev->lpm && dev->lpm_state == LPM_L0)
+ if (portsc1 & PORTS_SUSP && portsc1 & PORTS_SLP) {
+ INFO(dev, "LPM L0 to L1\n");
+ dev->lpm_state = LPM_L1;
+ }
+
+ /* LPM L1 to L0, force resume or remote wakeup finished */
+ if (dev->lpm && dev->lpm_state == LPM_L1)
+ if (!(portsc1 & PORTS_SUSP)) {
+ if (portsc1 & PORTS_SLP)
+ INFO(dev, "LPM L1 to L0, force resume\n");
+ else
+ INFO(dev, "LPM L1 to L0, remote wakeup\n");
+
+ dev->lpm_state = LPM_L0;
+ }
+
+ /* update USB state */
+ if (!dev->resume_state)
+ dev->usb_state = USB_STATE_DEFAULT;
+
+ VDBG(dev, "<--- %s()\n", __func__);
+}
+
+
+/* USB reset interrupt handler */
+static void handle_usb_reset(struct langwell_udc *dev)
+{
+ u32 deviceaddr,
+ endptsetupstat,
+ endptcomplete;
+ unsigned long timeout;
+
+ VDBG(dev, "---> %s()\n", __func__);
+
+ /* Write-Clear the device address */
+ deviceaddr = readl(&dev->op_regs->deviceaddr);
+ writel(deviceaddr & ~USBADR_MASK, &dev->op_regs->deviceaddr);
+
+ dev->dev_addr = 0;
+
+ /* clear usb state */
+ dev->resume_state = 0;
+
+ /* LPM L1 to L0, reset */
+ if (dev->lpm)
+ dev->lpm_state = LPM_L0;
+
+ dev->ep0_dir = USB_DIR_OUT;
+ dev->ep0_state = WAIT_FOR_SETUP;
+ dev->remote_wakeup = 0; /* default to 0 on reset */
+ dev->gadget.b_hnp_enable = 0;
+ dev->gadget.a_hnp_support = 0;
+ dev->gadget.a_alt_hnp_support = 0;
+
+ /* Write-Clear all the setup token semaphores */
+ endptsetupstat = readl(&dev->op_regs->endptsetupstat);
+ writel(endptsetupstat, &dev->op_regs->endptsetupstat);
+
+ /* Write-Clear all the endpoint complete status bits */
+ endptcomplete = readl(&dev->op_regs->endptcomplete);
+ writel(endptcomplete, &dev->op_regs->endptcomplete);
+
+ /* wait until all endptprime bits cleared */
+ timeout = jiffies + PRIME_TIMEOUT;
+ while (readl(&dev->op_regs->endptprime)) {
+ if (time_after(jiffies, timeout)) {
+ ERROR(dev, "USB reset timeout\n");
+ break;
+ }
+ cpu_relax();
+ }
+
+ /* write 1s to endptflush register to clear any primed buffers */
+ writel((u32) ~0, &dev->op_regs->endptflush);
+
+ if (readl(&dev->op_regs->portsc1) & PORTS_PR) {
+ VDBG(dev, "USB bus reset\n");
+ /* bus is reseting */
+ dev->bus_reset = 1;
+
+ /* reset all the queues, stop all USB activities */
+ stop_activity(dev, dev->driver);
+ dev->usb_state = USB_STATE_DEFAULT;
+ } else {
+ VDBG(dev, "device controller reset\n");
+ /* controller reset */
+ langwell_udc_reset(dev);
+
+ /* reset all the queues, stop all USB activities */
+ stop_activity(dev, dev->driver);
+
+ /* reset ep0 dQH and endptctrl */
+ ep0_reset(dev);
+
+ /* enable interrupt and set controller to run state */
+ langwell_udc_start(dev);
+
+ dev->usb_state = USB_STATE_ATTACHED;
+ }
+
+#ifdef OTG_TRANSCEIVER
+ /* refer to USB OTG 6.6.2.3 b_hnp_en is cleared */
+ if (!dev->lotg->otg.default_a)
+ dev->lotg->hsm.b_hnp_enable = 0;
+#endif
+
+ VDBG(dev, "<--- %s()\n", __func__);
+}
+
+
+/* USB bus suspend/resume interrupt */
+static void handle_bus_suspend(struct langwell_udc *dev)
+{
+ u32 devlc;
+ DBG(dev, "---> %s()\n", __func__);
+
+ dev->resume_state = dev->usb_state;
+ dev->usb_state = USB_STATE_SUSPENDED;
+
+#ifdef OTG_TRANSCEIVER
+ if (dev->lotg->otg.default_a) {
+ if (dev->lotg->hsm.b_bus_suspend_vld == 1) {
+ dev->lotg->hsm.b_bus_suspend = 1;
+ /* notify transceiver the state changes */
+ if (spin_trylock(&dev->lotg->wq_lock)) {
+ langwell_update_transceiver();
+ spin_unlock(&dev->lotg->wq_lock);
+ }
+ }
+ dev->lotg->hsm.b_bus_suspend_vld++;
+ } else {
+ if (!dev->lotg->hsm.a_bus_suspend) {
+ dev->lotg->hsm.a_bus_suspend = 1;
+ /* notify transceiver the state changes */
+ if (spin_trylock(&dev->lotg->wq_lock)) {
+ langwell_update_transceiver();
+ spin_unlock(&dev->lotg->wq_lock);
+ }
+ }
+ }
+#endif
+
+ /* report suspend to the driver */
+ if (dev->driver) {
+ if (dev->driver->suspend) {
+ spin_unlock(&dev->lock);
+ dev->driver->suspend(&dev->gadget);
+ spin_lock(&dev->lock);
+ DBG(dev, "suspend %s\n", dev->driver->driver.name);
+ }
+ }
+
+ /* enter PHY low power suspend */
+ devlc = readl(&dev->op_regs->devlc);
+ VDBG(dev, "devlc = 0x%08x\n", devlc);
+ devlc |= LPM_PHCD;
+ writel(devlc, &dev->op_regs->devlc);
+
+ DBG(dev, "<--- %s()\n", __func__);
+}
+
+
+static void handle_bus_resume(struct langwell_udc *dev)
+{
+ u32 devlc;
+ DBG(dev, "---> %s()\n", __func__);
+
+ dev->usb_state = dev->resume_state;
+ dev->resume_state = 0;
+
+ /* exit PHY low power suspend */
+ devlc = readl(&dev->op_regs->devlc);
+ VDBG(dev, "devlc = 0x%08x\n", devlc);
+ devlc &= ~LPM_PHCD;
+ writel(devlc, &dev->op_regs->devlc);
+
+#ifdef OTG_TRANSCEIVER
+ if (dev->lotg->otg.default_a == 0)
+ dev->lotg->hsm.a_bus_suspend = 0;
+#endif
+
+ /* report resume to the driver */
+ if (dev->driver) {
+ if (dev->driver->resume) {
+ spin_unlock(&dev->lock);
+ dev->driver->resume(&dev->gadget);
+ spin_lock(&dev->lock);
+ DBG(dev, "resume %s\n", dev->driver->driver.name);
+ }
+ }
+
+ DBG(dev, "<--- %s()\n", __func__);
+}
+
+
+/* USB device controller interrupt handler */
+static irqreturn_t langwell_irq(int irq, void *_dev)
+{
+ struct langwell_udc *dev = _dev;
+ u32 usbsts,
+ usbintr,
+ irq_sts,
+ portsc1;
+
+ VDBG(dev, "---> %s()\n", __func__);
+
+ if (dev->stopped) {
+ VDBG(dev, "handle IRQ_NONE\n");
+ VDBG(dev, "<--- %s()\n", __func__);
+ return IRQ_NONE;
+ }
+
+ spin_lock(&dev->lock);
+
+ /* USB status */
+ usbsts = readl(&dev->op_regs->usbsts);
+
+ /* USB interrupt enable */
+ usbintr = readl(&dev->op_regs->usbintr);
+
+ irq_sts = usbsts & usbintr;
+ VDBG(dev, "usbsts = 0x%08x, usbintr = 0x%08x, irq_sts = 0x%08x\n",
+ usbsts, usbintr, irq_sts);
+
+ if (!irq_sts) {
+ VDBG(dev, "handle IRQ_NONE\n");
+ VDBG(dev, "<--- %s()\n", __func__);
+ spin_unlock(&dev->lock);
+ return IRQ_NONE;
+ }
+
+ /* Write-Clear interrupt status bits */
+ writel(irq_sts, &dev->op_regs->usbsts);
+
+ /* resume from suspend */
+ portsc1 = readl(&dev->op_regs->portsc1);
+ if (dev->usb_state == USB_STATE_SUSPENDED)
+ if (!(portsc1 & PORTS_SUSP))
+ handle_bus_resume(dev);
+
+ /* USB interrupt */
+ if (irq_sts & STS_UI) {
+ VDBG(dev, "USB interrupt\n");
+
+ /* setup packet received from ep0 */
+ if (readl(&dev->op_regs->endptsetupstat)
+ & EP0SETUPSTAT_MASK) {
+ VDBG(dev, "USB SETUP packet received interrupt\n");
+ /* setup tripwire semaphone */
+ setup_tripwire(dev);
+ handle_setup_packet(dev, &dev->local_setup_buff);
+ }
+
+ /* USB transfer completion */
+ if (readl(&dev->op_regs->endptcomplete)) {
+ VDBG(dev, "USB transfer completion interrupt\n");
+ handle_trans_complete(dev);
+ }
+ }
+
+ /* SOF received interrupt (for ISO transfer) */
+ if (irq_sts & STS_SRI) {
+ /* FIXME */
+ /* VDBG(dev, "SOF received interrupt\n"); */
+ }
+
+ /* port change detect interrupt */
+ if (irq_sts & STS_PCI) {
+ VDBG(dev, "port change detect interrupt\n");
+ handle_port_change(dev);
+ }
+
+ /* suspend interrrupt */
+ if (irq_sts & STS_SLI) {
+ VDBG(dev, "suspend interrupt\n");
+ handle_bus_suspend(dev);
+ }
+
+ /* USB reset interrupt */
+ if (irq_sts & STS_URI) {
+ VDBG(dev, "USB reset interrupt\n");
+ handle_usb_reset(dev);
+ }
+
+ /* USB error or system error interrupt */
+ if (irq_sts & (STS_UEI | STS_SEI)) {
+ /* FIXME */
+ WARNING(dev, "error IRQ, irq_sts: %x\n", irq_sts);
+ }
+
+ spin_unlock(&dev->lock);
+
+ VDBG(dev, "<--- %s()\n", __func__);
+ return IRQ_HANDLED;
+}
+
+
+/*-------------------------------------------------------------------------*/
+
+/* release device structure */
+static void gadget_release(struct device *_dev)
+{
+ struct langwell_udc *dev = the_controller;
+
+ DBG(dev, "---> %s()\n", __func__);
+
+ complete(dev->done);
+
+ DBG(dev, "<--- %s()\n", __func__);
+ kfree(dev);
+}
+
+
+/* tear down the binding between this driver and the pci device */
+static void langwell_udc_remove(struct pci_dev *pdev)
+{
+ struct langwell_udc *dev = the_controller;
+
+ DECLARE_COMPLETION(done);
+
+ BUG_ON(dev->driver);
+ DBG(dev, "---> %s()\n", __func__);
+
+ dev->done = &done;
+
+ /* free memory allocated in probe */
+ if (dev->dtd_pool)
+ dma_pool_destroy(dev->dtd_pool);
+
+ if (dev->status_req) {
+ kfree(dev->status_req->req.buf);
+ kfree(dev->status_req);
+ }
+
+ if (dev->ep_dqh)
+ dma_free_coherent(&pdev->dev, dev->ep_dqh_size,
+ dev->ep_dqh, dev->ep_dqh_dma);
+
+ kfree(dev->ep);
+
+ /* diable IRQ handler */
+ if (dev->got_irq)
+ free_irq(pdev->irq, dev);
+
+#ifndef OTG_TRANSCEIVER
+ if (dev->cap_regs)
+ iounmap(dev->cap_regs);
+
+ if (dev->region)
+ release_mem_region(pci_resource_start(pdev, 0),
+ pci_resource_len(pdev, 0));
+
+ if (dev->enabled)
+ pci_disable_device(pdev);
+#else
+ if (dev->transceiver) {
+ otg_put_transceiver(dev->transceiver);
+ dev->transceiver = NULL;
+ dev->lotg = NULL;
+ }
+#endif
+
+ dev->cap_regs = NULL;
+
+ INFO(dev, "unbind\n");
+ DBG(dev, "<--- %s()\n", __func__);
+
+ device_unregister(&dev->gadget.dev);
+ device_remove_file(&pdev->dev, &dev_attr_langwell_udc);
+
+#ifndef OTG_TRANSCEIVER
+ pci_set_drvdata(pdev, NULL);
+#endif
+
+ /* free dev, wait for the release() finished */
+ wait_for_completion(&done);
+
+ the_controller = NULL;
+}
+
+
+/*
+ * wrap this driver around the specified device, but
+ * don't respond over USB until a gadget driver binds to us.
+ */
+static int langwell_udc_probe(struct pci_dev *pdev,
+ const struct pci_device_id *id)
+{
+ struct langwell_udc *dev;
+#ifndef OTG_TRANSCEIVER
+ unsigned long resource, len;
+#endif
+ void __iomem *base = NULL;
+ size_t size;
+ int retval;
+
+ if (the_controller) {
+ dev_warn(&pdev->dev, "ignoring\n");
+ return -EBUSY;
+ }
+
+ /* alloc, and start init */
+ dev = kzalloc(sizeof *dev, GFP_KERNEL);
+ if (dev == NULL) {
+ retval = -ENOMEM;
+ goto error;
+ }
+
+ /* initialize device spinlock */
+ spin_lock_init(&dev->lock);
+
+ dev->pdev = pdev;
+ DBG(dev, "---> %s()\n", __func__);
+
+#ifdef OTG_TRANSCEIVER
+ /* PCI device is already enabled by otg_transceiver driver */
+ dev->enabled = 1;
+
+ /* mem region and register base */
+ dev->region = 1;
+ dev->transceiver = otg_get_transceiver();
+ dev->lotg = otg_to_langwell(dev->transceiver);
+ base = dev->lotg->regs;
+#else
+ pci_set_drvdata(pdev, dev);
+
+ /* now all the pci goodies ... */
+ if (pci_enable_device(pdev) < 0) {
+ retval = -ENODEV;
+ goto error;
+ }
+ dev->enabled = 1;
+
+ /* control register: BAR 0 */
+ resource = pci_resource_start(pdev, 0);
+ len = pci_resource_len(pdev, 0);
+ if (!request_mem_region(resource, len, driver_name)) {
+ ERROR(dev, "controller already in use\n");
+ retval = -EBUSY;
+ goto error;
+ }
+ dev->region = 1;
+
+ base = ioremap_nocache(resource, len);
+#endif
+ if (base == NULL) {
+ ERROR(dev, "can't map memory\n");
+ retval = -EFAULT;
+ goto error;
+ }
+
+ dev->cap_regs = (struct langwell_cap_regs __iomem *) base;
+ VDBG(dev, "dev->cap_regs: %p\n", dev->cap_regs);
+ dev->op_regs = (struct langwell_op_regs __iomem *)
+ (base + OP_REG_OFFSET);
+ VDBG(dev, "dev->op_regs: %p\n", dev->op_regs);
+
+ /* irq setup after old hardware is cleaned up */
+ if (!pdev->irq) {
+ ERROR(dev, "No IRQ. Check PCI setup!\n");
+ retval = -ENODEV;
+ goto error;
+ }
+
+#ifndef OTG_TRANSCEIVER
+ INFO(dev, "irq %d, io mem: 0x%08lx, len: 0x%08lx, pci mem 0x%p\n",
+ pdev->irq, resource, len, base);
+ /* enables bus-mastering for device dev */
+ pci_set_master(pdev);
+
+ if (request_irq(pdev->irq, langwell_irq, IRQF_SHARED,
+ driver_name, dev) != 0) {
+ ERROR(dev, "request interrupt %d failed\n", pdev->irq);
+ retval = -EBUSY;
+ goto error;
+ }
+ dev->got_irq = 1;
+#endif
+
+ /* set stopped bit */
+ dev->stopped = 1;
+
+ /* capabilities and endpoint number */
+ dev->lpm = (readl(&dev->cap_regs->hccparams) & HCC_LEN) ? 1 : 0;
+ dev->dciversion = readw(&dev->cap_regs->dciversion);
+ dev->devcap = (readl(&dev->cap_regs->dccparams) & DEVCAP) ? 1 : 0;
+ VDBG(dev, "dev->lpm: %d\n", dev->lpm);
+ VDBG(dev, "dev->dciversion: 0x%04x\n", dev->dciversion);
+ VDBG(dev, "dccparams: 0x%08x\n", readl(&dev->cap_regs->dccparams));
+ VDBG(dev, "dev->devcap: %d\n", dev->devcap);
+ if (!dev->devcap) {
+ ERROR(dev, "can't support device mode\n");
+ retval = -ENODEV;
+ goto error;
+ }
+
+ /* a pair of endpoints (out/in) for each address */
+ dev->ep_max = DEN(readl(&dev->cap_regs->dccparams)) * 2;
+ VDBG(dev, "dev->ep_max: %d\n", dev->ep_max);
+
+ /* allocate endpoints memory */
+ dev->ep = kzalloc(sizeof(struct langwell_ep) * dev->ep_max,
+ GFP_KERNEL);
+ if (!dev->ep) {
+ ERROR(dev, "allocate endpoints memory failed\n");
+ retval = -ENOMEM;
+ goto error;
+ }
+
+ /* allocate device dQH memory */
+ size = dev->ep_max * sizeof(struct langwell_dqh);
+ VDBG(dev, "orig size = %d\n", size);
+ if (size < DQH_ALIGNMENT)
+ size = DQH_ALIGNMENT;
+ else if ((size % DQH_ALIGNMENT) != 0) {
+ size += DQH_ALIGNMENT + 1;
+ size &= ~(DQH_ALIGNMENT - 1);
+ }
+ dev->ep_dqh = dma_alloc_coherent(&pdev->dev, size,
+ &dev->ep_dqh_dma, GFP_KERNEL);
+ if (!dev->ep_dqh) {
+ ERROR(dev, "allocate dQH memory failed\n");
+ retval = -ENOMEM;
+ goto error;
+ }
+ dev->ep_dqh_size = size;
+ VDBG(dev, "ep_dqh_size = %d\n", dev->ep_dqh_size);
+
+ /* initialize ep0 status request structure */
+ dev->status_req = kzalloc(sizeof(struct langwell_request), GFP_KERNEL);
+ if (!dev->status_req) {
+ ERROR(dev, "allocate status_req memory failed\n");
+ retval = -ENOMEM;
+ goto error;
+ }
+ INIT_LIST_HEAD(&dev->status_req->queue);
+
+ /* allocate a small amount of memory to get valid address */
+ dev->status_req->req.buf = kmalloc(8, GFP_KERNEL);
+ dev->status_req->req.dma = virt_to_phys(dev->status_req->req.buf);
+
+ dev->resume_state = USB_STATE_NOTATTACHED;
+ dev->usb_state = USB_STATE_POWERED;
+ dev->ep0_dir = USB_DIR_OUT;
+ dev->remote_wakeup = 0; /* default to 0 on reset */
+
+#ifndef OTG_TRANSCEIVER
+ /* reset device controller */
+ langwell_udc_reset(dev);
+#endif
+
+ /* initialize gadget structure */
+ dev->gadget.ops = &langwell_ops; /* usb_gadget_ops */
+ dev->gadget.ep0 = &dev->ep[0].ep; /* gadget ep0 */
+ INIT_LIST_HEAD(&dev->gadget.ep_list); /* ep_list */
+ dev->gadget.speed = USB_SPEED_UNKNOWN; /* speed */
+ dev->gadget.is_dualspeed = 1; /* support dual speed */
+#ifdef OTG_TRANSCEIVER
+ dev->gadget.is_otg = 1; /* support otg mode */
+#endif
+
+ /* the "gadget" abstracts/virtualizes the controller */
+ dev_set_name(&dev->gadget.dev, "gadget");
+ dev->gadget.dev.parent = &pdev->dev;
+ dev->gadget.dev.dma_mask = pdev->dev.dma_mask;
+ dev->gadget.dev.release = gadget_release;
+ dev->gadget.name = driver_name; /* gadget name */
+
+ /* controller endpoints reinit */
+ eps_reinit(dev);
+
+#ifndef OTG_TRANSCEIVER
+ /* reset ep0 dQH and endptctrl */
+ ep0_reset(dev);
+#endif
+
+ /* create dTD dma_pool resource */
+ dev->dtd_pool = dma_pool_create("langwell_dtd",
+ &dev->pdev->dev,
+ sizeof(struct langwell_dtd),
+ DTD_ALIGNMENT,
+ DMA_BOUNDARY);
+
+ if (!dev->dtd_pool) {
+ retval = -ENOMEM;
+ goto error;
+ }
+
+ /* done */
+ INFO(dev, "%s\n", driver_desc);
+ INFO(dev, "irq %d, pci mem %p\n", pdev->irq, base);
+ INFO(dev, "Driver version: " DRIVER_VERSION "\n");
+ INFO(dev, "Support (max) %d endpoints\n", dev->ep_max);
+ INFO(dev, "Device interface version: 0x%04x\n", dev->dciversion);
+ INFO(dev, "Controller mode: %s\n", dev->devcap ? "Device" : "Host");
+ INFO(dev, "Support USB LPM: %s\n", dev->lpm ? "Yes" : "No");
+
+ VDBG(dev, "After langwell_udc_probe(), print all registers:\n");
+#ifdef VERBOSE
+ print_all_registers(dev);
+#endif
+
+ the_controller = dev;
+
+ retval = device_register(&dev->gadget.dev);
+ if (retval)
+ goto error;
+
+ retval = device_create_file(&pdev->dev, &dev_attr_langwell_udc);
+ if (retval)
+ goto error;
+
+ VDBG(dev, "<--- %s()\n", __func__);
+ return 0;
+
+error:
+ if (dev) {
+ DBG(dev, "<--- %s()\n", __func__);
+ langwell_udc_remove(pdev);
+ }
+
+ return retval;
+}
+
+
+/* device controller suspend */
+static int langwell_udc_suspend(struct pci_dev *pdev, pm_message_t state)
+{
+ struct langwell_udc *dev = the_controller;
+ u32 devlc;
+
+ DBG(dev, "---> %s()\n", __func__);
+
+ /* disable interrupt and set controller to stop state */
+ langwell_udc_stop(dev);
+
+ /* diable IRQ handler */
+ if (dev->got_irq)
+ free_irq(pdev->irq, dev);
+ dev->got_irq = 0;
+
+
+ /* save PCI state */
+ pci_save_state(pdev);
+
+ /* set device power state */
+ pci_set_power_state(pdev, PCI_D3hot);
+
+ /* enter PHY low power suspend */
+ devlc = readl(&dev->op_regs->devlc);
+ VDBG(dev, "devlc = 0x%08x\n", devlc);
+ devlc |= LPM_PHCD;
+ writel(devlc, &dev->op_regs->devlc);
+
+ DBG(dev, "<--- %s()\n", __func__);
+ return 0;
+}
+
+
+/* device controller resume */
+static int langwell_udc_resume(struct pci_dev *pdev)
+{
+ struct langwell_udc *dev = the_controller;
+ u32 devlc;
+
+ DBG(dev, "---> %s()\n", __func__);
+
+ /* exit PHY low power suspend */
+ devlc = readl(&dev->op_regs->devlc);
+ VDBG(dev, "devlc = 0x%08x\n", devlc);
+ devlc &= ~LPM_PHCD;
+ writel(devlc, &dev->op_regs->devlc);
+
+ /* set device D0 power state */
+ pci_set_power_state(pdev, PCI_D0);
+
+ /* restore PCI state */
+ pci_restore_state(pdev);
+
+ /* enable IRQ handler */
+ if (request_irq(pdev->irq, langwell_irq, IRQF_SHARED, driver_name, dev)
+ != 0) {
+ ERROR(dev, "request interrupt %d failed\n", pdev->irq);
+ return -1;
+ }
+ dev->got_irq = 1;
+
+ /* reset and start controller to run state */
+ if (dev->stopped) {
+ /* reset device controller */
+ langwell_udc_reset(dev);
+
+ /* reset ep0 dQH and endptctrl */
+ ep0_reset(dev);
+
+ /* start device if gadget is loaded */
+ if (dev->driver)
+ langwell_udc_start(dev);
+ }
+
+ /* reset USB status */
+ dev->usb_state = USB_STATE_ATTACHED;
+ dev->ep0_state = WAIT_FOR_SETUP;
+ dev->ep0_dir = USB_DIR_OUT;
+
+ DBG(dev, "<--- %s()\n", __func__);
+ return 0;
+}
+
+
+/* pci driver shutdown */
+static void langwell_udc_shutdown(struct pci_dev *pdev)
+{
+ struct langwell_udc *dev = the_controller;
+ u32 usbmode;
+
+ DBG(dev, "---> %s()\n", __func__);
+
+ /* reset controller mode to IDLE */
+ usbmode = readl(&dev->op_regs->usbmode);
+ DBG(dev, "usbmode = 0x%08x\n", usbmode);
+ usbmode &= (~3 | MODE_IDLE);
+ writel(usbmode, &dev->op_regs->usbmode);
+
+ DBG(dev, "<--- %s()\n", __func__);
+}
+
+/*-------------------------------------------------------------------------*/
+
+static const struct pci_device_id pci_ids[] = { {
+ .class = ((PCI_CLASS_SERIAL_USB << 8) | 0xfe),
+ .class_mask = ~0,
+ .vendor = 0x8086,
+ .device = 0x0811,
+ .subvendor = PCI_ANY_ID,
+ .subdevice = PCI_ANY_ID,
+}, { /* end: all zeroes */ }
+};
+
+
+MODULE_DEVICE_TABLE(pci, pci_ids);
+
+
+static struct pci_driver langwell_pci_driver = {
+ .name = (char *) driver_name,
+ .id_table = pci_ids,
+
+ .probe = langwell_udc_probe,
+ .remove = langwell_udc_remove,
+
+ /* device controller suspend/resume */
+ .suspend = langwell_udc_suspend,
+ .resume = langwell_udc_resume,
+
+ .shutdown = langwell_udc_shutdown,
+};
+
+
+MODULE_DESCRIPTION(DRIVER_DESC);
+MODULE_AUTHOR("Xiaochen Shen <xiaochen.shen@intel.com>");
+MODULE_VERSION(DRIVER_VERSION);
+MODULE_LICENSE("GPL");
+
+
+static int __init init(void)
+{
+#ifdef OTG_TRANSCEIVER
+ return langwell_register_peripheral(&langwell_pci_driver);
+#else
+ return pci_register_driver(&langwell_pci_driver);
+#endif
+}
+module_init(init);
+
+
+static void __exit cleanup(void)
+{
+#ifdef OTG_TRANSCEIVER
+ return langwell_unregister_peripheral(&langwell_pci_driver);
+#else
+ pci_unregister_driver(&langwell_pci_driver);
+#endif
+}
+module_exit(cleanup);
+
diff --git a/drivers/usb/gadget/langwell_udc.h b/drivers/usb/gadget/langwell_udc.h
new file mode 100644
index 00000000000..9719934e1c0
--- /dev/null
+++ b/drivers/usb/gadget/langwell_udc.h
@@ -0,0 +1,228 @@
+/*
+ * Intel Langwell USB Device Controller driver
+ * Copyright (C) 2008-2009, Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ */
+
+#include <linux/usb/langwell_udc.h>
+
+#if defined(CONFIG_USB_LANGWELL_OTG)
+#include <linux/usb/langwell_otg.h>
+#endif
+
+
+/*-------------------------------------------------------------------------*/
+
+/* driver data structures and utilities */
+
+/*
+ * dTD: Device Endpoint Transfer Descriptor
+ * describe to the device controller the location and quantity of
+ * data to be send/received for given transfer
+ */
+struct langwell_dtd {
+ u32 dtd_next;
+/* bits 31:5, next transfer element pointer */
+#define DTD_NEXT(d) (((d)>>5)&0x7ffffff)
+#define DTD_NEXT_MASK (0x7ffffff << 5)
+/* terminate */
+#define DTD_TERM BIT(0)
+ /* bits 7:0, execution back states */
+ u32 dtd_status:8;
+#define DTD_STATUS(d) (((d)>>0)&0xff)
+#define DTD_STS_ACTIVE BIT(7) /* active */
+#define DTD_STS_HALTED BIT(6) /* halted */
+#define DTD_STS_DBE BIT(5) /* data buffer error */
+#define DTD_STS_TRE BIT(3) /* transaction error */
+ /* bits 9:8 */
+ u32 dtd_res0:2;
+ /* bits 11:10, multipier override */
+ u32 dtd_multo:2;
+#define DTD_MULTO (BIT(11) | BIT(10))
+ /* bits 14:12 */
+ u32 dtd_res1:3;
+ /* bit 15, interrupt on complete */
+ u32 dtd_ioc:1;
+#define DTD_IOC BIT(15)
+ /* bits 30:16, total bytes */
+ u32 dtd_total:15;
+#define DTD_TOTAL(d) (((d)>>16)&0x7fff)
+#define DTD_MAX_TRANSFER_LENGTH 0x4000
+ /* bit 31 */
+ u32 dtd_res2:1;
+ /* dTD buffer pointer page 0 to 4 */
+ u32 dtd_buf[5];
+#define DTD_OFFSET_MASK 0xfff
+/* bits 31:12, buffer pointer */
+#define DTD_BUFFER(d) (((d)>>12)&0x3ff)
+/* bits 11:0, current offset */
+#define DTD_C_OFFSET(d) (((d)>>0)&0xfff)
+/* bits 10:0, frame number */
+#define DTD_FRAME(d) (((d)>>0)&0x7ff)
+
+ /* driver-private parts */
+
+ /* dtd dma address */
+ dma_addr_t dtd_dma;
+ /* next dtd virtual address */
+ struct langwell_dtd *next_dtd_virt;
+};
+
+
+/*
+ * dQH: Device Endpoint Queue Head
+ * describe where all transfers are managed
+ * 48-byte data structure, aligned on 64-byte boundary
+ *
+ * These are associated with dTD structure
+ */
+struct langwell_dqh {
+ /* endpoint capabilities and characteristics */
+ u32 dqh_res0:15; /* bits 14:0 */
+ u32 dqh_ios:1; /* bit 15, interrupt on setup */
+#define DQH_IOS BIT(15)
+ u32 dqh_mpl:11; /* bits 26:16, maximum packet length */
+#define DQH_MPL (0x7ff << 16)
+ u32 dqh_res1:2; /* bits 28:27 */
+ u32 dqh_zlt:1; /* bit 29, zero length termination */
+#define DQH_ZLT BIT(29)
+ u32 dqh_mult:2; /* bits 31:30 */
+#define DQH_MULT (BIT(30) | BIT(31))
+
+ /* current dTD pointer */
+ u32 dqh_current; /* locate the transfer in progress */
+#define DQH_C_DTD(e) \
+ (((e)>>5)&0x7ffffff) /* bits 31:5, current dTD pointer */
+
+ /* transfer overlay, hardware parts of a struct langwell_dtd */
+ u32 dtd_next;
+ u32 dtd_status:8; /* bits 7:0, execution back states */
+ u32 dtd_res0:2; /* bits 9:8 */
+ u32 dtd_multo:2; /* bits 11:10, multipier override */
+ u32 dtd_res1:3; /* bits 14:12 */
+ u32 dtd_ioc:1; /* bit 15, interrupt on complete */
+ u32 dtd_total:15; /* bits 30:16, total bytes */
+ u32 dtd_res2:1; /* bit 31 */
+ u32 dtd_buf[5]; /* dTD buffer pointer page 0 to 4 */
+
+ u32 dqh_res2;
+ struct usb_ctrlrequest dqh_setup; /* setup packet buffer */
+} __attribute__ ((aligned(64)));
+
+
+/* endpoint data structure */
+struct langwell_ep {
+ struct usb_ep ep;
+ dma_addr_t dma;
+ struct langwell_udc *dev;
+ unsigned long irqs;
+ struct list_head queue;
+ struct langwell_dqh *dqh;
+ const struct usb_endpoint_descriptor *desc;
+ char name[14];
+ unsigned stopped:1,
+ ep_type:2,
+ ep_num:8;
+};
+
+
+/* request data structure */
+struct langwell_request {
+ struct usb_request req;
+ struct langwell_dtd *dtd, *head, *tail;
+ struct langwell_ep *ep;
+ dma_addr_t dtd_dma;
+ struct list_head queue;
+ unsigned dtd_count;
+ unsigned mapped:1;
+};
+
+
+/* ep0 transfer state */
+enum ep0_state {
+ WAIT_FOR_SETUP,
+ DATA_STATE_XMIT,
+ DATA_STATE_NEED_ZLP,
+ WAIT_FOR_OUT_STATUS,
+ DATA_STATE_RECV,
+};
+
+
+/* device suspend state */
+enum lpm_state {
+ LPM_L0, /* on */
+ LPM_L1, /* LPM L1 sleep */
+ LPM_L2, /* suspend */
+ LPM_L3, /* off */
+};
+
+
+/* device data structure */
+struct langwell_udc {
+ /* each pci device provides one gadget, several endpoints */
+ struct usb_gadget gadget;
+ spinlock_t lock; /* device lock */
+ struct langwell_ep *ep;
+ struct usb_gadget_driver *driver;
+ struct otg_transceiver *transceiver;
+ u8 dev_addr;
+ u32 usb_state;
+ u32 resume_state;
+ u32 bus_reset;
+ enum lpm_state lpm_state;
+ enum ep0_state ep0_state;
+ u32 ep0_dir;
+ u16 dciversion;
+ unsigned ep_max;
+ unsigned devcap:1,
+ enabled:1,
+ region:1,
+ got_irq:1,
+ powered:1,
+ remote_wakeup:1,
+ rate:1,
+ is_reset:1,
+ softconnected:1,
+ vbus_active:1,
+ suspended:1,
+ stopped:1,
+ lpm:1; /* LPM capability */
+
+ /* pci state used to access those endpoints */
+ struct pci_dev *pdev;
+
+ /* Langwell otg transceiver */
+ struct langwell_otg *lotg;
+
+ /* control registers */
+ struct langwell_cap_regs __iomem *cap_regs;
+ struct langwell_op_regs __iomem *op_regs;
+
+ struct usb_ctrlrequest local_setup_buff;
+ struct langwell_dqh *ep_dqh;
+ size_t ep_dqh_size;
+ dma_addr_t ep_dqh_dma;
+
+ /* ep0 status request */
+ struct langwell_request *status_req;
+
+ /* dma pool */
+ struct dma_pool *dtd_pool;
+
+ /* make sure release() is done */
+ struct completion *done;
+};
+
diff --git a/drivers/usb/gadget/pxa27x_udc.c b/drivers/usb/gadget/pxa27x_udc.c
index 8cc676ecbb2..1937d8c7b43 100644
--- a/drivers/usb/gadget/pxa27x_udc.c
+++ b/drivers/usb/gadget/pxa27x_udc.c
@@ -38,7 +38,6 @@
#include <linux/usb.h>
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
-#include <mach/pxa2xx-regs.h> /* FIXME: for PSSR */
#include <mach/udc.h>
#include "pxa27x_udc.h"
@@ -474,6 +473,23 @@ static inline void udc_clear_mask_UDCCR(struct pxa_udc *udc, int mask)
}
/**
+ * ep_write_UDCCSR - set bits in UDCCSR
+ * @udc: udc device
+ * @mask: bits to set in UDCCR
+ *
+ * Sets bits in UDCCSR (UDCCSR0 and UDCCSR*).
+ *
+ * A specific case is applied to ep0 : the ACM bit is always set to 1, for
+ * SET_INTERFACE and SET_CONFIGURATION.
+ */
+static inline void ep_write_UDCCSR(struct pxa_ep *ep, int mask)
+{
+ if (is_ep0(ep))
+ mask |= UDCCSR0_ACM;
+ udc_ep_writel(ep, UDCCSR, mask);
+}
+
+/**
* ep_count_bytes_remain - get how many bytes in udc endpoint
* @ep: udc endpoint
*
@@ -861,7 +877,7 @@ static int read_packet(struct pxa_ep *ep, struct pxa27x_request *req)
*buf++ = udc_ep_readl(ep, UDCDR);
req->req.actual += count;
- udc_ep_writel(ep, UDCCSR, UDCCSR_PC);
+ ep_write_UDCCSR(ep, UDCCSR_PC);
return count;
}
@@ -969,12 +985,12 @@ static int write_fifo(struct pxa_ep *ep, struct pxa27x_request *req)
if (udccsr & UDCCSR_PC) {
ep_vdbg(ep, "Clearing Transmit Complete, udccsr=%x\n",
udccsr);
- udc_ep_writel(ep, UDCCSR, UDCCSR_PC);
+ ep_write_UDCCSR(ep, UDCCSR_PC);
}
if (udccsr & UDCCSR_TRN) {
ep_vdbg(ep, "Clearing Underrun on, udccsr=%x\n",
udccsr);
- udc_ep_writel(ep, UDCCSR, UDCCSR_TRN);
+ ep_write_UDCCSR(ep, UDCCSR_TRN);
}
count = write_packet(ep, req, max);
@@ -996,7 +1012,7 @@ static int write_fifo(struct pxa_ep *ep, struct pxa27x_request *req)
}
if (is_short)
- udc_ep_writel(ep, UDCCSR, UDCCSR_SP);
+ ep_write_UDCCSR(ep, UDCCSR_SP);
/* requests complete when all IN data is in the FIFO */
if (is_last) {
@@ -1029,7 +1045,7 @@ static int read_ep0_fifo(struct pxa_ep *ep, struct pxa27x_request *req)
while (epout_has_pkt(ep)) {
count = read_packet(ep, req);
- udc_ep_writel(ep, UDCCSR, UDCCSR0_OPC);
+ ep_write_UDCCSR(ep, UDCCSR0_OPC);
inc_ep_stats_bytes(ep, count, !USB_DIR_IN);
is_short = (count < ep->fifo_size);
@@ -1074,7 +1090,7 @@ static int write_ep0_fifo(struct pxa_ep *ep, struct pxa27x_request *req)
/* Sends either a short packet or a 0 length packet */
if (unlikely(is_short))
- udc_ep_writel(ep, UDCCSR, UDCCSR0_IPR);
+ ep_write_UDCCSR(ep, UDCCSR0_IPR);
ep_dbg(ep, "in %d bytes%s%s, %d left, req=%p, udccsr0=0x%03x\n",
count, is_short ? "/S" : "", is_last ? "/L" : "",
@@ -1277,7 +1293,7 @@ static int pxa_ep_set_halt(struct usb_ep *_ep, int value)
/* FST, FEF bits are the same for control and non control endpoints */
rc = 0;
- udc_ep_writel(ep, UDCCSR, UDCCSR_FST | UDCCSR_FEF);
+ ep_write_UDCCSR(ep, UDCCSR_FST | UDCCSR_FEF);
if (is_ep0(ep))
set_ep0state(ep->dev, STALL);
@@ -1343,7 +1359,7 @@ static void pxa_ep_fifo_flush(struct usb_ep *_ep)
udc_ep_readl(ep, UDCDR);
} else {
/* most IN status is the same, but ISO can't stall */
- udc_ep_writel(ep, UDCCSR,
+ ep_write_UDCCSR(ep,
UDCCSR_PC | UDCCSR_FEF | UDCCSR_TRN
| (EPXFERTYPE_is_ISO(ep) ? 0 : UDCCSR_SST));
}
@@ -1728,6 +1744,7 @@ static void udc_enable(struct pxa_udc *udc)
memset(&udc->stats, 0, sizeof(udc->stats));
udc_set_mask_UDCCR(udc, UDCCR_UDE);
+ ep_write_UDCCSR(&udc->pxa_ep[0], UDCCSR0_ACM);
udelay(2);
if (udc_readl(udc, UDCCR) & UDCCR_EMCE)
dev_err(udc->dev, "Configuration errors, udc disabled\n");
@@ -1893,6 +1910,15 @@ static void handle_ep0_ctrl_req(struct pxa_udc *udc,
nuke(ep, -EPROTO);
+ /*
+ * In the PXA320 manual, in the section about Back-to-Back setup
+ * packets, it describes this situation. The solution is to set OPC to
+ * get rid of the status packet, and then continue with the setup
+ * packet. Generalize to pxa27x CPUs.
+ */
+ if (epout_has_pkt(ep) && (ep_count_bytes_remain(ep) == 0))
+ ep_write_UDCCSR(ep, UDCCSR0_OPC);
+
/* read SETUP packet */
for (i = 0; i < 2; i++) {
if (unlikely(ep_is_empty(ep)))
@@ -1919,7 +1945,7 @@ static void handle_ep0_ctrl_req(struct pxa_udc *udc,
set_ep0state(udc, OUT_DATA_STAGE);
/* Tell UDC to enter Data Stage */
- udc_ep_writel(ep, UDCCSR, UDCCSR0_SA | UDCCSR0_OPC);
+ ep_write_UDCCSR(ep, UDCCSR0_SA | UDCCSR0_OPC);
i = udc->driver->setup(&udc->gadget, &u.r);
if (i < 0)
@@ -1929,7 +1955,7 @@ out:
stall:
ep_dbg(ep, "protocol STALL, udccsr0=%03x err %d\n",
udc_ep_readl(ep, UDCCSR), i);
- udc_ep_writel(ep, UDCCSR, UDCCSR0_FST | UDCCSR0_FTF);
+ ep_write_UDCCSR(ep, UDCCSR0_FST | UDCCSR0_FTF);
set_ep0state(udc, STALL);
goto out;
}
@@ -1966,6 +1992,8 @@ stall:
* cleared by software.
* - clearing UDCCSR0_OPC always flushes ep0. If in setup stage, never do it
* before reading ep0.
+ * This is true only for PXA27x. This is not true anymore for PXA3xx family
+ * (check Back-to-Back setup packet in developers guide).
* - irq can be called on a "packet complete" event (opc_irq=1), while
* UDCCSR0_OPC is not yet raised (delta can be as big as 100ms
* from experimentation).
@@ -1998,7 +2026,7 @@ static void handle_ep0(struct pxa_udc *udc, int fifo_irq, int opc_irq)
if (udccsr0 & UDCCSR0_SST) {
ep_dbg(ep, "clearing stall status\n");
nuke(ep, -EPIPE);
- udc_ep_writel(ep, UDCCSR, UDCCSR0_SST);
+ ep_write_UDCCSR(ep, UDCCSR0_SST);
ep0_idle(udc);
}
@@ -2023,7 +2051,7 @@ static void handle_ep0(struct pxa_udc *udc, int fifo_irq, int opc_irq)
break;
case IN_DATA_STAGE: /* GET_DESCRIPTOR */
if (epout_has_pkt(ep))
- udc_ep_writel(ep, UDCCSR, UDCCSR0_OPC);
+ ep_write_UDCCSR(ep, UDCCSR0_OPC);
if (req && !ep_is_full(ep))
completed = write_ep0_fifo(ep, req);
if (completed)
@@ -2036,7 +2064,7 @@ static void handle_ep0(struct pxa_udc *udc, int fifo_irq, int opc_irq)
ep0_end_out_req(ep, req);
break;
case STALL:
- udc_ep_writel(ep, UDCCSR, UDCCSR0_FST);
+ ep_write_UDCCSR(ep, UDCCSR0_FST);
break;
case IN_STATUS_STAGE:
/*
@@ -2131,6 +2159,7 @@ static void pxa27x_change_configuration(struct pxa_udc *udc, int config)
set_ep0state(udc, WAIT_ACK_SET_CONF_INTERF);
udc->driver->setup(&udc->gadget, &req);
+ ep_write_UDCCSR(&udc->pxa_ep[0], UDCCSR0_AREN);
}
/**
@@ -2159,6 +2188,7 @@ static void pxa27x_change_interface(struct pxa_udc *udc, int iface, int alt)
set_ep0state(udc, WAIT_ACK_SET_CONF_INTERF);
udc->driver->setup(&udc->gadget, &req);
+ ep_write_UDCCSR(&udc->pxa_ep[0], UDCCSR0_AREN);
}
/*
@@ -2280,7 +2310,7 @@ static void irq_udc_reset(struct pxa_udc *udc)
memset(&udc->stats, 0, sizeof udc->stats);
nuke(ep, -EPROTO);
- udc_ep_writel(ep, UDCCSR, UDCCSR0_FTF | UDCCSR0_OPC);
+ ep_write_UDCCSR(ep, UDCCSR0_FTF | UDCCSR0_OPC);
ep0_idle(udc);
}
@@ -2479,6 +2509,12 @@ static void pxa_udc_shutdown(struct platform_device *_dev)
udc_disable(udc);
}
+#ifdef CONFIG_CPU_PXA27x
+extern void pxa27x_clear_otgph(void);
+#else
+#define pxa27x_clear_otgph() do {} while (0)
+#endif
+
#ifdef CONFIG_PM
/**
* pxa_udc_suspend - Suspend udc device
@@ -2546,8 +2582,7 @@ static int pxa_udc_resume(struct platform_device *_dev)
* Software must configure the USB OTG pad, UDC, and UHC
* to the state they were in before entering sleep mode.
*/
- if (cpu_is_pxa27x())
- PSSR |= PSSR_OTGPH;
+ pxa27x_clear_otgph();
return 0;
}
@@ -2571,7 +2606,7 @@ static struct platform_driver udc_driver = {
static int __init udc_init(void)
{
- if (!cpu_is_pxa27x())
+ if (!cpu_is_pxa27x() && !cpu_is_pxa3xx())
return -ENODEV;
printk(KERN_INFO "%s: version %s\n", driver_name, DRIVER_VERSION);
diff --git a/drivers/usb/gadget/pxa27x_udc.h b/drivers/usb/gadget/pxa27x_udc.h
index db58125331d..e25225e2658 100644
--- a/drivers/usb/gadget/pxa27x_udc.h
+++ b/drivers/usb/gadget/pxa27x_udc.h
@@ -130,6 +130,8 @@
#define UP2OCR_HXOE (1 << 17) /* Transceiver Output Enable */
#define UP2OCR_SEOS (1 << 24) /* Single-Ended Output Select */
+#define UDCCSR0_ACM (1 << 9) /* Ack Control Mode */
+#define UDCCSR0_AREN (1 << 8) /* Ack Response Enable */
#define UDCCSR0_SA (1 << 7) /* Setup Active */
#define UDCCSR0_RNE (1 << 6) /* Receive FIFO Not Empty */
#define UDCCSR0_FST (1 << 5) /* Force Stall */
diff --git a/drivers/usb/gadget/s3c-hsotg.c b/drivers/usb/gadget/s3c-hsotg.c
new file mode 100644
index 00000000000..50c71aae2cc
--- /dev/null
+++ b/drivers/usb/gadget/s3c-hsotg.c
@@ -0,0 +1,3269 @@
+/* linux/drivers/usb/gadget/s3c-hsotg.c
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * S3C USB2.0 High-speed / OtG driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/spinlock.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+
+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+
+#include <mach/map.h>
+
+#include <plat/regs-usb-hsotg-phy.h>
+#include <plat/regs-usb-hsotg.h>
+#include <plat/regs-sys.h>
+#include <plat/udc-hs.h>
+
+#define DMA_ADDR_INVALID (~((dma_addr_t)0))
+
+/* EP0_MPS_LIMIT
+ *
+ * Unfortunately there seems to be a limit of the amount of data that can
+ * be transfered by IN transactions on EP0. This is either 127 bytes or 3
+ * packets (which practially means 1 packet and 63 bytes of data) when the
+ * MPS is set to 64.
+ *
+ * This means if we are wanting to move >127 bytes of data, we need to
+ * split the transactions up, but just doing one packet at a time does
+ * not work (this may be an implicit DATA0 PID on first packet of the
+ * transaction) and doing 2 packets is outside the controller's limits.
+ *
+ * If we try to lower the MPS size for EP0, then no transfers work properly
+ * for EP0, and the system will fail basic enumeration. As no cause for this
+ * has currently been found, we cannot support any large IN transfers for
+ * EP0.
+ */
+#define EP0_MPS_LIMIT 64
+
+struct s3c_hsotg;
+struct s3c_hsotg_req;
+
+/**
+ * struct s3c_hsotg_ep - driver endpoint definition.
+ * @ep: The gadget layer representation of the endpoint.
+ * @name: The driver generated name for the endpoint.
+ * @queue: Queue of requests for this endpoint.
+ * @parent: Reference back to the parent device structure.
+ * @req: The current request that the endpoint is processing. This is
+ * used to indicate an request has been loaded onto the endpoint
+ * and has yet to be completed (maybe due to data move, or simply
+ * awaiting an ack from the core all the data has been completed).
+ * @debugfs: File entry for debugfs file for this endpoint.
+ * @lock: State lock to protect contents of endpoint.
+ * @dir_in: Set to true if this endpoint is of the IN direction, which
+ * means that it is sending data to the Host.
+ * @index: The index for the endpoint registers.
+ * @name: The name array passed to the USB core.
+ * @halted: Set if the endpoint has been halted.
+ * @periodic: Set if this is a periodic ep, such as Interrupt
+ * @sent_zlp: Set if we've sent a zero-length packet.
+ * @total_data: The total number of data bytes done.
+ * @fifo_size: The size of the FIFO (for periodic IN endpoints)
+ * @fifo_load: The amount of data loaded into the FIFO (periodic IN)
+ * @last_load: The offset of data for the last start of request.
+ * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN
+ *
+ * This is the driver's state for each registered enpoint, allowing it
+ * to keep track of transactions that need doing. Each endpoint has a
+ * lock to protect the state, to try and avoid using an overall lock
+ * for the host controller as much as possible.
+ *
+ * For periodic IN endpoints, we have fifo_size and fifo_load to try
+ * and keep track of the amount of data in the periodic FIFO for each
+ * of these as we don't have a status register that tells us how much
+ * is in each of them.
+ */
+struct s3c_hsotg_ep {
+ struct usb_ep ep;
+ struct list_head queue;
+ struct s3c_hsotg *parent;
+ struct s3c_hsotg_req *req;
+ struct dentry *debugfs;
+
+ spinlock_t lock;
+
+ unsigned long total_data;
+ unsigned int size_loaded;
+ unsigned int last_load;
+ unsigned int fifo_load;
+ unsigned short fifo_size;
+
+ unsigned char dir_in;
+ unsigned char index;
+
+ unsigned int halted:1;
+ unsigned int periodic:1;
+ unsigned int sent_zlp:1;
+
+ char name[10];
+};
+
+#define S3C_HSOTG_EPS (8+1) /* limit to 9 for the moment */
+
+/**
+ * struct s3c_hsotg - driver state.
+ * @dev: The parent device supplied to the probe function
+ * @driver: USB gadget driver
+ * @plat: The platform specific configuration data.
+ * @regs: The memory area mapped for accessing registers.
+ * @regs_res: The resource that was allocated when claiming register space.
+ * @irq: The IRQ number we are using
+ * @debug_root: root directrory for debugfs.
+ * @debug_file: main status file for debugfs.
+ * @debug_fifo: FIFO status file for debugfs.
+ * @ep0_reply: Request used for ep0 reply.
+ * @ep0_buff: Buffer for EP0 reply data, if needed.
+ * @ctrl_buff: Buffer for EP0 control requests.
+ * @ctrl_req: Request for EP0 control packets.
+ * @eps: The endpoints being supplied to the gadget framework
+ */
+struct s3c_hsotg {
+ struct device *dev;
+ struct usb_gadget_driver *driver;
+ struct s3c_hsotg_plat *plat;
+
+ void __iomem *regs;
+ struct resource *regs_res;
+ int irq;
+
+ struct dentry *debug_root;
+ struct dentry *debug_file;
+ struct dentry *debug_fifo;
+
+ struct usb_request *ep0_reply;
+ struct usb_request *ctrl_req;
+ u8 ep0_buff[8];
+ u8 ctrl_buff[8];
+
+ struct usb_gadget gadget;
+ struct s3c_hsotg_ep eps[];
+};
+
+/**
+ * struct s3c_hsotg_req - data transfer request
+ * @req: The USB gadget request
+ * @queue: The list of requests for the endpoint this is queued for.
+ * @in_progress: Has already had size/packets written to core
+ * @mapped: DMA buffer for this request has been mapped via dma_map_single().
+ */
+struct s3c_hsotg_req {
+ struct usb_request req;
+ struct list_head queue;
+ unsigned char in_progress;
+ unsigned char mapped;
+};
+
+/* conversion functions */
+static inline struct s3c_hsotg_req *our_req(struct usb_request *req)
+{
+ return container_of(req, struct s3c_hsotg_req, req);
+}
+
+static inline struct s3c_hsotg_ep *our_ep(struct usb_ep *ep)
+{
+ return container_of(ep, struct s3c_hsotg_ep, ep);
+}
+
+static inline struct s3c_hsotg *to_hsotg(struct usb_gadget *gadget)
+{
+ return container_of(gadget, struct s3c_hsotg, gadget);
+}
+
+static inline void __orr32(void __iomem *ptr, u32 val)
+{
+ writel(readl(ptr) | val, ptr);
+}
+
+static inline void __bic32(void __iomem *ptr, u32 val)
+{
+ writel(readl(ptr) & ~val, ptr);
+}
+
+/* forward decleration of functions */
+static void s3c_hsotg_dump(struct s3c_hsotg *hsotg);
+
+/**
+ * using_dma - return the DMA status of the driver.
+ * @hsotg: The driver state.
+ *
+ * Return true if we're using DMA.
+ *
+ * Currently, we have the DMA support code worked into everywhere
+ * that needs it, but the AMBA DMA implementation in the hardware can
+ * only DMA from 32bit aligned addresses. This means that gadgets such
+ * as the CDC Ethernet cannot work as they often pass packets which are
+ * not 32bit aligned.
+ *
+ * Unfortunately the choice to use DMA or not is global to the controller
+ * and seems to be only settable when the controller is being put through
+ * a core reset. This means we either need to fix the gadgets to take
+ * account of DMA alignment, or add bounce buffers (yuerk).
+ *
+ * Until this issue is sorted out, we always return 'false'.
+ */
+static inline bool using_dma(struct s3c_hsotg *hsotg)
+{
+ return false; /* support is not complete */
+}
+
+/**
+ * s3c_hsotg_en_gsint - enable one or more of the general interrupt
+ * @hsotg: The device state
+ * @ints: A bitmask of the interrupts to enable
+ */
+static void s3c_hsotg_en_gsint(struct s3c_hsotg *hsotg, u32 ints)
+{
+ u32 gsintmsk = readl(hsotg->regs + S3C_GINTMSK);
+ u32 new_gsintmsk;
+
+ new_gsintmsk = gsintmsk | ints;
+
+ if (new_gsintmsk != gsintmsk) {
+ dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
+ writel(new_gsintmsk, hsotg->regs + S3C_GINTMSK);
+ }
+}
+
+/**
+ * s3c_hsotg_disable_gsint - disable one or more of the general interrupt
+ * @hsotg: The device state
+ * @ints: A bitmask of the interrupts to enable
+ */
+static void s3c_hsotg_disable_gsint(struct s3c_hsotg *hsotg, u32 ints)
+{
+ u32 gsintmsk = readl(hsotg->regs + S3C_GINTMSK);
+ u32 new_gsintmsk;
+
+ new_gsintmsk = gsintmsk & ~ints;
+
+ if (new_gsintmsk != gsintmsk)
+ writel(new_gsintmsk, hsotg->regs + S3C_GINTMSK);
+}
+
+/**
+ * s3c_hsotg_ctrl_epint - enable/disable an endpoint irq
+ * @hsotg: The device state
+ * @ep: The endpoint index
+ * @dir_in: True if direction is in.
+ * @en: The enable value, true to enable
+ *
+ * Set or clear the mask for an individual endpoint's interrupt
+ * request.
+ */
+static void s3c_hsotg_ctrl_epint(struct s3c_hsotg *hsotg,
+ unsigned int ep, unsigned int dir_in,
+ unsigned int en)
+{
+ unsigned long flags;
+ u32 bit = 1 << ep;
+ u32 daint;
+
+ if (!dir_in)
+ bit <<= 16;
+
+ local_irq_save(flags);
+ daint = readl(hsotg->regs + S3C_DAINTMSK);
+ if (en)
+ daint |= bit;
+ else
+ daint &= ~bit;
+ writel(daint, hsotg->regs + S3C_DAINTMSK);
+ local_irq_restore(flags);
+}
+
+/**
+ * s3c_hsotg_init_fifo - initialise non-periodic FIFOs
+ * @hsotg: The device instance.
+ */
+static void s3c_hsotg_init_fifo(struct s3c_hsotg *hsotg)
+{
+ /* the ryu 2.6.24 release ahs
+ writel(0x1C0, hsotg->regs + S3C_GRXFSIZ);
+ writel(S3C_GNPTXFSIZ_NPTxFStAddr(0x200) |
+ S3C_GNPTXFSIZ_NPTxFDep(0x1C0),
+ hsotg->regs + S3C_GNPTXFSIZ);
+ */
+
+ /* set FIFO sizes to 2048/0x1C0 */
+
+ writel(2048, hsotg->regs + S3C_GRXFSIZ);
+ writel(S3C_GNPTXFSIZ_NPTxFStAddr(2048) |
+ S3C_GNPTXFSIZ_NPTxFDep(0x1C0),
+ hsotg->regs + S3C_GNPTXFSIZ);
+}
+
+/**
+ * @ep: USB endpoint to allocate request for.
+ * @flags: Allocation flags
+ *
+ * Allocate a new USB request structure appropriate for the specified endpoint
+ */
+struct usb_request *s3c_hsotg_ep_alloc_request(struct usb_ep *ep, gfp_t flags)
+{
+ struct s3c_hsotg_req *req;
+
+ req = kzalloc(sizeof(struct s3c_hsotg_req), flags);
+ if (!req)
+ return NULL;
+
+ INIT_LIST_HEAD(&req->queue);
+
+ req->req.dma = DMA_ADDR_INVALID;
+ return &req->req;
+}
+
+/**
+ * is_ep_periodic - return true if the endpoint is in periodic mode.
+ * @hs_ep: The endpoint to query.
+ *
+ * Returns true if the endpoint is in periodic mode, meaning it is being
+ * used for an Interrupt or ISO transfer.
+ */
+static inline int is_ep_periodic(struct s3c_hsotg_ep *hs_ep)
+{
+ return hs_ep->periodic;
+}
+
+/**
+ * s3c_hsotg_unmap_dma - unmap the DMA memory being used for the request
+ * @hsotg: The device state.
+ * @hs_ep: The endpoint for the request
+ * @hs_req: The request being processed.
+ *
+ * This is the reverse of s3c_hsotg_map_dma(), called for the completion
+ * of a request to ensure the buffer is ready for access by the caller.
+*/
+static void s3c_hsotg_unmap_dma(struct s3c_hsotg *hsotg,
+ struct s3c_hsotg_ep *hs_ep,
+ struct s3c_hsotg_req *hs_req)
+{
+ struct usb_request *req = &hs_req->req;
+ enum dma_data_direction dir;
+
+ dir = hs_ep->dir_in ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
+
+ /* ignore this if we're not moving any data */
+ if (hs_req->req.length == 0)
+ return;
+
+ if (hs_req->mapped) {
+ /* we mapped this, so unmap and remove the dma */
+
+ dma_unmap_single(hsotg->dev, req->dma, req->length, dir);
+
+ req->dma = DMA_ADDR_INVALID;
+ hs_req->mapped = 0;
+ } else {
+ dma_sync_single(hsotg->dev, req->dma, req->length, dir);
+ }
+}
+
+/**
+ * s3c_hsotg_write_fifo - write packet Data to the TxFIFO
+ * @hsotg: The controller state.
+ * @hs_ep: The endpoint we're going to write for.
+ * @hs_req: The request to write data for.
+ *
+ * This is called when the TxFIFO has some space in it to hold a new
+ * transmission and we have something to give it. The actual setup of
+ * the data size is done elsewhere, so all we have to do is to actually
+ * write the data.
+ *
+ * The return value is zero if there is more space (or nothing was done)
+ * otherwise -ENOSPC is returned if the FIFO space was used up.
+ *
+ * This routine is only needed for PIO
+*/
+static int s3c_hsotg_write_fifo(struct s3c_hsotg *hsotg,
+ struct s3c_hsotg_ep *hs_ep,
+ struct s3c_hsotg_req *hs_req)
+{
+ bool periodic = is_ep_periodic(hs_ep);
+ u32 gnptxsts = readl(hsotg->regs + S3C_GNPTXSTS);
+ int buf_pos = hs_req->req.actual;
+ int to_write = hs_ep->size_loaded;
+ void *data;
+ int can_write;
+ int pkt_round;
+
+ to_write -= (buf_pos - hs_ep->last_load);
+
+ /* if there's nothing to write, get out early */
+ if (to_write == 0)
+ return 0;
+
+ if (periodic) {
+ u32 epsize = readl(hsotg->regs + S3C_DIEPTSIZ(hs_ep->index));
+ int size_left;
+ int size_done;
+
+ /* work out how much data was loaded so we can calculate
+ * how much data is left in the fifo. */
+
+ size_left = S3C_DxEPTSIZ_XferSize_GET(epsize);
+
+ dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n",
+ __func__, size_left,
+ hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size);
+
+ /* how much of the data has moved */
+ size_done = hs_ep->size_loaded - size_left;
+
+ /* how much data is left in the fifo */
+ can_write = hs_ep->fifo_load - size_done;
+ dev_dbg(hsotg->dev, "%s: => can_write1=%d\n",
+ __func__, can_write);
+
+ can_write = hs_ep->fifo_size - can_write;
+ dev_dbg(hsotg->dev, "%s: => can_write2=%d\n",
+ __func__, can_write);
+
+ if (can_write <= 0) {
+ s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_PTxFEmp);
+ return -ENOSPC;
+ }
+ } else {
+ if (S3C_GNPTXSTS_NPTxQSpcAvail_GET(gnptxsts) == 0) {
+ dev_dbg(hsotg->dev,
+ "%s: no queue slots available (0x%08x)\n",
+ __func__, gnptxsts);
+
+ s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_NPTxFEmp);
+ return -ENOSPC;
+ }
+
+ can_write = S3C_GNPTXSTS_NPTxFSpcAvail_GET(gnptxsts);
+ }
+
+ dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, mps %d\n",
+ __func__, gnptxsts, can_write, to_write, hs_ep->ep.maxpacket);
+
+ /* limit to 512 bytes of data, it seems at least on the non-periodic
+ * FIFO, requests of >512 cause the endpoint to get stuck with a
+ * fragment of the end of the transfer in it.
+ */
+ if (can_write > 512)
+ can_write = 512;
+
+ /* see if we can write data */
+
+ if (to_write > can_write) {
+ to_write = can_write;
+ pkt_round = to_write % hs_ep->ep.maxpacket;
+
+ /* Not sure, but we probably shouldn't be writing partial
+ * packets into the FIFO, so round the write down to an
+ * exact number of packets.
+ *
+ * Note, we do not currently check to see if we can ever
+ * write a full packet or not to the FIFO.
+ */
+
+ if (pkt_round)
+ to_write -= pkt_round;
+
+ /* enable correct FIFO interrupt to alert us when there
+ * is more room left. */
+
+ s3c_hsotg_en_gsint(hsotg,
+ periodic ? S3C_GINTSTS_PTxFEmp :
+ S3C_GINTSTS_NPTxFEmp);
+ }
+
+ dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n",
+ to_write, hs_req->req.length, can_write, buf_pos);
+
+ if (to_write <= 0)
+ return -ENOSPC;
+
+ hs_req->req.actual = buf_pos + to_write;
+ hs_ep->total_data += to_write;
+
+ if (periodic)
+ hs_ep->fifo_load += to_write;
+
+ to_write = DIV_ROUND_UP(to_write, 4);
+ data = hs_req->req.buf + buf_pos;
+
+ writesl(hsotg->regs + S3C_EPFIFO(hs_ep->index), data, to_write);
+
+ return (to_write >= can_write) ? -ENOSPC : 0;
+}
+
+/**
+ * get_ep_limit - get the maximum data legnth for this endpoint
+ * @hs_ep: The endpoint
+ *
+ * Return the maximum data that can be queued in one go on a given endpoint
+ * so that transfers that are too long can be split.
+ */
+static unsigned get_ep_limit(struct s3c_hsotg_ep *hs_ep)
+{
+ int index = hs_ep->index;
+ unsigned maxsize;
+ unsigned maxpkt;
+
+ if (index != 0) {
+ maxsize = S3C_DxEPTSIZ_XferSize_LIMIT + 1;
+ maxpkt = S3C_DxEPTSIZ_PktCnt_LIMIT + 1;
+ } else {
+ if (hs_ep->dir_in) {
+ /* maxsize = S3C_DIEPTSIZ0_XferSize_LIMIT + 1; */
+ maxsize = 64+64+1;
+ maxpkt = S3C_DIEPTSIZ0_PktCnt_LIMIT + 1;
+ } else {
+ maxsize = 0x3f;
+ maxpkt = 2;
+ }
+ }
+
+ /* we made the constant loading easier above by using +1 */
+ maxpkt--;
+ maxsize--;
+
+ /* constrain by packet count if maxpkts*pktsize is greater
+ * than the length register size. */
+
+ if ((maxpkt * hs_ep->ep.maxpacket) < maxsize)
+ maxsize = maxpkt * hs_ep->ep.maxpacket;
+
+ return maxsize;
+}
+
+/**
+ * s3c_hsotg_start_req - start a USB request from an endpoint's queue
+ * @hsotg: The controller state.
+ * @hs_ep: The endpoint to process a request for
+ * @hs_req: The request to start.
+ * @continuing: True if we are doing more for the current request.
+ *
+ * Start the given request running by setting the endpoint registers
+ * appropriately, and writing any data to the FIFOs.
+ */
+static void s3c_hsotg_start_req(struct s3c_hsotg *hsotg,
+ struct s3c_hsotg_ep *hs_ep,
+ struct s3c_hsotg_req *hs_req,
+ bool continuing)
+{
+ struct usb_request *ureq = &hs_req->req;
+ int index = hs_ep->index;
+ int dir_in = hs_ep->dir_in;
+ u32 epctrl_reg;
+ u32 epsize_reg;
+ u32 epsize;
+ u32 ctrl;
+ unsigned length;
+ unsigned packets;
+ unsigned maxreq;
+
+ if (index != 0) {
+ if (hs_ep->req && !continuing) {
+ dev_err(hsotg->dev, "%s: active request\n", __func__);
+ WARN_ON(1);
+ return;
+ } else if (hs_ep->req != hs_req && continuing) {
+ dev_err(hsotg->dev,
+ "%s: continue different req\n", __func__);
+ WARN_ON(1);
+ return;
+ }
+ }
+
+ epctrl_reg = dir_in ? S3C_DIEPCTL(index) : S3C_DOEPCTL(index);
+ epsize_reg = dir_in ? S3C_DIEPTSIZ(index) : S3C_DOEPTSIZ(index);
+
+ dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
+ __func__, readl(hsotg->regs + epctrl_reg), index,
+ hs_ep->dir_in ? "in" : "out");
+
+ length = ureq->length - ureq->actual;
+
+ if (0)
+ dev_dbg(hsotg->dev,
+ "REQ buf %p len %d dma 0x%08x noi=%d zp=%d snok=%d\n",
+ ureq->buf, length, ureq->dma,
+ ureq->no_interrupt, ureq->zero, ureq->short_not_ok);
+
+ maxreq = get_ep_limit(hs_ep);
+ if (length > maxreq) {
+ int round = maxreq % hs_ep->ep.maxpacket;
+
+ dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n",
+ __func__, length, maxreq, round);
+
+ /* round down to multiple of packets */
+ if (round)
+ maxreq -= round;
+
+ length = maxreq;
+ }
+
+ if (length)
+ packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket);
+ else
+ packets = 1; /* send one packet if length is zero. */
+
+ if (dir_in && index != 0)
+ epsize = S3C_DxEPTSIZ_MC(1);
+ else
+ epsize = 0;
+
+ if (index != 0 && ureq->zero) {
+ /* test for the packets being exactly right for the
+ * transfer */
+
+ if (length == (packets * hs_ep->ep.maxpacket))
+ packets++;
+ }
+
+ epsize |= S3C_DxEPTSIZ_PktCnt(packets);
+ epsize |= S3C_DxEPTSIZ_XferSize(length);
+
+ dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
+ __func__, packets, length, ureq->length, epsize, epsize_reg);
+
+ /* store the request as the current one we're doing */
+ hs_ep->req = hs_req;
+
+ /* write size / packets */
+ writel(epsize, hsotg->regs + epsize_reg);
+
+ ctrl = readl(hsotg->regs + epctrl_reg);
+
+ if (ctrl & S3C_DxEPCTL_Stall) {
+ dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
+
+ /* not sure what we can do here, if it is EP0 then we should
+ * get this cleared once the endpoint has transmitted the
+ * STALL packet, otherwise it needs to be cleared by the
+ * host.
+ */
+ }
+
+ if (using_dma(hsotg)) {
+ unsigned int dma_reg;
+
+ /* write DMA address to control register, buffer already
+ * synced by s3c_hsotg_ep_queue(). */
+
+ dma_reg = dir_in ? S3C_DIEPDMA(index) : S3C_DOEPDMA(index);
+ writel(ureq->dma, hsotg->regs + dma_reg);
+
+ dev_dbg(hsotg->dev, "%s: 0x%08x => 0x%08x\n",
+ __func__, ureq->dma, dma_reg);
+ }
+
+ ctrl |= S3C_DxEPCTL_EPEna; /* ensure ep enabled */
+ ctrl |= S3C_DxEPCTL_USBActEp;
+ ctrl |= S3C_DxEPCTL_CNAK; /* clear NAK set by core */
+
+ dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
+ writel(ctrl, hsotg->regs + epctrl_reg);
+
+ /* set these, it seems that DMA support increments past the end
+ * of the packet buffer so we need to calculate the length from
+ * this information. */
+ hs_ep->size_loaded = length;
+ hs_ep->last_load = ureq->actual;
+
+ if (dir_in && !using_dma(hsotg)) {
+ /* set these anyway, we may need them for non-periodic in */
+ hs_ep->fifo_load = 0;
+
+ s3c_hsotg_write_fifo(hsotg, hs_ep, hs_req);
+ }
+
+ /* clear the INTknTXFEmpMsk when we start request, more as a aide
+ * to debugging to see what is going on. */
+ if (dir_in)
+ writel(S3C_DIEPMSK_INTknTXFEmpMsk,
+ hsotg->regs + S3C_DIEPINT(index));
+
+ /* Note, trying to clear the NAK here causes problems with transmit
+ * on the S3C6400 ending up with the TXFIFO becomming full. */
+
+ /* check ep is enabled */
+ if (!(readl(hsotg->regs + epctrl_reg) & S3C_DxEPCTL_EPEna))
+ dev_warn(hsotg->dev,
+ "ep%d: failed to become enabled (DxEPCTL=0x%08x)?\n",
+ index, readl(hsotg->regs + epctrl_reg));
+
+ dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n",
+ __func__, readl(hsotg->regs + epctrl_reg));
+}
+
+/**
+ * s3c_hsotg_map_dma - map the DMA memory being used for the request
+ * @hsotg: The device state.
+ * @hs_ep: The endpoint the request is on.
+ * @req: The request being processed.
+ *
+ * We've been asked to queue a request, so ensure that the memory buffer
+ * is correctly setup for DMA. If we've been passed an extant DMA address
+ * then ensure the buffer has been synced to memory. If our buffer has no
+ * DMA memory, then we map the memory and mark our request to allow us to
+ * cleanup on completion.
+*/
+static int s3c_hsotg_map_dma(struct s3c_hsotg *hsotg,
+ struct s3c_hsotg_ep *hs_ep,
+ struct usb_request *req)
+{
+ enum dma_data_direction dir;
+ struct s3c_hsotg_req *hs_req = our_req(req);
+
+ dir = hs_ep->dir_in ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
+
+ /* if the length is zero, ignore the DMA data */
+ if (hs_req->req.length == 0)
+ return 0;
+
+ if (req->dma == DMA_ADDR_INVALID) {
+ dma_addr_t dma;
+
+ dma = dma_map_single(hsotg->dev, req->buf, req->length, dir);
+
+ if (unlikely(dma_mapping_error(hsotg->dev, dma)))
+ goto dma_error;
+
+ if (dma & 3) {
+ dev_err(hsotg->dev, "%s: unaligned dma buffer\n",
+ __func__);
+
+ dma_unmap_single(hsotg->dev, dma, req->length, dir);
+ return -EINVAL;
+ }
+
+ hs_req->mapped = 1;
+ req->dma = dma;
+ } else {
+ dma_sync_single(hsotg->dev, req->dma, req->length, dir);
+ hs_req->mapped = 0;
+ }
+
+ return 0;
+
+dma_error:
+ dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n",
+ __func__, req->buf, req->length);
+
+ return -EIO;
+}
+
+static int s3c_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
+ gfp_t gfp_flags)
+{
+ struct s3c_hsotg_req *hs_req = our_req(req);
+ struct s3c_hsotg_ep *hs_ep = our_ep(ep);
+ struct s3c_hsotg *hs = hs_ep->parent;
+ unsigned long irqflags;
+ bool first;
+
+ dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
+ ep->name, req, req->length, req->buf, req->no_interrupt,
+ req->zero, req->short_not_ok);
+
+ /* initialise status of the request */
+ INIT_LIST_HEAD(&hs_req->queue);
+ req->actual = 0;
+ req->status = -EINPROGRESS;
+
+ /* if we're using DMA, sync the buffers as necessary */
+ if (using_dma(hs)) {
+ int ret = s3c_hsotg_map_dma(hs, hs_ep, req);
+ if (ret)
+ return ret;
+ }
+
+ spin_lock_irqsave(&hs_ep->lock, irqflags);
+
+ first = list_empty(&hs_ep->queue);
+ list_add_tail(&hs_req->queue, &hs_ep->queue);
+
+ if (first)
+ s3c_hsotg_start_req(hs, hs_ep, hs_req, false);
+
+ spin_unlock_irqrestore(&hs_ep->lock, irqflags);
+
+ return 0;
+}
+
+static void s3c_hsotg_ep_free_request(struct usb_ep *ep,
+ struct usb_request *req)
+{
+ struct s3c_hsotg_req *hs_req = our_req(req);
+
+ kfree(hs_req);
+}
+
+/**
+ * s3c_hsotg_complete_oursetup - setup completion callback
+ * @ep: The endpoint the request was on.
+ * @req: The request completed.
+ *
+ * Called on completion of any requests the driver itself
+ * submitted that need cleaning up.
+ */
+static void s3c_hsotg_complete_oursetup(struct usb_ep *ep,
+ struct usb_request *req)
+{
+ struct s3c_hsotg_ep *hs_ep = our_ep(ep);
+ struct s3c_hsotg *hsotg = hs_ep->parent;
+
+ dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req);
+
+ s3c_hsotg_ep_free_request(ep, req);
+}
+
+/**
+ * ep_from_windex - convert control wIndex value to endpoint
+ * @hsotg: The driver state.
+ * @windex: The control request wIndex field (in host order).
+ *
+ * Convert the given wIndex into a pointer to an driver endpoint
+ * structure, or return NULL if it is not a valid endpoint.
+*/
+static struct s3c_hsotg_ep *ep_from_windex(struct s3c_hsotg *hsotg,
+ u32 windex)
+{
+ struct s3c_hsotg_ep *ep = &hsotg->eps[windex & 0x7F];
+ int dir = (windex & USB_DIR_IN) ? 1 : 0;
+ int idx = windex & 0x7F;
+
+ if (windex >= 0x100)
+ return NULL;
+
+ if (idx > S3C_HSOTG_EPS)
+ return NULL;
+
+ if (idx && ep->dir_in != dir)
+ return NULL;
+
+ return ep;
+}
+
+/**
+ * s3c_hsotg_send_reply - send reply to control request
+ * @hsotg: The device state
+ * @ep: Endpoint 0
+ * @buff: Buffer for request
+ * @length: Length of reply.
+ *
+ * Create a request and queue it on the given endpoint. This is useful as
+ * an internal method of sending replies to certain control requests, etc.
+ */
+static int s3c_hsotg_send_reply(struct s3c_hsotg *hsotg,
+ struct s3c_hsotg_ep *ep,
+ void *buff,
+ int length)
+{
+ struct usb_request *req;
+ int ret;
+
+ dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length);
+
+ req = s3c_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC);
+ hsotg->ep0_reply = req;
+ if (!req) {
+ dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__);
+ return -ENOMEM;
+ }
+
+ req->buf = hsotg->ep0_buff;
+ req->length = length;
+ req->zero = 1; /* always do zero-length final transfer */
+ req->complete = s3c_hsotg_complete_oursetup;
+
+ if (length)
+ memcpy(req->buf, buff, length);
+ else
+ ep->sent_zlp = 1;
+
+ ret = s3c_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC);
+ if (ret) {
+ dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__);
+ return ret;
+ }
+
+ return 0;
+}
+
+/**
+ * s3c_hsotg_process_req_status - process request GET_STATUS
+ * @hsotg: The device state
+ * @ctrl: USB control request
+ */
+static int s3c_hsotg_process_req_status(struct s3c_hsotg *hsotg,
+ struct usb_ctrlrequest *ctrl)
+{
+ struct s3c_hsotg_ep *ep0 = &hsotg->eps[0];
+ struct s3c_hsotg_ep *ep;
+ __le16 reply;
+ int ret;
+
+ dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__);
+
+ if (!ep0->dir_in) {
+ dev_warn(hsotg->dev, "%s: direction out?\n", __func__);
+ return -EINVAL;
+ }
+
+ switch (ctrl->bRequestType & USB_RECIP_MASK) {
+ case USB_RECIP_DEVICE:
+ reply = cpu_to_le16(0); /* bit 0 => self powered,
+ * bit 1 => remote wakeup */
+ break;
+
+ case USB_RECIP_INTERFACE:
+ /* currently, the data result should be zero */
+ reply = cpu_to_le16(0);
+ break;
+
+ case USB_RECIP_ENDPOINT:
+ ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
+ if (!ep)
+ return -ENOENT;
+
+ reply = cpu_to_le16(ep->halted ? 1 : 0);
+ break;
+
+ default:
+ return 0;
+ }
+
+ if (le16_to_cpu(ctrl->wLength) != 2)
+ return -EINVAL;
+
+ ret = s3c_hsotg_send_reply(hsotg, ep0, &reply, 2);
+ if (ret) {
+ dev_err(hsotg->dev, "%s: failed to send reply\n", __func__);
+ return ret;
+ }
+
+ return 1;
+}
+
+static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value);
+
+/**
+ * s3c_hsotg_process_req_featire - process request {SET,CLEAR}_FEATURE
+ * @hsotg: The device state
+ * @ctrl: USB control request
+ */
+static int s3c_hsotg_process_req_feature(struct s3c_hsotg *hsotg,
+ struct usb_ctrlrequest *ctrl)
+{
+ bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
+ struct s3c_hsotg_ep *ep;
+
+ dev_dbg(hsotg->dev, "%s: %s_FEATURE\n",
+ __func__, set ? "SET" : "CLEAR");
+
+ if (ctrl->bRequestType == USB_RECIP_ENDPOINT) {
+ ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
+ if (!ep) {
+ dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n",
+ __func__, le16_to_cpu(ctrl->wIndex));
+ return -ENOENT;
+ }
+
+ switch (le16_to_cpu(ctrl->wValue)) {
+ case USB_ENDPOINT_HALT:
+ s3c_hsotg_ep_sethalt(&ep->ep, set);
+ break;
+
+ default:
+ return -ENOENT;
+ }
+ } else
+ return -ENOENT; /* currently only deal with endpoint */
+
+ return 1;
+}
+
+/**
+ * s3c_hsotg_process_control - process a control request
+ * @hsotg: The device state
+ * @ctrl: The control request received
+ *
+ * The controller has received the SETUP phase of a control request, and
+ * needs to work out what to do next (and whether to pass it on to the
+ * gadget driver).
+ */
+static void s3c_hsotg_process_control(struct s3c_hsotg *hsotg,
+ struct usb_ctrlrequest *ctrl)
+{
+ struct s3c_hsotg_ep *ep0 = &hsotg->eps[0];
+ int ret = 0;
+ u32 dcfg;
+
+ ep0->sent_zlp = 0;
+
+ dev_dbg(hsotg->dev, "ctrl Req=%02x, Type=%02x, V=%04x, L=%04x\n",
+ ctrl->bRequest, ctrl->bRequestType,
+ ctrl->wValue, ctrl->wLength);
+
+ /* record the direction of the request, for later use when enquing
+ * packets onto EP0. */
+
+ ep0->dir_in = (ctrl->bRequestType & USB_DIR_IN) ? 1 : 0;
+ dev_dbg(hsotg->dev, "ctrl: dir_in=%d\n", ep0->dir_in);
+
+ /* if we've no data with this request, then the last part of the
+ * transaction is going to implicitly be IN. */
+ if (ctrl->wLength == 0)
+ ep0->dir_in = 1;
+
+ if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
+ switch (ctrl->bRequest) {
+ case USB_REQ_SET_ADDRESS:
+ dcfg = readl(hsotg->regs + S3C_DCFG);
+ dcfg &= ~S3C_DCFG_DevAddr_MASK;
+ dcfg |= ctrl->wValue << S3C_DCFG_DevAddr_SHIFT;
+ writel(dcfg, hsotg->regs + S3C_DCFG);
+
+ dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
+
+ ret = s3c_hsotg_send_reply(hsotg, ep0, NULL, 0);
+ return;
+
+ case USB_REQ_GET_STATUS:
+ ret = s3c_hsotg_process_req_status(hsotg, ctrl);
+ break;
+
+ case USB_REQ_CLEAR_FEATURE:
+ case USB_REQ_SET_FEATURE:
+ ret = s3c_hsotg_process_req_feature(hsotg, ctrl);
+ break;
+ }
+ }
+
+ /* as a fallback, try delivering it to the driver to deal with */
+
+ if (ret == 0 && hsotg->driver) {
+ ret = hsotg->driver->setup(&hsotg->gadget, ctrl);
+ if (ret < 0)
+ dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret);
+ }
+
+ if (ret > 0) {
+ if (!ep0->dir_in) {
+ /* need to generate zlp in reply or take data */
+ /* todo - deal with any data we might be sent? */
+ ret = s3c_hsotg_send_reply(hsotg, ep0, NULL, 0);
+ }
+ }
+
+ /* the request is either unhandlable, or is not formatted correctly
+ * so respond with a STALL for the status stage to indicate failure.
+ */
+
+ if (ret < 0) {
+ u32 reg;
+ u32 ctrl;
+
+ dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in);
+ reg = (ep0->dir_in) ? S3C_DIEPCTL0 : S3C_DOEPCTL0;
+
+ /* S3C_DxEPCTL_Stall will be cleared by EP once it has
+ * taken effect, so no need to clear later. */
+
+ ctrl = readl(hsotg->regs + reg);
+ ctrl |= S3C_DxEPCTL_Stall;
+ ctrl |= S3C_DxEPCTL_CNAK;
+ writel(ctrl, hsotg->regs + reg);
+
+ dev_dbg(hsotg->dev,
+ "writen DxEPCTL=0x%08x to %08x (DxEPCTL=0x%08x)\n",
+ ctrl, reg, readl(hsotg->regs + reg));
+
+ /* don't belive we need to anything more to get the EP
+ * to reply with a STALL packet */
+ }
+}
+
+static void s3c_hsotg_enqueue_setup(struct s3c_hsotg *hsotg);
+
+/**
+ * s3c_hsotg_complete_setup - completion of a setup transfer
+ * @ep: The endpoint the request was on.
+ * @req: The request completed.
+ *
+ * Called on completion of any requests the driver itself submitted for
+ * EP0 setup packets
+ */
+static void s3c_hsotg_complete_setup(struct usb_ep *ep,
+ struct usb_request *req)
+{
+ struct s3c_hsotg_ep *hs_ep = our_ep(ep);
+ struct s3c_hsotg *hsotg = hs_ep->parent;
+
+ if (req->status < 0) {
+ dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status);
+ return;
+ }
+
+ if (req->actual == 0)
+ s3c_hsotg_enqueue_setup(hsotg);
+ else
+ s3c_hsotg_process_control(hsotg, req->buf);
+}
+
+/**
+ * s3c_hsotg_enqueue_setup - start a request for EP0 packets
+ * @hsotg: The device state.
+ *
+ * Enqueue a request on EP0 if necessary to received any SETUP packets
+ * received from the host.
+ */
+static void s3c_hsotg_enqueue_setup(struct s3c_hsotg *hsotg)
+{
+ struct usb_request *req = hsotg->ctrl_req;
+ struct s3c_hsotg_req *hs_req = our_req(req);
+ int ret;
+
+ dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__);
+
+ req->zero = 0;
+ req->length = 8;
+ req->buf = hsotg->ctrl_buff;
+ req->complete = s3c_hsotg_complete_setup;
+
+ if (!list_empty(&hs_req->queue)) {
+ dev_dbg(hsotg->dev, "%s already queued???\n", __func__);
+ return;
+ }
+
+ hsotg->eps[0].dir_in = 0;
+
+ ret = s3c_hsotg_ep_queue(&hsotg->eps[0].ep, req, GFP_ATOMIC);
+ if (ret < 0) {
+ dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret);
+ /* Don't think there's much we can do other than watch the
+ * driver fail. */
+ }
+}
+
+/**
+ * get_ep_head - return the first request on the endpoint
+ * @hs_ep: The controller endpoint to get
+ *
+ * Get the first request on the endpoint.
+*/
+static struct s3c_hsotg_req *get_ep_head(struct s3c_hsotg_ep *hs_ep)
+{
+ if (list_empty(&hs_ep->queue))
+ return NULL;
+
+ return list_first_entry(&hs_ep->queue, struct s3c_hsotg_req, queue);
+}
+
+/**
+ * s3c_hsotg_complete_request - complete a request given to us
+ * @hsotg: The device state.
+ * @hs_ep: The endpoint the request was on.
+ * @hs_req: The request to complete.
+ * @result: The result code (0 => Ok, otherwise errno)
+ *
+ * The given request has finished, so call the necessary completion
+ * if it has one and then look to see if we can start a new request
+ * on the endpoint.
+ *
+ * Note, expects the ep to already be locked as appropriate.
+*/
+static void s3c_hsotg_complete_request(struct s3c_hsotg *hsotg,
+ struct s3c_hsotg_ep *hs_ep,
+ struct s3c_hsotg_req *hs_req,
+ int result)
+{
+ bool restart;
+
+ if (!hs_req) {
+ dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__);
+ return;
+ }
+
+ dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n",
+ hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete);
+
+ /* only replace the status if we've not already set an error
+ * from a previous transaction */
+
+ if (hs_req->req.status == -EINPROGRESS)
+ hs_req->req.status = result;
+
+ hs_ep->req = NULL;
+ list_del_init(&hs_req->queue);
+
+ if (using_dma(hsotg))
+ s3c_hsotg_unmap_dma(hsotg, hs_ep, hs_req);
+
+ /* call the complete request with the locks off, just in case the
+ * request tries to queue more work for this endpoint. */
+
+ if (hs_req->req.complete) {
+ spin_unlock(&hs_ep->lock);
+ hs_req->req.complete(&hs_ep->ep, &hs_req->req);
+ spin_lock(&hs_ep->lock);
+ }
+
+ /* Look to see if there is anything else to do. Note, the completion
+ * of the previous request may have caused a new request to be started
+ * so be careful when doing this. */
+
+ if (!hs_ep->req && result >= 0) {
+ restart = !list_empty(&hs_ep->queue);
+ if (restart) {
+ hs_req = get_ep_head(hs_ep);
+ s3c_hsotg_start_req(hsotg, hs_ep, hs_req, false);
+ }
+ }
+}
+
+/**
+ * s3c_hsotg_complete_request_lock - complete a request given to us (locked)
+ * @hsotg: The device state.
+ * @hs_ep: The endpoint the request was on.
+ * @hs_req: The request to complete.
+ * @result: The result code (0 => Ok, otherwise errno)
+ *
+ * See s3c_hsotg_complete_request(), but called with the endpoint's
+ * lock held.
+*/
+static void s3c_hsotg_complete_request_lock(struct s3c_hsotg *hsotg,
+ struct s3c_hsotg_ep *hs_ep,
+ struct s3c_hsotg_req *hs_req,
+ int result)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&hs_ep->lock, flags);
+ s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, result);
+ spin_unlock_irqrestore(&hs_ep->lock, flags);
+}
+
+/**
+ * s3c_hsotg_rx_data - receive data from the FIFO for an endpoint
+ * @hsotg: The device state.
+ * @ep_idx: The endpoint index for the data
+ * @size: The size of data in the fifo, in bytes
+ *
+ * The FIFO status shows there is data to read from the FIFO for a given
+ * endpoint, so sort out whether we need to read the data into a request
+ * that has been made for that endpoint.
+ */
+static void s3c_hsotg_rx_data(struct s3c_hsotg *hsotg, int ep_idx, int size)
+{
+ struct s3c_hsotg_ep *hs_ep = &hsotg->eps[ep_idx];
+ struct s3c_hsotg_req *hs_req = hs_ep->req;
+ void __iomem *fifo = hsotg->regs + S3C_EPFIFO(ep_idx);
+ int to_read;
+ int max_req;
+ int read_ptr;
+
+ if (!hs_req) {
+ u32 epctl = readl(hsotg->regs + S3C_DOEPCTL(ep_idx));
+ int ptr;
+
+ dev_warn(hsotg->dev,
+ "%s: FIFO %d bytes on ep%d but no req (DxEPCTl=0x%08x)\n",
+ __func__, size, ep_idx, epctl);
+
+ /* dump the data from the FIFO, we've nothing we can do */
+ for (ptr = 0; ptr < size; ptr += 4)
+ (void)readl(fifo);
+
+ return;
+ }
+
+ spin_lock(&hs_ep->lock);
+
+ to_read = size;
+ read_ptr = hs_req->req.actual;
+ max_req = hs_req->req.length - read_ptr;
+
+ if (to_read > max_req) {
+ /* more data appeared than we where willing
+ * to deal with in this request.
+ */
+
+ /* currently we don't deal this */
+ WARN_ON_ONCE(1);
+ }
+
+ dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n",
+ __func__, to_read, max_req, read_ptr, hs_req->req.length);
+
+ hs_ep->total_data += to_read;
+ hs_req->req.actual += to_read;
+ to_read = DIV_ROUND_UP(to_read, 4);
+
+ /* note, we might over-write the buffer end by 3 bytes depending on
+ * alignment of the data. */
+ readsl(fifo, hs_req->req.buf + read_ptr, to_read);
+
+ spin_unlock(&hs_ep->lock);
+}
+
+/**
+ * s3c_hsotg_send_zlp - send zero-length packet on control endpoint
+ * @hsotg: The device instance
+ * @req: The request currently on this endpoint
+ *
+ * Generate a zero-length IN packet request for terminating a SETUP
+ * transaction.
+ *
+ * Note, since we don't write any data to the TxFIFO, then it is
+ * currently belived that we do not need to wait for any space in
+ * the TxFIFO.
+ */
+static void s3c_hsotg_send_zlp(struct s3c_hsotg *hsotg,
+ struct s3c_hsotg_req *req)
+{
+ u32 ctrl;
+
+ if (!req) {
+ dev_warn(hsotg->dev, "%s: no request?\n", __func__);
+ return;
+ }
+
+ if (req->req.length == 0) {
+ hsotg->eps[0].sent_zlp = 1;
+ s3c_hsotg_enqueue_setup(hsotg);
+ return;
+ }
+
+ hsotg->eps[0].dir_in = 1;
+ hsotg->eps[0].sent_zlp = 1;
+
+ dev_dbg(hsotg->dev, "sending zero-length packet\n");
+
+ /* issue a zero-sized packet to terminate this */
+ writel(S3C_DxEPTSIZ_MC(1) | S3C_DxEPTSIZ_PktCnt(1) |
+ S3C_DxEPTSIZ_XferSize(0), hsotg->regs + S3C_DIEPTSIZ(0));
+
+ ctrl = readl(hsotg->regs + S3C_DIEPCTL0);
+ ctrl |= S3C_DxEPCTL_CNAK; /* clear NAK set by core */
+ ctrl |= S3C_DxEPCTL_EPEna; /* ensure ep enabled */
+ ctrl |= S3C_DxEPCTL_USBActEp;
+ writel(ctrl, hsotg->regs + S3C_DIEPCTL0);
+}
+
+/**
+ * s3c_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
+ * @hsotg: The device instance
+ * @epnum: The endpoint received from
+ * @was_setup: Set if processing a SetupDone event.
+ *
+ * The RXFIFO has delivered an OutDone event, which means that the data
+ * transfer for an OUT endpoint has been completed, either by a short
+ * packet or by the finish of a transfer.
+*/
+static void s3c_hsotg_handle_outdone(struct s3c_hsotg *hsotg,
+ int epnum, bool was_setup)
+{
+ struct s3c_hsotg_ep *hs_ep = &hsotg->eps[epnum];
+ struct s3c_hsotg_req *hs_req = hs_ep->req;
+ struct usb_request *req = &hs_req->req;
+ int result = 0;
+
+ if (!hs_req) {
+ dev_dbg(hsotg->dev, "%s: no request active\n", __func__);
+ return;
+ }
+
+ if (using_dma(hsotg)) {
+ u32 epsize = readl(hsotg->regs + S3C_DOEPTSIZ(epnum));
+ unsigned size_done;
+ unsigned size_left;
+
+ /* Calculate the size of the transfer by checking how much
+ * is left in the endpoint size register and then working it
+ * out from the amount we loaded for the transfer.
+ *
+ * We need to do this as DMA pointers are always 32bit aligned
+ * so may overshoot/undershoot the transfer.
+ */
+
+ size_left = S3C_DxEPTSIZ_XferSize_GET(epsize);
+
+ size_done = hs_ep->size_loaded - size_left;
+ size_done += hs_ep->last_load;
+
+ req->actual = size_done;
+ }
+
+ if (req->actual < req->length && req->short_not_ok) {
+ dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n",
+ __func__, req->actual, req->length);
+
+ /* todo - what should we return here? there's no one else
+ * even bothering to check the status. */
+ }
+
+ if (epnum == 0) {
+ if (!was_setup && req->complete != s3c_hsotg_complete_setup)
+ s3c_hsotg_send_zlp(hsotg, hs_req);
+ }
+
+ s3c_hsotg_complete_request_lock(hsotg, hs_ep, hs_req, result);
+}
+
+/**
+ * s3c_hsotg_read_frameno - read current frame number
+ * @hsotg: The device instance
+ *
+ * Return the current frame number
+*/
+static u32 s3c_hsotg_read_frameno(struct s3c_hsotg *hsotg)
+{
+ u32 dsts;
+
+ dsts = readl(hsotg->regs + S3C_DSTS);
+ dsts &= S3C_DSTS_SOFFN_MASK;
+ dsts >>= S3C_DSTS_SOFFN_SHIFT;
+
+ return dsts;
+}
+
+/**
+ * s3c_hsotg_handle_rx - RX FIFO has data
+ * @hsotg: The device instance
+ *
+ * The IRQ handler has detected that the RX FIFO has some data in it
+ * that requires processing, so find out what is in there and do the
+ * appropriate read.
+ *
+ * The RXFIFO is a true FIFO, the packets comming out are still in packet
+ * chunks, so if you have x packets received on an endpoint you'll get x
+ * FIFO events delivered, each with a packet's worth of data in it.
+ *
+ * When using DMA, we should not be processing events from the RXFIFO
+ * as the actual data should be sent to the memory directly and we turn
+ * on the completion interrupts to get notifications of transfer completion.
+ */
+void s3c_hsotg_handle_rx(struct s3c_hsotg *hsotg)
+{
+ u32 grxstsr = readl(hsotg->regs + S3C_GRXSTSP);
+ u32 epnum, status, size;
+
+ WARN_ON(using_dma(hsotg));
+
+ epnum = grxstsr & S3C_GRXSTS_EPNum_MASK;
+ status = grxstsr & S3C_GRXSTS_PktSts_MASK;
+
+ size = grxstsr & S3C_GRXSTS_ByteCnt_MASK;
+ size >>= S3C_GRXSTS_ByteCnt_SHIFT;
+
+ if (1)
+ dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n",
+ __func__, grxstsr, size, epnum);
+
+#define __status(x) ((x) >> S3C_GRXSTS_PktSts_SHIFT)
+
+ switch (status >> S3C_GRXSTS_PktSts_SHIFT) {
+ case __status(S3C_GRXSTS_PktSts_GlobalOutNAK):
+ dev_dbg(hsotg->dev, "GlobalOutNAK\n");
+ break;
+
+ case __status(S3C_GRXSTS_PktSts_OutDone):
+ dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n",
+ s3c_hsotg_read_frameno(hsotg));
+
+ if (!using_dma(hsotg))
+ s3c_hsotg_handle_outdone(hsotg, epnum, false);
+ break;
+
+ case __status(S3C_GRXSTS_PktSts_SetupDone):
+ dev_dbg(hsotg->dev,
+ "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
+ s3c_hsotg_read_frameno(hsotg),
+ readl(hsotg->regs + S3C_DOEPCTL(0)));
+
+ s3c_hsotg_handle_outdone(hsotg, epnum, true);
+ break;
+
+ case __status(S3C_GRXSTS_PktSts_OutRX):
+ s3c_hsotg_rx_data(hsotg, epnum, size);
+ break;
+
+ case __status(S3C_GRXSTS_PktSts_SetupRX):
+ dev_dbg(hsotg->dev,
+ "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
+ s3c_hsotg_read_frameno(hsotg),
+ readl(hsotg->regs + S3C_DOEPCTL(0)));
+
+ s3c_hsotg_rx_data(hsotg, epnum, size);
+ break;
+
+ default:
+ dev_warn(hsotg->dev, "%s: unknown status %08x\n",
+ __func__, grxstsr);
+
+ s3c_hsotg_dump(hsotg);
+ break;
+ }
+}
+
+/**
+ * s3c_hsotg_ep0_mps - turn max packet size into register setting
+ * @mps: The maximum packet size in bytes.
+*/
+static u32 s3c_hsotg_ep0_mps(unsigned int mps)
+{
+ switch (mps) {
+ case 64:
+ return S3C_D0EPCTL_MPS_64;
+ case 32:
+ return S3C_D0EPCTL_MPS_32;
+ case 16:
+ return S3C_D0EPCTL_MPS_16;
+ case 8:
+ return S3C_D0EPCTL_MPS_8;
+ }
+
+ /* bad max packet size, warn and return invalid result */
+ WARN_ON(1);
+ return (u32)-1;
+}
+
+/**
+ * s3c_hsotg_set_ep_maxpacket - set endpoint's max-packet field
+ * @hsotg: The driver state.
+ * @ep: The index number of the endpoint
+ * @mps: The maximum packet size in bytes
+ *
+ * Configure the maximum packet size for the given endpoint, updating
+ * the hardware control registers to reflect this.
+ */
+static void s3c_hsotg_set_ep_maxpacket(struct s3c_hsotg *hsotg,
+ unsigned int ep, unsigned int mps)
+{
+ struct s3c_hsotg_ep *hs_ep = &hsotg->eps[ep];
+ void __iomem *regs = hsotg->regs;
+ u32 mpsval;
+ u32 reg;
+
+ if (ep == 0) {
+ /* EP0 is a special case */
+ mpsval = s3c_hsotg_ep0_mps(mps);
+ if (mpsval > 3)
+ goto bad_mps;
+ } else {
+ if (mps >= S3C_DxEPCTL_MPS_LIMIT+1)
+ goto bad_mps;
+
+ mpsval = mps;
+ }
+
+ hs_ep->ep.maxpacket = mps;
+
+ /* update both the in and out endpoint controldir_ registers, even
+ * if one of the directions may not be in use. */
+
+ reg = readl(regs + S3C_DIEPCTL(ep));
+ reg &= ~S3C_DxEPCTL_MPS_MASK;
+ reg |= mpsval;
+ writel(reg, regs + S3C_DIEPCTL(ep));
+
+ reg = readl(regs + S3C_DOEPCTL(ep));
+ reg &= ~S3C_DxEPCTL_MPS_MASK;
+ reg |= mpsval;
+ writel(reg, regs + S3C_DOEPCTL(ep));
+
+ return;
+
+bad_mps:
+ dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps);
+}
+
+
+/**
+ * s3c_hsotg_trytx - check to see if anything needs transmitting
+ * @hsotg: The driver state
+ * @hs_ep: The driver endpoint to check.
+ *
+ * Check to see if there is a request that has data to send, and if so
+ * make an attempt to write data into the FIFO.
+ */
+static int s3c_hsotg_trytx(struct s3c_hsotg *hsotg,
+ struct s3c_hsotg_ep *hs_ep)
+{
+ struct s3c_hsotg_req *hs_req = hs_ep->req;
+
+ if (!hs_ep->dir_in || !hs_req)
+ return 0;
+
+ if (hs_req->req.actual < hs_req->req.length) {
+ dev_dbg(hsotg->dev, "trying to write more for ep%d\n",
+ hs_ep->index);
+ return s3c_hsotg_write_fifo(hsotg, hs_ep, hs_req);
+ }
+
+ return 0;
+}
+
+/**
+ * s3c_hsotg_complete_in - complete IN transfer
+ * @hsotg: The device state.
+ * @hs_ep: The endpoint that has just completed.
+ *
+ * An IN transfer has been completed, update the transfer's state and then
+ * call the relevant completion routines.
+ */
+static void s3c_hsotg_complete_in(struct s3c_hsotg *hsotg,
+ struct s3c_hsotg_ep *hs_ep)
+{
+ struct s3c_hsotg_req *hs_req = hs_ep->req;
+ u32 epsize = readl(hsotg->regs + S3C_DIEPTSIZ(hs_ep->index));
+ int size_left, size_done;
+
+ if (!hs_req) {
+ dev_dbg(hsotg->dev, "XferCompl but no req\n");
+ return;
+ }
+
+ /* Calculate the size of the transfer by checking how much is left
+ * in the endpoint size register and then working it out from
+ * the amount we loaded for the transfer.
+ *
+ * We do this even for DMA, as the transfer may have incremented
+ * past the end of the buffer (DMA transfers are always 32bit
+ * aligned).
+ */
+
+ size_left = S3C_DxEPTSIZ_XferSize_GET(epsize);
+
+ size_done = hs_ep->size_loaded - size_left;
+ size_done += hs_ep->last_load;
+
+ if (hs_req->req.actual != size_done)
+ dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n",
+ __func__, hs_req->req.actual, size_done);
+
+ hs_req->req.actual = size_done;
+
+ /* if we did all of the transfer, and there is more data left
+ * around, then try restarting the rest of the request */
+
+ if (!size_left && hs_req->req.actual < hs_req->req.length) {
+ dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__);
+ s3c_hsotg_start_req(hsotg, hs_ep, hs_req, true);
+ } else
+ s3c_hsotg_complete_request_lock(hsotg, hs_ep, hs_req, 0);
+}
+
+/**
+ * s3c_hsotg_epint - handle an in/out endpoint interrupt
+ * @hsotg: The driver state
+ * @idx: The index for the endpoint (0..15)
+ * @dir_in: Set if this is an IN endpoint
+ *
+ * Process and clear any interrupt pending for an individual endpoint
+*/
+static void s3c_hsotg_epint(struct s3c_hsotg *hsotg, unsigned int idx,
+ int dir_in)
+{
+ struct s3c_hsotg_ep *hs_ep = &hsotg->eps[idx];
+ u32 epint_reg = dir_in ? S3C_DIEPINT(idx) : S3C_DOEPINT(idx);
+ u32 epctl_reg = dir_in ? S3C_DIEPCTL(idx) : S3C_DOEPCTL(idx);
+ u32 epsiz_reg = dir_in ? S3C_DIEPTSIZ(idx) : S3C_DOEPTSIZ(idx);
+ u32 ints;
+ u32 clear = 0;
+
+ ints = readl(hsotg->regs + epint_reg);
+
+ dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
+ __func__, idx, dir_in ? "in" : "out", ints);
+
+ if (ints & S3C_DxEPINT_XferCompl) {
+ dev_dbg(hsotg->dev,
+ "%s: XferCompl: DxEPCTL=0x%08x, DxEPTSIZ=%08x\n",
+ __func__, readl(hsotg->regs + epctl_reg),
+ readl(hsotg->regs + epsiz_reg));
+
+ /* we get OutDone from the FIFO, so we only need to look
+ * at completing IN requests here */
+ if (dir_in) {
+ s3c_hsotg_complete_in(hsotg, hs_ep);
+
+ if (idx == 0)
+ s3c_hsotg_enqueue_setup(hsotg);
+ } else if (using_dma(hsotg)) {
+ /* We're using DMA, we need to fire an OutDone here
+ * as we ignore the RXFIFO. */
+
+ s3c_hsotg_handle_outdone(hsotg, idx, false);
+ }
+
+ clear |= S3C_DxEPINT_XferCompl;
+ }
+
+ if (ints & S3C_DxEPINT_EPDisbld) {
+ dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
+ clear |= S3C_DxEPINT_EPDisbld;
+ }
+
+ if (ints & S3C_DxEPINT_AHBErr) {
+ dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__);
+ clear |= S3C_DxEPINT_AHBErr;
+ }
+
+ if (ints & S3C_DxEPINT_Setup) { /* Setup or Timeout */
+ dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__);
+
+ if (using_dma(hsotg) && idx == 0) {
+ /* this is the notification we've received a
+ * setup packet. In non-DMA mode we'd get this
+ * from the RXFIFO, instead we need to process
+ * the setup here. */
+
+ if (dir_in)
+ WARN_ON_ONCE(1);
+ else
+ s3c_hsotg_handle_outdone(hsotg, 0, true);
+ }
+
+ clear |= S3C_DxEPINT_Setup;
+ }
+
+ if (ints & S3C_DxEPINT_Back2BackSetup) {
+ dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
+ clear |= S3C_DxEPINT_Back2BackSetup;
+ }
+
+ if (dir_in) {
+ /* not sure if this is important, but we'll clear it anyway
+ */
+ if (ints & S3C_DIEPMSK_INTknTXFEmpMsk) {
+ dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n",
+ __func__, idx);
+ clear |= S3C_DIEPMSK_INTknTXFEmpMsk;
+ }
+
+ /* this probably means something bad is happening */
+ if (ints & S3C_DIEPMSK_INTknEPMisMsk) {
+ dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n",
+ __func__, idx);
+ clear |= S3C_DIEPMSK_INTknEPMisMsk;
+ }
+ }
+
+ writel(clear, hsotg->regs + epint_reg);
+}
+
+/**
+ * s3c_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
+ * @hsotg: The device state.
+ *
+ * Handle updating the device settings after the enumeration phase has
+ * been completed.
+*/
+static void s3c_hsotg_irq_enumdone(struct s3c_hsotg *hsotg)
+{
+ u32 dsts = readl(hsotg->regs + S3C_DSTS);
+ int ep0_mps = 0, ep_mps;
+
+ /* This should signal the finish of the enumeration phase
+ * of the USB handshaking, so we should now know what rate
+ * we connected at. */
+
+ dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts);
+
+ /* note, since we're limited by the size of transfer on EP0, and
+ * it seems IN transfers must be a even number of packets we do
+ * not advertise a 64byte MPS on EP0. */
+
+ /* catch both EnumSpd_FS and EnumSpd_FS48 */
+ switch (dsts & S3C_DSTS_EnumSpd_MASK) {
+ case S3C_DSTS_EnumSpd_FS:
+ case S3C_DSTS_EnumSpd_FS48:
+ hsotg->gadget.speed = USB_SPEED_FULL;
+ dev_info(hsotg->dev, "new device is full-speed\n");
+
+ ep0_mps = EP0_MPS_LIMIT;
+ ep_mps = 64;
+ break;
+
+ case S3C_DSTS_EnumSpd_HS:
+ dev_info(hsotg->dev, "new device is high-speed\n");
+ hsotg->gadget.speed = USB_SPEED_HIGH;
+
+ ep0_mps = EP0_MPS_LIMIT;
+ ep_mps = 512;
+ break;
+
+ case S3C_DSTS_EnumSpd_LS:
+ hsotg->gadget.speed = USB_SPEED_LOW;
+ dev_info(hsotg->dev, "new device is low-speed\n");
+
+ /* note, we don't actually support LS in this driver at the
+ * moment, and the documentation seems to imply that it isn't
+ * supported by the PHYs on some of the devices.
+ */
+ break;
+ }
+
+ /* we should now know the maximum packet size for an
+ * endpoint, so set the endpoints to a default value. */
+
+ if (ep0_mps) {
+ int i;
+ s3c_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps);
+ for (i = 1; i < S3C_HSOTG_EPS; i++)
+ s3c_hsotg_set_ep_maxpacket(hsotg, i, ep_mps);
+ }
+
+ /* ensure after enumeration our EP0 is active */
+
+ s3c_hsotg_enqueue_setup(hsotg);
+
+ dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
+ readl(hsotg->regs + S3C_DIEPCTL0),
+ readl(hsotg->regs + S3C_DOEPCTL0));
+}
+
+/**
+ * kill_all_requests - remove all requests from the endpoint's queue
+ * @hsotg: The device state.
+ * @ep: The endpoint the requests may be on.
+ * @result: The result code to use.
+ * @force: Force removal of any current requests
+ *
+ * Go through the requests on the given endpoint and mark them
+ * completed with the given result code.
+ */
+static void kill_all_requests(struct s3c_hsotg *hsotg,
+ struct s3c_hsotg_ep *ep,
+ int result, bool force)
+{
+ struct s3c_hsotg_req *req, *treq;
+ unsigned long flags;
+
+ spin_lock_irqsave(&ep->lock, flags);
+
+ list_for_each_entry_safe(req, treq, &ep->queue, queue) {
+ /* currently, we can't do much about an already
+ * running request on an in endpoint */
+
+ if (ep->req == req && ep->dir_in && !force)
+ continue;
+
+ s3c_hsotg_complete_request(hsotg, ep, req,
+ result);
+ }
+
+ spin_unlock_irqrestore(&ep->lock, flags);
+}
+
+#define call_gadget(_hs, _entry) \
+ if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \
+ (_hs)->driver && (_hs)->driver->_entry) \
+ (_hs)->driver->_entry(&(_hs)->gadget);
+
+/**
+ * s3c_hsotg_disconnect_irq - disconnect irq service
+ * @hsotg: The device state.
+ *
+ * A disconnect IRQ has been received, meaning that the host has
+ * lost contact with the bus. Remove all current transactions
+ * and signal the gadget driver that this has happened.
+*/
+static void s3c_hsotg_disconnect_irq(struct s3c_hsotg *hsotg)
+{
+ unsigned ep;
+
+ for (ep = 0; ep < S3C_HSOTG_EPS; ep++)
+ kill_all_requests(hsotg, &hsotg->eps[ep], -ESHUTDOWN, true);
+
+ call_gadget(hsotg, disconnect);
+}
+
+/**
+ * s3c_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
+ * @hsotg: The device state:
+ * @periodic: True if this is a periodic FIFO interrupt
+ */
+static void s3c_hsotg_irq_fifoempty(struct s3c_hsotg *hsotg, bool periodic)
+{
+ struct s3c_hsotg_ep *ep;
+ int epno, ret;
+
+ /* look through for any more data to transmit */
+
+ for (epno = 0; epno < S3C_HSOTG_EPS; epno++) {
+ ep = &hsotg->eps[epno];
+
+ if (!ep->dir_in)
+ continue;
+
+ if ((periodic && !ep->periodic) ||
+ (!periodic && ep->periodic))
+ continue;
+
+ ret = s3c_hsotg_trytx(hsotg, ep);
+ if (ret < 0)
+ break;
+ }
+}
+
+static struct s3c_hsotg *our_hsotg;
+
+/* IRQ flags which will trigger a retry around the IRQ loop */
+#define IRQ_RETRY_MASK (S3C_GINTSTS_NPTxFEmp | \
+ S3C_GINTSTS_PTxFEmp | \
+ S3C_GINTSTS_RxFLvl)
+
+/**
+ * s3c_hsotg_irq - handle device interrupt
+ * @irq: The IRQ number triggered
+ * @pw: The pw value when registered the handler.
+ */
+static irqreturn_t s3c_hsotg_irq(int irq, void *pw)
+{
+ struct s3c_hsotg *hsotg = pw;
+ int retry_count = 8;
+ u32 gintsts;
+ u32 gintmsk;
+
+irq_retry:
+ gintsts = readl(hsotg->regs + S3C_GINTSTS);
+ gintmsk = readl(hsotg->regs + S3C_GINTMSK);
+
+ dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
+ __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
+
+ gintsts &= gintmsk;
+
+ if (gintsts & S3C_GINTSTS_OTGInt) {
+ u32 otgint = readl(hsotg->regs + S3C_GOTGINT);
+
+ dev_info(hsotg->dev, "OTGInt: %08x\n", otgint);
+
+ writel(otgint, hsotg->regs + S3C_GOTGINT);
+ writel(S3C_GINTSTS_OTGInt, hsotg->regs + S3C_GINTSTS);
+ }
+
+ if (gintsts & S3C_GINTSTS_DisconnInt) {
+ dev_dbg(hsotg->dev, "%s: DisconnInt\n", __func__);
+ writel(S3C_GINTSTS_DisconnInt, hsotg->regs + S3C_GINTSTS);
+
+ s3c_hsotg_disconnect_irq(hsotg);
+ }
+
+ if (gintsts & S3C_GINTSTS_SessReqInt) {
+ dev_dbg(hsotg->dev, "%s: SessReqInt\n", __func__);
+ writel(S3C_GINTSTS_SessReqInt, hsotg->regs + S3C_GINTSTS);
+ }
+
+ if (gintsts & S3C_GINTSTS_EnumDone) {
+ s3c_hsotg_irq_enumdone(hsotg);
+ writel(S3C_GINTSTS_EnumDone, hsotg->regs + S3C_GINTSTS);
+ }
+
+ if (gintsts & S3C_GINTSTS_ConIDStsChng) {
+ dev_dbg(hsotg->dev, "ConIDStsChg (DSTS=0x%08x, GOTCTL=%08x)\n",
+ readl(hsotg->regs + S3C_DSTS),
+ readl(hsotg->regs + S3C_GOTGCTL));
+
+ writel(S3C_GINTSTS_ConIDStsChng, hsotg->regs + S3C_GINTSTS);
+ }
+
+ if (gintsts & (S3C_GINTSTS_OEPInt | S3C_GINTSTS_IEPInt)) {
+ u32 daint = readl(hsotg->regs + S3C_DAINT);
+ u32 daint_out = daint >> S3C_DAINT_OutEP_SHIFT;
+ u32 daint_in = daint & ~(daint_out << S3C_DAINT_OutEP_SHIFT);
+ int ep;
+
+ dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint);
+
+ for (ep = 0; ep < 15 && daint_out; ep++, daint_out >>= 1) {
+ if (daint_out & 1)
+ s3c_hsotg_epint(hsotg, ep, 0);
+ }
+
+ for (ep = 0; ep < 15 && daint_in; ep++, daint_in >>= 1) {
+ if (daint_in & 1)
+ s3c_hsotg_epint(hsotg, ep, 1);
+ }
+
+ writel(daint, hsotg->regs + S3C_DAINT);
+ writel(gintsts & (S3C_GINTSTS_OEPInt | S3C_GINTSTS_IEPInt),
+ hsotg->regs + S3C_GINTSTS);
+ }
+
+ if (gintsts & S3C_GINTSTS_USBRst) {
+ dev_info(hsotg->dev, "%s: USBRst\n", __func__);
+ dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
+ readl(hsotg->regs + S3C_GNPTXSTS));
+
+ kill_all_requests(hsotg, &hsotg->eps[0], -ECONNRESET, true);
+
+ /* it seems after a reset we can end up with a situation
+ * where the TXFIFO still has data in it... try flushing
+ * it to remove anything that may still be in it.
+ */
+
+ if (1) {
+ writel(S3C_GRSTCTL_TxFNum(0) | S3C_GRSTCTL_TxFFlsh,
+ hsotg->regs + S3C_GRSTCTL);
+
+ dev_info(hsotg->dev, "GNPTXSTS=%08x\n",
+ readl(hsotg->regs + S3C_GNPTXSTS));
+ }
+
+ s3c_hsotg_enqueue_setup(hsotg);
+
+ writel(S3C_GINTSTS_USBRst, hsotg->regs + S3C_GINTSTS);
+ }
+
+ /* check both FIFOs */
+
+ if (gintsts & S3C_GINTSTS_NPTxFEmp) {
+ dev_dbg(hsotg->dev, "NPTxFEmp\n");
+
+ /* Disable the interrupt to stop it happening again
+ * unless one of these endpoint routines decides that
+ * it needs re-enabling */
+
+ s3c_hsotg_disable_gsint(hsotg, S3C_GINTSTS_NPTxFEmp);
+ s3c_hsotg_irq_fifoempty(hsotg, false);
+
+ writel(S3C_GINTSTS_NPTxFEmp, hsotg->regs + S3C_GINTSTS);
+ }
+
+ if (gintsts & S3C_GINTSTS_PTxFEmp) {
+ dev_dbg(hsotg->dev, "PTxFEmp\n");
+
+ /* See note in S3C_GINTSTS_NPTxFEmp */
+
+ s3c_hsotg_disable_gsint(hsotg, S3C_GINTSTS_PTxFEmp);
+ s3c_hsotg_irq_fifoempty(hsotg, true);
+
+ writel(S3C_GINTSTS_PTxFEmp, hsotg->regs + S3C_GINTSTS);
+ }
+
+ if (gintsts & S3C_GINTSTS_RxFLvl) {
+ /* note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
+ * we need to retry s3c_hsotg_handle_rx if this is still
+ * set. */
+
+ s3c_hsotg_handle_rx(hsotg);
+ writel(S3C_GINTSTS_RxFLvl, hsotg->regs + S3C_GINTSTS);
+ }
+
+ if (gintsts & S3C_GINTSTS_ModeMis) {
+ dev_warn(hsotg->dev, "warning, mode mismatch triggered\n");
+ writel(S3C_GINTSTS_ModeMis, hsotg->regs + S3C_GINTSTS);
+ }
+
+ if (gintsts & S3C_GINTSTS_USBSusp) {
+ dev_info(hsotg->dev, "S3C_GINTSTS_USBSusp\n");
+ writel(S3C_GINTSTS_USBSusp, hsotg->regs + S3C_GINTSTS);
+
+ call_gadget(hsotg, suspend);
+ }
+
+ if (gintsts & S3C_GINTSTS_WkUpInt) {
+ dev_info(hsotg->dev, "S3C_GINTSTS_WkUpIn\n");
+ writel(S3C_GINTSTS_WkUpInt, hsotg->regs + S3C_GINTSTS);
+
+ call_gadget(hsotg, resume);
+ }
+
+ if (gintsts & S3C_GINTSTS_ErlySusp) {
+ dev_dbg(hsotg->dev, "S3C_GINTSTS_ErlySusp\n");
+ writel(S3C_GINTSTS_ErlySusp, hsotg->regs + S3C_GINTSTS);
+ }
+
+ /* these next two seem to crop-up occasionally causing the core
+ * to shutdown the USB transfer, so try clearing them and logging
+ * the occurence. */
+
+ if (gintsts & S3C_GINTSTS_GOUTNakEff) {
+ dev_info(hsotg->dev, "GOUTNakEff triggered\n");
+
+ s3c_hsotg_dump(hsotg);
+
+ writel(S3C_DCTL_CGOUTNak, hsotg->regs + S3C_DCTL);
+ writel(S3C_GINTSTS_GOUTNakEff, hsotg->regs + S3C_GINTSTS);
+ }
+
+ if (gintsts & S3C_GINTSTS_GINNakEff) {
+ dev_info(hsotg->dev, "GINNakEff triggered\n");
+
+ s3c_hsotg_dump(hsotg);
+
+ writel(S3C_DCTL_CGNPInNAK, hsotg->regs + S3C_DCTL);
+ writel(S3C_GINTSTS_GINNakEff, hsotg->regs + S3C_GINTSTS);
+ }
+
+ /* if we've had fifo events, we should try and go around the
+ * loop again to see if there's any point in returning yet. */
+
+ if (gintsts & IRQ_RETRY_MASK && --retry_count > 0)
+ goto irq_retry;
+
+ return IRQ_HANDLED;
+}
+
+/**
+ * s3c_hsotg_ep_enable - enable the given endpoint
+ * @ep: The USB endpint to configure
+ * @desc: The USB endpoint descriptor to configure with.
+ *
+ * This is called from the USB gadget code's usb_ep_enable().
+*/
+static int s3c_hsotg_ep_enable(struct usb_ep *ep,
+ const struct usb_endpoint_descriptor *desc)
+{
+ struct s3c_hsotg_ep *hs_ep = our_ep(ep);
+ struct s3c_hsotg *hsotg = hs_ep->parent;
+ unsigned long flags;
+ int index = hs_ep->index;
+ u32 epctrl_reg;
+ u32 epctrl;
+ u32 mps;
+ int dir_in;
+
+ dev_dbg(hsotg->dev,
+ "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
+ __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes,
+ desc->wMaxPacketSize, desc->bInterval);
+
+ /* not to be called for EP0 */
+ WARN_ON(index == 0);
+
+ dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0;
+ if (dir_in != hs_ep->dir_in) {
+ dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__);
+ return -EINVAL;
+ }
+
+ mps = le16_to_cpu(desc->wMaxPacketSize);
+
+ /* note, we handle this here instead of s3c_hsotg_set_ep_maxpacket */
+
+ epctrl_reg = dir_in ? S3C_DIEPCTL(index) : S3C_DOEPCTL(index);
+ epctrl = readl(hsotg->regs + epctrl_reg);
+
+ dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
+ __func__, epctrl, epctrl_reg);
+
+ spin_lock_irqsave(&hs_ep->lock, flags);
+
+ epctrl &= ~(S3C_DxEPCTL_EPType_MASK | S3C_DxEPCTL_MPS_MASK);
+ epctrl |= S3C_DxEPCTL_MPS(mps);
+
+ /* mark the endpoint as active, otherwise the core may ignore
+ * transactions entirely for this endpoint */
+ epctrl |= S3C_DxEPCTL_USBActEp;
+
+ /* set the NAK status on the endpoint, otherwise we might try and
+ * do something with data that we've yet got a request to process
+ * since the RXFIFO will take data for an endpoint even if the
+ * size register hasn't been set.
+ */
+
+ epctrl |= S3C_DxEPCTL_SNAK;
+
+ /* update the endpoint state */
+ hs_ep->ep.maxpacket = mps;
+
+ /* default, set to non-periodic */
+ hs_ep->periodic = 0;
+
+ switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
+ case USB_ENDPOINT_XFER_ISOC:
+ dev_err(hsotg->dev, "no current ISOC support\n");
+ return -EINVAL;
+
+ case USB_ENDPOINT_XFER_BULK:
+ epctrl |= S3C_DxEPCTL_EPType_Bulk;
+ break;
+
+ case USB_ENDPOINT_XFER_INT:
+ if (dir_in) {
+ /* Allocate our TxFNum by simply using the index
+ * of the endpoint for the moment. We could do
+ * something better if the host indicates how
+ * many FIFOs we are expecting to use. */
+
+ hs_ep->periodic = 1;
+ epctrl |= S3C_DxEPCTL_TxFNum(index);
+ }
+
+ epctrl |= S3C_DxEPCTL_EPType_Intterupt;
+ break;
+
+ case USB_ENDPOINT_XFER_CONTROL:
+ epctrl |= S3C_DxEPCTL_EPType_Control;
+ break;
+ }
+
+ /* for non control endpoints, set PID to D0 */
+ if (index)
+ epctrl |= S3C_DxEPCTL_SetD0PID;
+
+ dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
+ __func__, epctrl);
+
+ writel(epctrl, hsotg->regs + epctrl_reg);
+ dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n",
+ __func__, readl(hsotg->regs + epctrl_reg));
+
+ /* enable the endpoint interrupt */
+ s3c_hsotg_ctrl_epint(hsotg, index, dir_in, 1);
+
+ spin_unlock_irqrestore(&hs_ep->lock, flags);
+ return 0;
+}
+
+static int s3c_hsotg_ep_disable(struct usb_ep *ep)
+{
+ struct s3c_hsotg_ep *hs_ep = our_ep(ep);
+ struct s3c_hsotg *hsotg = hs_ep->parent;
+ int dir_in = hs_ep->dir_in;
+ int index = hs_ep->index;
+ unsigned long flags;
+ u32 epctrl_reg;
+ u32 ctrl;
+
+ dev_info(hsotg->dev, "%s(ep %p)\n", __func__, ep);
+
+ if (ep == &hsotg->eps[0].ep) {
+ dev_err(hsotg->dev, "%s: called for ep0\n", __func__);
+ return -EINVAL;
+ }
+
+ epctrl_reg = dir_in ? S3C_DIEPCTL(index) : S3C_DOEPCTL(index);
+
+ /* terminate all requests with shutdown */
+ kill_all_requests(hsotg, hs_ep, -ESHUTDOWN, false);
+
+ spin_lock_irqsave(&hs_ep->lock, flags);
+
+ ctrl = readl(hsotg->regs + epctrl_reg);
+ ctrl &= ~S3C_DxEPCTL_EPEna;
+ ctrl &= ~S3C_DxEPCTL_USBActEp;
+ ctrl |= S3C_DxEPCTL_SNAK;
+
+ dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
+ writel(ctrl, hsotg->regs + epctrl_reg);
+
+ /* disable endpoint interrupts */
+ s3c_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0);
+
+ spin_unlock_irqrestore(&hs_ep->lock, flags);
+ return 0;
+}
+
+/**
+ * on_list - check request is on the given endpoint
+ * @ep: The endpoint to check.
+ * @test: The request to test if it is on the endpoint.
+*/
+static bool on_list(struct s3c_hsotg_ep *ep, struct s3c_hsotg_req *test)
+{
+ struct s3c_hsotg_req *req, *treq;
+
+ list_for_each_entry_safe(req, treq, &ep->queue, queue) {
+ if (req == test)
+ return true;
+ }
+
+ return false;
+}
+
+static int s3c_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req)
+{
+ struct s3c_hsotg_req *hs_req = our_req(req);
+ struct s3c_hsotg_ep *hs_ep = our_ep(ep);
+ struct s3c_hsotg *hs = hs_ep->parent;
+ unsigned long flags;
+
+ dev_info(hs->dev, "ep_dequeue(%p,%p)\n", ep, req);
+
+ if (hs_req == hs_ep->req) {
+ dev_dbg(hs->dev, "%s: already in progress\n", __func__);
+ return -EINPROGRESS;
+ }
+
+ spin_lock_irqsave(&hs_ep->lock, flags);
+
+ if (!on_list(hs_ep, hs_req)) {
+ spin_unlock_irqrestore(&hs_ep->lock, flags);
+ return -EINVAL;
+ }
+
+ s3c_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET);
+ spin_unlock_irqrestore(&hs_ep->lock, flags);
+
+ return 0;
+}
+
+static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value)
+{
+ struct s3c_hsotg_ep *hs_ep = our_ep(ep);
+ struct s3c_hsotg *hs = hs_ep->parent;
+ int index = hs_ep->index;
+ unsigned long irqflags;
+ u32 epreg;
+ u32 epctl;
+
+ dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value);
+
+ spin_lock_irqsave(&hs_ep->lock, irqflags);
+
+ /* write both IN and OUT control registers */
+
+ epreg = S3C_DIEPCTL(index);
+ epctl = readl(hs->regs + epreg);
+
+ if (value)
+ epctl |= S3C_DxEPCTL_Stall;
+ else
+ epctl &= ~S3C_DxEPCTL_Stall;
+
+ writel(epctl, hs->regs + epreg);
+
+ epreg = S3C_DOEPCTL(index);
+ epctl = readl(hs->regs + epreg);
+
+ if (value)
+ epctl |= S3C_DxEPCTL_Stall;
+ else
+ epctl &= ~S3C_DxEPCTL_Stall;
+
+ writel(epctl, hs->regs + epreg);
+
+ spin_unlock_irqrestore(&hs_ep->lock, irqflags);
+
+ return 0;
+}
+
+static struct usb_ep_ops s3c_hsotg_ep_ops = {
+ .enable = s3c_hsotg_ep_enable,
+ .disable = s3c_hsotg_ep_disable,
+ .alloc_request = s3c_hsotg_ep_alloc_request,
+ .free_request = s3c_hsotg_ep_free_request,
+ .queue = s3c_hsotg_ep_queue,
+ .dequeue = s3c_hsotg_ep_dequeue,
+ .set_halt = s3c_hsotg_ep_sethalt,
+ /* note, don't belive we have any call for the fifo routines */
+};
+
+/**
+ * s3c_hsotg_corereset - issue softreset to the core
+ * @hsotg: The device state
+ *
+ * Issue a soft reset to the core, and await the core finishing it.
+*/
+static int s3c_hsotg_corereset(struct s3c_hsotg *hsotg)
+{
+ int timeout;
+ u32 grstctl;
+
+ dev_dbg(hsotg->dev, "resetting core\n");
+
+ /* issue soft reset */
+ writel(S3C_GRSTCTL_CSftRst, hsotg->regs + S3C_GRSTCTL);
+
+ timeout = 1000;
+ do {
+ grstctl = readl(hsotg->regs + S3C_GRSTCTL);
+ } while (!(grstctl & S3C_GRSTCTL_CSftRst) && timeout-- > 0);
+
+ if (!grstctl & S3C_GRSTCTL_CSftRst) {
+ dev_err(hsotg->dev, "Failed to get CSftRst asserted\n");
+ return -EINVAL;
+ }
+
+ timeout = 1000;
+
+ while (1) {
+ u32 grstctl = readl(hsotg->regs + S3C_GRSTCTL);
+
+ if (timeout-- < 0) {
+ dev_info(hsotg->dev,
+ "%s: reset failed, GRSTCTL=%08x\n",
+ __func__, grstctl);
+ return -ETIMEDOUT;
+ }
+
+ if (grstctl & S3C_GRSTCTL_CSftRst)
+ continue;
+
+ if (!(grstctl & S3C_GRSTCTL_AHBIdle))
+ continue;
+
+ break; /* reset done */
+ }
+
+ dev_dbg(hsotg->dev, "reset successful\n");
+ return 0;
+}
+
+int usb_gadget_register_driver(struct usb_gadget_driver *driver)
+{
+ struct s3c_hsotg *hsotg = our_hsotg;
+ int ret;
+
+ if (!hsotg) {
+ printk(KERN_ERR "%s: called with no device\n", __func__);
+ return -ENODEV;
+ }
+
+ if (!driver) {
+ dev_err(hsotg->dev, "%s: no driver\n", __func__);
+ return -EINVAL;
+ }
+
+ if (driver->speed != USB_SPEED_HIGH &&
+ driver->speed != USB_SPEED_FULL) {
+ dev_err(hsotg->dev, "%s: bad speed\n", __func__);
+ }
+
+ if (!driver->bind || !driver->setup) {
+ dev_err(hsotg->dev, "%s: missing entry points\n", __func__);
+ return -EINVAL;
+ }
+
+ WARN_ON(hsotg->driver);
+
+ driver->driver.bus = NULL;
+ hsotg->driver = driver;
+ hsotg->gadget.dev.driver = &driver->driver;
+ hsotg->gadget.dev.dma_mask = hsotg->dev->dma_mask;
+ hsotg->gadget.speed = USB_SPEED_UNKNOWN;
+
+ ret = device_add(&hsotg->gadget.dev);
+ if (ret) {
+ dev_err(hsotg->dev, "failed to register gadget device\n");
+ goto err;
+ }
+
+ ret = driver->bind(&hsotg->gadget);
+ if (ret) {
+ dev_err(hsotg->dev, "failed bind %s\n", driver->driver.name);
+
+ hsotg->gadget.dev.driver = NULL;
+ hsotg->driver = NULL;
+ goto err;
+ }
+
+ /* we must now enable ep0 ready for host detection and then
+ * set configuration. */
+
+ s3c_hsotg_corereset(hsotg);
+
+ /* set the PLL on, remove the HNP/SRP and set the PHY */
+ writel(S3C_GUSBCFG_PHYIf16 | S3C_GUSBCFG_TOutCal(7) |
+ (0x5 << 10), hsotg->regs + S3C_GUSBCFG);
+
+ /* looks like soft-reset changes state of FIFOs */
+ s3c_hsotg_init_fifo(hsotg);
+
+ __orr32(hsotg->regs + S3C_DCTL, S3C_DCTL_SftDiscon);
+
+ writel(1 << 18 | S3C_DCFG_DevSpd_HS, hsotg->regs + S3C_DCFG);
+
+ writel(S3C_GINTSTS_DisconnInt | S3C_GINTSTS_SessReqInt |
+ S3C_GINTSTS_ConIDStsChng | S3C_GINTSTS_USBRst |
+ S3C_GINTSTS_EnumDone | S3C_GINTSTS_OTGInt |
+ S3C_GINTSTS_USBSusp | S3C_GINTSTS_WkUpInt |
+ S3C_GINTSTS_GOUTNakEff | S3C_GINTSTS_GINNakEff |
+ S3C_GINTSTS_ErlySusp,
+ hsotg->regs + S3C_GINTMSK);
+
+ if (using_dma(hsotg))
+ writel(S3C_GAHBCFG_GlblIntrEn | S3C_GAHBCFG_DMAEn |
+ S3C_GAHBCFG_HBstLen_Incr4,
+ hsotg->regs + S3C_GAHBCFG);
+ else
+ writel(S3C_GAHBCFG_GlblIntrEn, hsotg->regs + S3C_GAHBCFG);
+
+ /* Enabling INTknTXFEmpMsk here seems to be a big mistake, we end
+ * up being flooded with interrupts if the host is polling the
+ * endpoint to try and read data. */
+
+ writel(S3C_DIEPMSK_TimeOUTMsk | S3C_DIEPMSK_AHBErrMsk |
+ S3C_DIEPMSK_INTknEPMisMsk |
+ S3C_DIEPMSK_EPDisbldMsk | S3C_DIEPMSK_XferComplMsk,
+ hsotg->regs + S3C_DIEPMSK);
+
+ /* don't need XferCompl, we get that from RXFIFO in slave mode. In
+ * DMA mode we may need this. */
+ writel(S3C_DOEPMSK_SetupMsk | S3C_DOEPMSK_AHBErrMsk |
+ S3C_DOEPMSK_EPDisbldMsk |
+ using_dma(hsotg) ? (S3C_DIEPMSK_XferComplMsk |
+ S3C_DIEPMSK_TimeOUTMsk) : 0,
+ hsotg->regs + S3C_DOEPMSK);
+
+ writel(0, hsotg->regs + S3C_DAINTMSK);
+
+ dev_info(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
+ readl(hsotg->regs + S3C_DIEPCTL0),
+ readl(hsotg->regs + S3C_DOEPCTL0));
+
+ /* enable in and out endpoint interrupts */
+ s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_OEPInt | S3C_GINTSTS_IEPInt);
+
+ /* Enable the RXFIFO when in slave mode, as this is how we collect
+ * the data. In DMA mode, we get events from the FIFO but also
+ * things we cannot process, so do not use it. */
+ if (!using_dma(hsotg))
+ s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_RxFLvl);
+
+ /* Enable interrupts for EP0 in and out */
+ s3c_hsotg_ctrl_epint(hsotg, 0, 0, 1);
+ s3c_hsotg_ctrl_epint(hsotg, 0, 1, 1);
+
+ __orr32(hsotg->regs + S3C_DCTL, S3C_DCTL_PWROnPrgDone);
+ udelay(10); /* see openiboot */
+ __bic32(hsotg->regs + S3C_DCTL, S3C_DCTL_PWROnPrgDone);
+
+ dev_info(hsotg->dev, "DCTL=0x%08x\n", readl(hsotg->regs + S3C_DCTL));
+
+ /* S3C_DxEPCTL_USBActEp says RO in manual, but seems to be set by
+ writing to the EPCTL register.. */
+
+ /* set to read 1 8byte packet */
+ writel(S3C_DxEPTSIZ_MC(1) | S3C_DxEPTSIZ_PktCnt(1) |
+ S3C_DxEPTSIZ_XferSize(8), hsotg->regs + DOEPTSIZ0);
+
+ writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) |
+ S3C_DxEPCTL_CNAK | S3C_DxEPCTL_EPEna |
+ S3C_DxEPCTL_USBActEp,
+ hsotg->regs + S3C_DOEPCTL0);
+
+ /* enable, but don't activate EP0in */
+ writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) |
+ S3C_DxEPCTL_USBActEp, hsotg->regs + S3C_DIEPCTL0);
+
+ s3c_hsotg_enqueue_setup(hsotg);
+
+ dev_info(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
+ readl(hsotg->regs + S3C_DIEPCTL0),
+ readl(hsotg->regs + S3C_DOEPCTL0));
+
+ /* clear global NAKs */
+ writel(S3C_DCTL_CGOUTNak | S3C_DCTL_CGNPInNAK,
+ hsotg->regs + S3C_DCTL);
+
+ /* remove the soft-disconnect and let's go */
+ __bic32(hsotg->regs + S3C_DCTL, S3C_DCTL_SftDiscon);
+
+ /* report to the user, and return */
+
+ dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
+ return 0;
+
+err:
+ hsotg->driver = NULL;
+ hsotg->gadget.dev.driver = NULL;
+ return ret;
+}
+
+int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
+{
+ struct s3c_hsotg *hsotg = our_hsotg;
+ int ep;
+
+ if (!hsotg)
+ return -ENODEV;
+
+ if (!driver || driver != hsotg->driver || !driver->unbind)
+ return -EINVAL;
+
+ /* all endpoints should be shutdown */
+ for (ep = 0; ep < S3C_HSOTG_EPS; ep++)
+ s3c_hsotg_ep_disable(&hsotg->eps[ep].ep);
+
+ call_gadget(hsotg, disconnect);
+
+ driver->unbind(&hsotg->gadget);
+ hsotg->driver = NULL;
+ hsotg->gadget.speed = USB_SPEED_UNKNOWN;
+
+ device_del(&hsotg->gadget.dev);
+
+ dev_info(hsotg->dev, "unregistered gadget driver '%s'\n",
+ driver->driver.name);
+
+ return 0;
+}
+EXPORT_SYMBOL(usb_gadget_unregister_driver);
+
+static int s3c_hsotg_gadget_getframe(struct usb_gadget *gadget)
+{
+ return s3c_hsotg_read_frameno(to_hsotg(gadget));
+}
+
+static struct usb_gadget_ops s3c_hsotg_gadget_ops = {
+ .get_frame = s3c_hsotg_gadget_getframe,
+};
+
+/**
+ * s3c_hsotg_initep - initialise a single endpoint
+ * @hsotg: The device state.
+ * @hs_ep: The endpoint to be initialised.
+ * @epnum: The endpoint number
+ *
+ * Initialise the given endpoint (as part of the probe and device state
+ * creation) to give to the gadget driver. Setup the endpoint name, any
+ * direction information and other state that may be required.
+ */
+static void __devinit s3c_hsotg_initep(struct s3c_hsotg *hsotg,
+ struct s3c_hsotg_ep *hs_ep,
+ int epnum)
+{
+ u32 ptxfifo;
+ char *dir;
+
+ if (epnum == 0)
+ dir = "";
+ else if ((epnum % 2) == 0) {
+ dir = "out";
+ } else {
+ dir = "in";
+ hs_ep->dir_in = 1;
+ }
+
+ hs_ep->index = epnum;
+
+ snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir);
+
+ INIT_LIST_HEAD(&hs_ep->queue);
+ INIT_LIST_HEAD(&hs_ep->ep.ep_list);
+
+ spin_lock_init(&hs_ep->lock);
+
+ /* add to the list of endpoints known by the gadget driver */
+ if (epnum)
+ list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list);
+
+ hs_ep->parent = hsotg;
+ hs_ep->ep.name = hs_ep->name;
+ hs_ep->ep.maxpacket = epnum ? 512 : EP0_MPS_LIMIT;
+ hs_ep->ep.ops = &s3c_hsotg_ep_ops;
+
+ /* Read the FIFO size for the Periodic TX FIFO, even if we're
+ * an OUT endpoint, we may as well do this if in future the
+ * code is changed to make each endpoint's direction changeable.
+ */
+
+ ptxfifo = readl(hsotg->regs + S3C_DPTXFSIZn(epnum));
+ hs_ep->fifo_size = S3C_DPTXFSIZn_DPTxFSize_GET(ptxfifo);
+
+ /* if we're using dma, we need to set the next-endpoint pointer
+ * to be something valid.
+ */
+
+ if (using_dma(hsotg)) {
+ u32 next = S3C_DxEPCTL_NextEp((epnum + 1) % 15);
+ writel(next, hsotg->regs + S3C_DIEPCTL(epnum));
+ writel(next, hsotg->regs + S3C_DOEPCTL(epnum));
+ }
+}
+
+/**
+ * s3c_hsotg_otgreset - reset the OtG phy block
+ * @hsotg: The host state.
+ *
+ * Power up the phy, set the basic configuration and start the PHY.
+ */
+static void s3c_hsotg_otgreset(struct s3c_hsotg *hsotg)
+{
+ u32 osc;
+
+ writel(0, S3C_PHYPWR);
+ mdelay(1);
+
+ osc = hsotg->plat->is_osc ? S3C_PHYCLK_EXT_OSC : 0;
+
+ writel(osc | 0x10, S3C_PHYCLK);
+
+ /* issue a full set of resets to the otg and core */
+
+ writel(S3C_RSTCON_PHY, S3C_RSTCON);
+ udelay(20); /* at-least 10uS */
+ writel(0, S3C_RSTCON);
+}
+
+
+static void s3c_hsotg_init(struct s3c_hsotg *hsotg)
+{
+ /* unmask subset of endpoint interrupts */
+
+ writel(S3C_DIEPMSK_TimeOUTMsk | S3C_DIEPMSK_AHBErrMsk |
+ S3C_DIEPMSK_EPDisbldMsk | S3C_DIEPMSK_XferComplMsk,
+ hsotg->regs + S3C_DIEPMSK);
+
+ writel(S3C_DOEPMSK_SetupMsk | S3C_DOEPMSK_AHBErrMsk |
+ S3C_DOEPMSK_EPDisbldMsk | S3C_DOEPMSK_XferComplMsk,
+ hsotg->regs + S3C_DOEPMSK);
+
+ writel(0, hsotg->regs + S3C_DAINTMSK);
+
+ if (0) {
+ /* post global nak until we're ready */
+ writel(S3C_DCTL_SGNPInNAK | S3C_DCTL_SGOUTNak,
+ hsotg->regs + S3C_DCTL);
+ }
+
+ /* setup fifos */
+
+ dev_info(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
+ readl(hsotg->regs + S3C_GRXFSIZ),
+ readl(hsotg->regs + S3C_GNPTXFSIZ));
+
+ s3c_hsotg_init_fifo(hsotg);
+
+ /* set the PLL on, remove the HNP/SRP and set the PHY */
+ writel(S3C_GUSBCFG_PHYIf16 | S3C_GUSBCFG_TOutCal(7) | (0x5 << 10),
+ hsotg->regs + S3C_GUSBCFG);
+
+ writel(using_dma(hsotg) ? S3C_GAHBCFG_DMAEn : 0x0,
+ hsotg->regs + S3C_GAHBCFG);
+}
+
+static void s3c_hsotg_dump(struct s3c_hsotg *hsotg)
+{
+ struct device *dev = hsotg->dev;
+ void __iomem *regs = hsotg->regs;
+ u32 val;
+ int idx;
+
+ dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
+ readl(regs + S3C_DCFG), readl(regs + S3C_DCTL),
+ readl(regs + S3C_DIEPMSK));
+
+ dev_info(dev, "GAHBCFG=0x%08x, 0x44=0x%08x\n",
+ readl(regs + S3C_GAHBCFG), readl(regs + 0x44));
+
+ dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
+ readl(regs + S3C_GRXFSIZ), readl(regs + S3C_GNPTXFSIZ));
+
+ /* show periodic fifo settings */
+
+ for (idx = 1; idx <= 15; idx++) {
+ val = readl(regs + S3C_DPTXFSIZn(idx));
+ dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
+ val >> S3C_DPTXFSIZn_DPTxFSize_SHIFT,
+ val & S3C_DPTXFSIZn_DPTxFStAddr_MASK);
+ }
+
+ for (idx = 0; idx < 15; idx++) {
+ dev_info(dev,
+ "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
+ readl(regs + S3C_DIEPCTL(idx)),
+ readl(regs + S3C_DIEPTSIZ(idx)),
+ readl(regs + S3C_DIEPDMA(idx)));
+
+ val = readl(regs + S3C_DOEPCTL(idx));
+ dev_info(dev,
+ "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
+ idx, readl(regs + S3C_DOEPCTL(idx)),
+ readl(regs + S3C_DOEPTSIZ(idx)),
+ readl(regs + S3C_DOEPDMA(idx)));
+
+ }
+
+ dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
+ readl(regs + S3C_DVBUSDIS), readl(regs + S3C_DVBUSPULSE));
+}
+
+
+/**
+ * state_show - debugfs: show overall driver and device state.
+ * @seq: The seq file to write to.
+ * @v: Unused parameter.
+ *
+ * This debugfs entry shows the overall state of the hardware and
+ * some general information about each of the endpoints available
+ * to the system.
+ */
+static int state_show(struct seq_file *seq, void *v)
+{
+ struct s3c_hsotg *hsotg = seq->private;
+ void __iomem *regs = hsotg->regs;
+ int idx;
+
+ seq_printf(seq, "DCFG=0x%08x, DCTL=0x%08x, DSTS=0x%08x\n",
+ readl(regs + S3C_DCFG),
+ readl(regs + S3C_DCTL),
+ readl(regs + S3C_DSTS));
+
+ seq_printf(seq, "DIEPMSK=0x%08x, DOEPMASK=0x%08x\n",
+ readl(regs + S3C_DIEPMSK), readl(regs + S3C_DOEPMSK));
+
+ seq_printf(seq, "GINTMSK=0x%08x, GINTSTS=0x%08x\n",
+ readl(regs + S3C_GINTMSK),
+ readl(regs + S3C_GINTSTS));
+
+ seq_printf(seq, "DAINTMSK=0x%08x, DAINT=0x%08x\n",
+ readl(regs + S3C_DAINTMSK),
+ readl(regs + S3C_DAINT));
+
+ seq_printf(seq, "GNPTXSTS=0x%08x, GRXSTSR=%08x\n",
+ readl(regs + S3C_GNPTXSTS),
+ readl(regs + S3C_GRXSTSR));
+
+ seq_printf(seq, "\nEndpoint status:\n");
+
+ for (idx = 0; idx < 15; idx++) {
+ u32 in, out;
+
+ in = readl(regs + S3C_DIEPCTL(idx));
+ out = readl(regs + S3C_DOEPCTL(idx));
+
+ seq_printf(seq, "ep%d: DIEPCTL=0x%08x, DOEPCTL=0x%08x",
+ idx, in, out);
+
+ in = readl(regs + S3C_DIEPTSIZ(idx));
+ out = readl(regs + S3C_DOEPTSIZ(idx));
+
+ seq_printf(seq, ", DIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x",
+ in, out);
+
+ seq_printf(seq, "\n");
+ }
+
+ return 0;
+}
+
+static int state_open(struct inode *inode, struct file *file)
+{
+ return single_open(file, state_show, inode->i_private);
+}
+
+static const struct file_operations state_fops = {
+ .owner = THIS_MODULE,
+ .open = state_open,
+ .read = seq_read,
+ .llseek = seq_lseek,
+ .release = single_release,
+};
+
+/**
+ * fifo_show - debugfs: show the fifo information
+ * @seq: The seq_file to write data to.
+ * @v: Unused parameter.
+ *
+ * Show the FIFO information for the overall fifo and all the
+ * periodic transmission FIFOs.
+*/
+static int fifo_show(struct seq_file *seq, void *v)
+{
+ struct s3c_hsotg *hsotg = seq->private;
+ void __iomem *regs = hsotg->regs;
+ u32 val;
+ int idx;
+
+ seq_printf(seq, "Non-periodic FIFOs:\n");
+ seq_printf(seq, "RXFIFO: Size %d\n", readl(regs + S3C_GRXFSIZ));
+
+ val = readl(regs + S3C_GNPTXFSIZ);
+ seq_printf(seq, "NPTXFIFO: Size %d, Start 0x%08x\n",
+ val >> S3C_GNPTXFSIZ_NPTxFDep_SHIFT,
+ val & S3C_GNPTXFSIZ_NPTxFStAddr_MASK);
+
+ seq_printf(seq, "\nPeriodic TXFIFOs:\n");
+
+ for (idx = 1; idx <= 15; idx++) {
+ val = readl(regs + S3C_DPTXFSIZn(idx));
+
+ seq_printf(seq, "\tDPTXFIFO%2d: Size %d, Start 0x%08x\n", idx,
+ val >> S3C_DPTXFSIZn_DPTxFSize_SHIFT,
+ val & S3C_DPTXFSIZn_DPTxFStAddr_MASK);
+ }
+
+ return 0;
+}
+
+static int fifo_open(struct inode *inode, struct file *file)
+{
+ return single_open(file, fifo_show, inode->i_private);
+}
+
+static const struct file_operations fifo_fops = {
+ .owner = THIS_MODULE,
+ .open = fifo_open,
+ .read = seq_read,
+ .llseek = seq_lseek,
+ .release = single_release,
+};
+
+
+static const char *decode_direction(int is_in)
+{
+ return is_in ? "in" : "out";
+}
+
+/**
+ * ep_show - debugfs: show the state of an endpoint.
+ * @seq: The seq_file to write data to.
+ * @v: Unused parameter.
+ *
+ * This debugfs entry shows the state of the given endpoint (one is
+ * registered for each available).
+*/
+static int ep_show(struct seq_file *seq, void *v)
+{
+ struct s3c_hsotg_ep *ep = seq->private;
+ struct s3c_hsotg *hsotg = ep->parent;
+ struct s3c_hsotg_req *req;
+ void __iomem *regs = hsotg->regs;
+ int index = ep->index;
+ int show_limit = 15;
+ unsigned long flags;
+
+ seq_printf(seq, "Endpoint index %d, named %s, dir %s:\n",
+ ep->index, ep->ep.name, decode_direction(ep->dir_in));
+
+ /* first show the register state */
+
+ seq_printf(seq, "\tDIEPCTL=0x%08x, DOEPCTL=0x%08x\n",
+ readl(regs + S3C_DIEPCTL(index)),
+ readl(regs + S3C_DOEPCTL(index)));
+
+ seq_printf(seq, "\tDIEPDMA=0x%08x, DOEPDMA=0x%08x\n",
+ readl(regs + S3C_DIEPDMA(index)),
+ readl(regs + S3C_DOEPDMA(index)));
+
+ seq_printf(seq, "\tDIEPINT=0x%08x, DOEPINT=0x%08x\n",
+ readl(regs + S3C_DIEPINT(index)),
+ readl(regs + S3C_DOEPINT(index)));
+
+ seq_printf(seq, "\tDIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x\n",
+ readl(regs + S3C_DIEPTSIZ(index)),
+ readl(regs + S3C_DOEPTSIZ(index)));
+
+ seq_printf(seq, "\n");
+ seq_printf(seq, "mps %d\n", ep->ep.maxpacket);
+ seq_printf(seq, "total_data=%ld\n", ep->total_data);
+
+ seq_printf(seq, "request list (%p,%p):\n",
+ ep->queue.next, ep->queue.prev);
+
+ spin_lock_irqsave(&ep->lock, flags);
+
+ list_for_each_entry(req, &ep->queue, queue) {
+ if (--show_limit < 0) {
+ seq_printf(seq, "not showing more requests...\n");
+ break;
+ }
+
+ seq_printf(seq, "%c req %p: %d bytes @%p, ",
+ req == ep->req ? '*' : ' ',
+ req, req->req.length, req->req.buf);
+ seq_printf(seq, "%d done, res %d\n",
+ req->req.actual, req->req.status);
+ }
+
+ spin_unlock_irqrestore(&ep->lock, flags);
+
+ return 0;
+}
+
+static int ep_open(struct inode *inode, struct file *file)
+{
+ return single_open(file, ep_show, inode->i_private);
+}
+
+static const struct file_operations ep_fops = {
+ .owner = THIS_MODULE,
+ .open = ep_open,
+ .read = seq_read,
+ .llseek = seq_lseek,
+ .release = single_release,
+};
+
+/**
+ * s3c_hsotg_create_debug - create debugfs directory and files
+ * @hsotg: The driver state
+ *
+ * Create the debugfs files to allow the user to get information
+ * about the state of the system. The directory name is created
+ * with the same name as the device itself, in case we end up
+ * with multiple blocks in future systems.
+*/
+static void __devinit s3c_hsotg_create_debug(struct s3c_hsotg *hsotg)
+{
+ struct dentry *root;
+ unsigned epidx;
+
+ root = debugfs_create_dir(dev_name(hsotg->dev), NULL);
+ hsotg->debug_root = root;
+ if (IS_ERR(root)) {
+ dev_err(hsotg->dev, "cannot create debug root\n");
+ return;
+ }
+
+ /* create general state file */
+
+ hsotg->debug_file = debugfs_create_file("state", 0444, root,
+ hsotg, &state_fops);
+
+ if (IS_ERR(hsotg->debug_file))
+ dev_err(hsotg->dev, "%s: failed to create state\n", __func__);
+
+ hsotg->debug_fifo = debugfs_create_file("fifo", 0444, root,
+ hsotg, &fifo_fops);
+
+ if (IS_ERR(hsotg->debug_fifo))
+ dev_err(hsotg->dev, "%s: failed to create fifo\n", __func__);
+
+ /* create one file for each endpoint */
+
+ for (epidx = 0; epidx < S3C_HSOTG_EPS; epidx++) {
+ struct s3c_hsotg_ep *ep = &hsotg->eps[epidx];
+
+ ep->debugfs = debugfs_create_file(ep->name, 0444,
+ root, ep, &ep_fops);
+
+ if (IS_ERR(ep->debugfs))
+ dev_err(hsotg->dev, "failed to create %s debug file\n",
+ ep->name);
+ }
+}
+
+/**
+ * s3c_hsotg_delete_debug - cleanup debugfs entries
+ * @hsotg: The driver state
+ *
+ * Cleanup (remove) the debugfs files for use on module exit.
+*/
+static void __devexit s3c_hsotg_delete_debug(struct s3c_hsotg *hsotg)
+{
+ unsigned epidx;
+
+ for (epidx = 0; epidx < S3C_HSOTG_EPS; epidx++) {
+ struct s3c_hsotg_ep *ep = &hsotg->eps[epidx];
+ debugfs_remove(ep->debugfs);
+ }
+
+ debugfs_remove(hsotg->debug_file);
+ debugfs_remove(hsotg->debug_fifo);
+ debugfs_remove(hsotg->debug_root);
+}
+
+/**
+ * s3c_hsotg_gate - set the hardware gate for the block
+ * @pdev: The device we bound to
+ * @on: On or off.
+ *
+ * Set the hardware gate setting into the block. If we end up on
+ * something other than an S3C64XX, then we might need to change this
+ * to using a platform data callback, or some other mechanism.
+ */
+static void s3c_hsotg_gate(struct platform_device *pdev, bool on)
+{
+ unsigned long flags;
+ u32 others;
+
+ local_irq_save(flags);
+
+ others = __raw_readl(S3C64XX_OTHERS);
+ if (on)
+ others |= S3C64XX_OTHERS_USBMASK;
+ else
+ others &= ~S3C64XX_OTHERS_USBMASK;
+ __raw_writel(others, S3C64XX_OTHERS);
+
+ local_irq_restore(flags);
+}
+
+struct s3c_hsotg_plat s3c_hsotg_default_pdata;
+
+static int __devinit s3c_hsotg_probe(struct platform_device *pdev)
+{
+ struct s3c_hsotg_plat *plat = pdev->dev.platform_data;
+ struct device *dev = &pdev->dev;
+ struct s3c_hsotg *hsotg;
+ struct resource *res;
+ int epnum;
+ int ret;
+
+ if (!plat)
+ plat = &s3c_hsotg_default_pdata;
+
+ hsotg = kzalloc(sizeof(struct s3c_hsotg) +
+ sizeof(struct s3c_hsotg_ep) * S3C_HSOTG_EPS,
+ GFP_KERNEL);
+ if (!hsotg) {
+ dev_err(dev, "cannot get memory\n");
+ return -ENOMEM;
+ }
+
+ hsotg->dev = dev;
+ hsotg->plat = plat;
+
+ platform_set_drvdata(pdev, hsotg);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+ dev_err(dev, "cannot find register resource 0\n");
+ ret = -EINVAL;
+ goto err_mem;
+ }
+
+ hsotg->regs_res = request_mem_region(res->start, resource_size(res),
+ dev_name(dev));
+ if (!hsotg->regs_res) {
+ dev_err(dev, "cannot reserve registers\n");
+ ret = -ENOENT;
+ goto err_mem;
+ }
+
+ hsotg->regs = ioremap(res->start, resource_size(res));
+ if (!hsotg->regs) {
+ dev_err(dev, "cannot map registers\n");
+ ret = -ENXIO;
+ goto err_regs_res;
+ }
+
+ ret = platform_get_irq(pdev, 0);
+ if (ret < 0) {
+ dev_err(dev, "cannot find IRQ\n");
+ goto err_regs;
+ }
+
+ hsotg->irq = ret;
+
+ ret = request_irq(ret, s3c_hsotg_irq, 0, dev_name(dev), hsotg);
+ if (ret < 0) {
+ dev_err(dev, "cannot claim IRQ\n");
+ goto err_regs;
+ }
+
+ dev_info(dev, "regs %p, irq %d\n", hsotg->regs, hsotg->irq);
+
+ device_initialize(&hsotg->gadget.dev);
+
+ dev_set_name(&hsotg->gadget.dev, "gadget");
+
+ hsotg->gadget.is_dualspeed = 1;
+ hsotg->gadget.ops = &s3c_hsotg_gadget_ops;
+ hsotg->gadget.name = dev_name(dev);
+
+ hsotg->gadget.dev.parent = dev;
+ hsotg->gadget.dev.dma_mask = dev->dma_mask;
+
+ /* setup endpoint information */
+
+ INIT_LIST_HEAD(&hsotg->gadget.ep_list);
+ hsotg->gadget.ep0 = &hsotg->eps[0].ep;
+
+ /* allocate EP0 request */
+
+ hsotg->ctrl_req = s3c_hsotg_ep_alloc_request(&hsotg->eps[0].ep,
+ GFP_KERNEL);
+ if (!hsotg->ctrl_req) {
+ dev_err(dev, "failed to allocate ctrl req\n");
+ goto err_regs;
+ }
+
+ /* reset the system */
+
+ s3c_hsotg_gate(pdev, true);
+
+ s3c_hsotg_otgreset(hsotg);
+ s3c_hsotg_corereset(hsotg);
+ s3c_hsotg_init(hsotg);
+
+ /* initialise the endpoints now the core has been initialised */
+ for (epnum = 0; epnum < S3C_HSOTG_EPS; epnum++)
+ s3c_hsotg_initep(hsotg, &hsotg->eps[epnum], epnum);
+
+ s3c_hsotg_create_debug(hsotg);
+
+ s3c_hsotg_dump(hsotg);
+
+ our_hsotg = hsotg;
+ return 0;
+
+err_regs:
+ iounmap(hsotg->regs);
+
+err_regs_res:
+ release_resource(hsotg->regs_res);
+ kfree(hsotg->regs_res);
+
+err_mem:
+ kfree(hsotg);
+ return ret;
+}
+
+static int __devexit s3c_hsotg_remove(struct platform_device *pdev)
+{
+ struct s3c_hsotg *hsotg = platform_get_drvdata(pdev);
+
+ s3c_hsotg_delete_debug(hsotg);
+
+ usb_gadget_unregister_driver(hsotg->driver);
+
+ free_irq(hsotg->irq, hsotg);
+ iounmap(hsotg->regs);
+
+ release_resource(hsotg->regs_res);
+ kfree(hsotg->regs_res);
+
+ s3c_hsotg_gate(pdev, false);
+
+ kfree(hsotg);
+ return 0;
+}
+
+#if 1
+#define s3c_hsotg_suspend NULL
+#define s3c_hsotg_resume NULL
+#endif
+
+static struct platform_driver s3c_hsotg_driver = {
+ .driver = {
+ .name = "s3c-hsotg",
+ .owner = THIS_MODULE,
+ },
+ .probe = s3c_hsotg_probe,
+ .remove = __devexit_p(s3c_hsotg_remove),
+ .suspend = s3c_hsotg_suspend,
+ .resume = s3c_hsotg_resume,
+};
+
+static int __init s3c_hsotg_modinit(void)
+{
+ return platform_driver_register(&s3c_hsotg_driver);
+}
+
+static void __exit s3c_hsotg_modexit(void)
+{
+ platform_driver_unregister(&s3c_hsotg_driver);
+}
+
+module_init(s3c_hsotg_modinit);
+module_exit(s3c_hsotg_modexit);
+
+MODULE_DESCRIPTION("Samsung S3C USB High-speed/OtG device");
+MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:s3c-hsotg");
diff --git a/drivers/usb/gadget/u_audio.c b/drivers/usb/gadget/u_audio.c
new file mode 100644
index 00000000000..0f3d22fc030
--- /dev/null
+++ b/drivers/usb/gadget/u_audio.c
@@ -0,0 +1,319 @@
+/*
+ * u_audio.c -- ALSA audio utilities for Gadget stack
+ *
+ * Copyright (C) 2008 Bryan Wu <cooloney@kernel.org>
+ * Copyright (C) 2008 Analog Devices, Inc
+ *
+ * Enter bugs at http://blackfin.uclinux.org/
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <linux/kernel.h>
+#include <linux/utsname.h>
+#include <linux/device.h>
+#include <linux/delay.h>
+#include <linux/ctype.h>
+#include <linux/random.h>
+#include <linux/syscalls.h>
+
+#include "u_audio.h"
+
+/*
+ * This component encapsulates the ALSA devices for USB audio gadget
+ */
+
+#define FILE_PCM_PLAYBACK "/dev/snd/pcmC0D0p"
+#define FILE_PCM_CAPTURE "/dev/snd/pcmC0D0c"
+#define FILE_CONTROL "/dev/snd/controlC0"
+
+static char *fn_play = FILE_PCM_PLAYBACK;
+module_param(fn_play, charp, S_IRUGO);
+MODULE_PARM_DESC(fn_play, "Playback PCM device file name");
+
+static char *fn_cap = FILE_PCM_CAPTURE;
+module_param(fn_cap, charp, S_IRUGO);
+MODULE_PARM_DESC(fn_cap, "Capture PCM device file name");
+
+static char *fn_cntl = FILE_CONTROL;
+module_param(fn_cntl, charp, S_IRUGO);
+MODULE_PARM_DESC(fn_cntl, "Control device file name");
+
+/*-------------------------------------------------------------------------*/
+
+/**
+ * Some ALSA internal helper functions
+ */
+static int snd_interval_refine_set(struct snd_interval *i, unsigned int val)
+{
+ struct snd_interval t;
+ t.empty = 0;
+ t.min = t.max = val;
+ t.openmin = t.openmax = 0;
+ t.integer = 1;
+ return snd_interval_refine(i, &t);
+}
+
+static int _snd_pcm_hw_param_set(struct snd_pcm_hw_params *params,
+ snd_pcm_hw_param_t var, unsigned int val,
+ int dir)
+{
+ int changed;
+ if (hw_is_mask(var)) {
+ struct snd_mask *m = hw_param_mask(params, var);
+ if (val == 0 && dir < 0) {
+ changed = -EINVAL;
+ snd_mask_none(m);
+ } else {
+ if (dir > 0)
+ val++;
+ else if (dir < 0)
+ val--;
+ changed = snd_mask_refine_set(
+ hw_param_mask(params, var), val);
+ }
+ } else if (hw_is_interval(var)) {
+ struct snd_interval *i = hw_param_interval(params, var);
+ if (val == 0 && dir < 0) {
+ changed = -EINVAL;
+ snd_interval_none(i);
+ } else if (dir == 0)
+ changed = snd_interval_refine_set(i, val);
+ else {
+ struct snd_interval t;
+ t.openmin = 1;
+ t.openmax = 1;
+ t.empty = 0;
+ t.integer = 0;
+ if (dir < 0) {
+ t.min = val - 1;
+ t.max = val;
+ } else {
+ t.min = val;
+ t.max = val+1;
+ }
+ changed = snd_interval_refine(i, &t);
+ }
+ } else
+ return -EINVAL;
+ if (changed) {
+ params->cmask |= 1 << var;
+ params->rmask |= 1 << var;
+ }
+ return changed;
+}
+/*-------------------------------------------------------------------------*/
+
+/**
+ * Set default hardware params
+ */
+static int playback_default_hw_params(struct gaudio_snd_dev *snd)
+{
+ struct snd_pcm_substream *substream = snd->substream;
+ struct snd_pcm_hw_params *params;
+ snd_pcm_sframes_t result;
+
+ /*
+ * SNDRV_PCM_ACCESS_RW_INTERLEAVED,
+ * SNDRV_PCM_FORMAT_S16_LE
+ * CHANNELS: 2
+ * RATE: 48000
+ */
+ snd->access = SNDRV_PCM_ACCESS_RW_INTERLEAVED;
+ snd->format = SNDRV_PCM_FORMAT_S16_LE;
+ snd->channels = 2;
+ snd->rate = 48000;
+
+ params = kzalloc(sizeof(*params), GFP_KERNEL);
+ if (!params)
+ return -ENOMEM;
+
+ _snd_pcm_hw_params_any(params);
+ _snd_pcm_hw_param_set(params, SNDRV_PCM_HW_PARAM_ACCESS,
+ snd->access, 0);
+ _snd_pcm_hw_param_set(params, SNDRV_PCM_HW_PARAM_FORMAT,
+ snd->format, 0);
+ _snd_pcm_hw_param_set(params, SNDRV_PCM_HW_PARAM_CHANNELS,
+ snd->channels, 0);
+ _snd_pcm_hw_param_set(params, SNDRV_PCM_HW_PARAM_RATE,
+ snd->rate, 0);
+
+ snd_pcm_kernel_ioctl(substream, SNDRV_PCM_IOCTL_DROP, NULL);
+ snd_pcm_kernel_ioctl(substream, SNDRV_PCM_IOCTL_HW_PARAMS, params);
+
+ result = snd_pcm_kernel_ioctl(substream, SNDRV_PCM_IOCTL_PREPARE, NULL);
+ if (result < 0) {
+ ERROR(snd->card,
+ "Preparing sound card failed: %d\n", (int)result);
+ kfree(params);
+ return result;
+ }
+
+ /* Store the hardware parameters */
+ snd->access = params_access(params);
+ snd->format = params_format(params);
+ snd->channels = params_channels(params);
+ snd->rate = params_rate(params);
+
+ kfree(params);
+
+ INFO(snd->card,
+ "Hardware params: access %x, format %x, channels %d, rate %d\n",
+ snd->access, snd->format, snd->channels, snd->rate);
+
+ return 0;
+}
+
+/**
+ * Playback audio buffer data by ALSA PCM device
+ */
+static size_t u_audio_playback(struct gaudio *card, void *buf, size_t count)
+{
+ struct gaudio_snd_dev *snd = &card->playback;
+ struct snd_pcm_substream *substream = snd->substream;
+ struct snd_pcm_runtime *runtime = substream->runtime;
+ mm_segment_t old_fs;
+ ssize_t result;
+ snd_pcm_sframes_t frames;
+
+try_again:
+ if (runtime->status->state == SNDRV_PCM_STATE_XRUN ||
+ runtime->status->state == SNDRV_PCM_STATE_SUSPENDED) {
+ result = snd_pcm_kernel_ioctl(substream,
+ SNDRV_PCM_IOCTL_PREPARE, NULL);
+ if (result < 0) {
+ ERROR(card, "Preparing sound card failed: %d\n",
+ (int)result);
+ return result;
+ }
+ }
+
+ frames = bytes_to_frames(runtime, count);
+ old_fs = get_fs();
+ set_fs(KERNEL_DS);
+ result = snd_pcm_lib_write(snd->substream, buf, frames);
+ if (result != frames) {
+ ERROR(card, "Playback error: %d\n", (int)result);
+ set_fs(old_fs);
+ goto try_again;
+ }
+ set_fs(old_fs);
+
+ return 0;
+}
+
+static int u_audio_get_playback_channels(struct gaudio *card)
+{
+ return card->playback.channels;
+}
+
+static int u_audio_get_playback_rate(struct gaudio *card)
+{
+ return card->playback.rate;
+}
+
+/**
+ * Open ALSA PCM and control device files
+ * Initial the PCM or control device
+ */
+static int gaudio_open_snd_dev(struct gaudio *card)
+{
+ struct snd_pcm_file *pcm_file;
+ struct gaudio_snd_dev *snd;
+
+ if (!card)
+ return -ENODEV;
+
+ /* Open control device */
+ snd = &card->control;
+ snd->filp = filp_open(fn_cntl, O_RDWR, 0);
+ if (IS_ERR(snd->filp)) {
+ int ret = PTR_ERR(snd->filp);
+ ERROR(card, "unable to open sound control device file: %s\n",
+ fn_cntl);
+ snd->filp = NULL;
+ return ret;
+ }
+ snd->card = card;
+
+ /* Open PCM playback device and setup substream */
+ snd = &card->playback;
+ snd->filp = filp_open(fn_play, O_WRONLY, 0);
+ if (IS_ERR(snd->filp)) {
+ ERROR(card, "No such PCM playback device: %s\n", fn_play);
+ snd->filp = NULL;
+ }
+ pcm_file = snd->filp->private_data;
+ snd->substream = pcm_file->substream;
+ snd->card = card;
+ playback_default_hw_params(snd);
+
+ /* Open PCM capture device and setup substream */
+ snd = &card->capture;
+ snd->filp = filp_open(fn_cap, O_RDONLY, 0);
+ if (IS_ERR(snd->filp)) {
+ ERROR(card, "No such PCM capture device: %s\n", fn_cap);
+ snd->filp = NULL;
+ }
+ pcm_file = snd->filp->private_data;
+ snd->substream = pcm_file->substream;
+ snd->card = card;
+
+ return 0;
+}
+
+/**
+ * Close ALSA PCM and control device files
+ */
+static int gaudio_close_snd_dev(struct gaudio *gau)
+{
+ struct gaudio_snd_dev *snd;
+
+ /* Close control device */
+ snd = &gau->control;
+ if (!IS_ERR(snd->filp))
+ filp_close(snd->filp, current->files);
+
+ /* Close PCM playback device and setup substream */
+ snd = &gau->playback;
+ if (!IS_ERR(snd->filp))
+ filp_close(snd->filp, current->files);
+
+ /* Close PCM capture device and setup substream */
+ snd = &gau->capture;
+ if (!IS_ERR(snd->filp))
+ filp_close(snd->filp, current->files);
+
+ return 0;
+}
+
+/**
+ * gaudio_setup - setup ALSA interface and preparing for USB transfer
+ *
+ * This sets up PCM, mixer or MIDI ALSA devices fore USB gadget using.
+ *
+ * Returns negative errno, or zero on success
+ */
+int __init gaudio_setup(struct gaudio *card)
+{
+ int ret;
+
+ ret = gaudio_open_snd_dev(card);
+ if (ret)
+ ERROR(card, "we need at least one control device\n");
+
+ return ret;
+
+}
+
+/**
+ * gaudio_cleanup - remove ALSA device interface
+ *
+ * This is called to free all resources allocated by @gaudio_setup().
+ */
+void gaudio_cleanup(struct gaudio *card)
+{
+ if (card)
+ gaudio_close_snd_dev(card);
+}
+
diff --git a/drivers/usb/gadget/u_audio.h b/drivers/usb/gadget/u_audio.h
new file mode 100644
index 00000000000..cc8d159c648
--- /dev/null
+++ b/drivers/usb/gadget/u_audio.h
@@ -0,0 +1,56 @@
+/*
+ * u_audio.h -- interface to USB gadget "ALSA AUDIO" utilities
+ *
+ * Copyright (C) 2008 Bryan Wu <cooloney@kernel.org>
+ * Copyright (C) 2008 Analog Devices, Inc
+ *
+ * Enter bugs at http://blackfin.uclinux.org/
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __U_AUDIO_H
+#define __U_AUDIO_H
+
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/usb/audio.h>
+#include <linux/usb/composite.h>
+
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+
+#include "gadget_chips.h"
+
+/*
+ * This represents the USB side of an audio card device, managed by a USB
+ * function which provides control and stream interfaces.
+ */
+
+struct gaudio_snd_dev {
+ struct gaudio *card;
+ struct file *filp;
+ struct snd_pcm_substream *substream;
+ int access;
+ int format;
+ int channels;
+ int rate;
+};
+
+struct gaudio {
+ struct usb_function func;
+ struct usb_gadget *gadget;
+
+ /* ALSA sound device interfaces */
+ struct gaudio_snd_dev control;
+ struct gaudio_snd_dev playback;
+ struct gaudio_snd_dev capture;
+
+ /* TODO */
+};
+
+int gaudio_setup(struct gaudio *card);
+void gaudio_cleanup(struct gaudio *card);
+
+#endif /* __U_AUDIO_H */
diff --git a/drivers/usb/gadget/u_serial.c b/drivers/usb/gadget/u_serial.c
index 0a4d99ab40d..fc6e709f45b 100644
--- a/drivers/usb/gadget/u_serial.c
+++ b/drivers/usb/gadget/u_serial.c
@@ -371,6 +371,7 @@ __acquires(&port->port_lock)
req->length = len;
list_del(&req->list);
+ req->zero = (gs_buf_data_avail(&port->port_write_buf) == 0);
pr_vdebug(PREFIX "%d: tx len=%d, 0x%02x 0x%02x 0x%02x ...\n",
port->port_num, len, *((u8 *)req->buf),