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authorMichael Chan <mchan@broadcom.com>2006-03-22 01:05:31 -0800
committerDavid S. Miller <davem@davemloft.net>2006-03-22 01:05:31 -0800
commitcaf636c760b33c72ebf018ff03c1b0d79ea6656a (patch)
treed8ac1d485a820abcb7a17b73d309bb752e3c6223 /drivers
parent9a6b9f2e763a1d1492e164f13c13b995a9b98d78 (diff)
[TG3]: Fix SRAM access during tg3_init_one()
5700 and 5701 will not return correct SRAM data when the chip is in D3hot power state. tg3_get_eeprom_hw_cfg() must first put the device in D0 before reading SRAM. Thanks to Thomas Chenault at Dell for noticing this problem. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/tg3.c12
1 files changed, 9 insertions, 3 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index e03d1ae50c3..cb687fcaae1 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -9436,12 +9436,18 @@ static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
return NULL;
}
-/* Since this function may be called in D3-hot power state during
- * tg3_init_one(), only config cycles are allowed.
- */
static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
{
u32 val;
+ u16 pmcsr;
+
+ /* On some early chips the SRAM cannot be accessed in D3hot state,
+ * so need make sure we're in D0.
+ */
+ pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
+ pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
+ pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
+ msleep(1);
/* Make sure register accesses (indirect or otherwise)
* will function correctly.