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authorPavel Pisa <ppisa@pikron.com>2007-03-07 23:56:16 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2007-03-12 16:49:35 +0000
commitb3c6b76ffb1a8c8d1f12e838a25c1a86f5316e2c (patch)
tree7e68897d90f93ea62b890128408cfbf2d0b57c86 /fs/hpfs
parent83b84c4e8c7cf00e26610f03ee59e9be010f527c (diff)
[ARM] 4255/1: i.MX/MX1 Correct MPU PLL reference clock value.
Only System PLL clock source is selectable by CSCR_SYSTEM_SEL bit. MPU PLL is driven by 512*CLK32 for each case. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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