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| author | Dmitry Torokhov <dtor_core@ameritech.net> | 2005-09-09 20:14:47 -0500 |
|---|---|---|
| committer | Dmitry Torokhov <dtor_core@ameritech.net> | 2005-09-09 20:14:47 -0500 |
| commit | d344c5e0856ad03278d8700b503762dbc8b86e12 (patch) | |
| tree | a6d893a643470a3c2580a58f3228a55fa1fd1d82 /include/asm-alpha/auxvec.h | |
| parent | 010988e888a0abbe7118635c1b33d049caae6b29 (diff) | |
| parent | 87fc767b832ef5a681a0ff9d203c3289bc3be2bf (diff) | |
Manual merge with Linus
Diffstat (limited to 'include/asm-alpha/auxvec.h')
| -rw-r--r-- | include/asm-alpha/auxvec.h | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/include/asm-alpha/auxvec.h b/include/asm-alpha/auxvec.h new file mode 100644 index 00000000000..e96fe880e31 --- /dev/null +++ b/include/asm-alpha/auxvec.h @@ -0,0 +1,24 @@ +#ifndef __ASM_ALPHA_AUXVEC_H +#define __ASM_ALPHA_AUXVEC_H + +/* Reserve these numbers for any future use of a VDSO. */ +#if 0 +#define AT_SYSINFO 32 +#define AT_SYSINFO_EHDR 33 +#endif + +/* More complete cache descriptions than AT_[DIU]CACHEBSIZE. If the + value is -1, then the cache doesn't exist. Otherwise: + + bit 0-3: Cache set-associativity; 0 means fully associative. + bit 4-7: Log2 of cacheline size. + bit 8-31: Size of the entire cache >> 8. + bit 32-63: Reserved. +*/ + +#define AT_L1I_CACHESHAPE 34 +#define AT_L1D_CACHESHAPE 35 +#define AT_L2_CACHESHAPE 36 +#define AT_L3_CACHESHAPE 37 + +#endif /* __ASM_ALPHA_AUXVEC_H */ |