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authorDmitry Torokhov <dtor_core@ameritech.net>2006-04-02 00:08:05 -0500
committerDmitry Torokhov <dtor_core@ameritech.net>2006-04-02 00:08:05 -0500
commit95d465fd750897ab32462a6702fbfe1b122cbbc0 (patch)
tree65c38b2f11c51bb6932e44dd6c92f15b0091abfe /include/asm-arm/system.h
parent642fde17dceceb56c7ba2762733ac688666ae657 (diff)
parent683aa4012f53b2ada0f430487e05d37b0d94e90a (diff)
Manual merge with Linus.
Conflicts: arch/powerpc/kernel/setup-common.c drivers/input/keyboard/hil_kbd.c drivers/input/mouse/hil_ptr.c
Diffstat (limited to 'include/asm-arm/system.h')
-rw-r--r--include/asm-arm/system.h22
1 files changed, 22 insertions, 0 deletions
diff --git a/include/asm-arm/system.h b/include/asm-arm/system.h
index eb2de8c1051..95b3abf4851 100644
--- a/include/asm-arm/system.h
+++ b/include/asm-arm/system.h
@@ -108,6 +108,25 @@ extern void __show_regs(struct pt_regs *);
extern int cpu_architecture(void);
extern void cpu_init(void);
+/*
+ * Intel's XScale3 core supports some v6 features (supersections, L2)
+ * but advertises itself as v5 as it does not support the v6 ISA. For
+ * this reason, we need a way to explicitly test for this type of CPU.
+ */
+#ifndef CONFIG_CPU_XSC3
+#define cpu_is_xsc3() 0
+#else
+static inline int cpu_is_xsc3(void)
+{
+ extern unsigned int processor_id;
+
+ if ((processor_id & 0xffffe000) == 0x69056000)
+ return 1;
+
+ return 0;
+}
+#endif
+
#define set_cr(x) \
__asm__ __volatile__( \
"mcr p15, 0, %0, c1, c0, 0 @ set CR" \
@@ -415,6 +434,9 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size
return ret;
}
+extern void disable_hlt(void);
+extern void enable_hlt(void);
+
#endif /* __ASSEMBLY__ */
#define arch_align_stack(x) (x)