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| author | Jeff Garzik <jeff@garzik.org> | 2006-03-29 17:18:49 -0500 |
|---|---|---|
| committer | Jeff Garzik <jeff@garzik.org> | 2006-03-29 17:18:49 -0500 |
| commit | e02a4cabfcb9a999b74a2e2e6f13ffcb7ff2d606 (patch) | |
| tree | 2f3db60be4c57eca2a4c3ab3f3122dcf1ec0c624 /include/asm-arm/system.h | |
| parent | 600511e86babe3727264a0883a3a264f6fb6caf5 (diff) | |
| parent | f3cab8a0b1a772dc8b055b7affa567a366627c9e (diff) | |
Merge branch 'master'
Diffstat (limited to 'include/asm-arm/system.h')
| -rw-r--r-- | include/asm-arm/system.h | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/include/asm-arm/system.h b/include/asm-arm/system.h index ec91d1ff032..95b3abf4851 100644 --- a/include/asm-arm/system.h +++ b/include/asm-arm/system.h @@ -108,6 +108,25 @@ extern void __show_regs(struct pt_regs *); extern int cpu_architecture(void); extern void cpu_init(void); +/* + * Intel's XScale3 core supports some v6 features (supersections, L2) + * but advertises itself as v5 as it does not support the v6 ISA. For + * this reason, we need a way to explicitly test for this type of CPU. + */ +#ifndef CONFIG_CPU_XSC3 +#define cpu_is_xsc3() 0 +#else +static inline int cpu_is_xsc3(void) +{ + extern unsigned int processor_id; + + if ((processor_id & 0xffffe000) == 0x69056000) + return 1; + + return 0; +} +#endif + #define set_cr(x) \ __asm__ __volatile__( \ "mcr p15, 0, %0, c1, c0, 0 @ set CR" \ |