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authorGeorge G. Davis <gdavis@mvista.com>2007-06-26 01:38:27 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2007-07-12 11:13:35 +0100
commit909d6c6c80311f800aee338e5fa528818b115951 (patch)
treed4934d8ea67ade7c78e02e4cebd0fc934d3698b1 /include/asm-arm
parent9d20fdd58e74d4d26dc5216efaaa0f800c23dd3a (diff)
[ARM] 4453/1: Fully Decode ARM instruction set state in show_regs() tombstone
The ARM show_regs() tombstone only partially decodes which ARM ISA was executing at the time a fault occurred displaying either "(T)" for the Thumb case or nothing at all for other cases. This patch therefore explicitly identifies which state the processor is in at the time of a fault: ARM, Thumb, Jazelle or JazelleEE. Signed-off-by: George G. Davis <gdavis@mvista.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include/asm-arm')
-rw-r--r--include/asm-arm/ptrace.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/include/asm-arm/ptrace.h b/include/asm-arm/ptrace.h
index ee3d93c281d..ff038b65f37 100644
--- a/include/asm-arm/ptrace.h
+++ b/include/asm-arm/ptrace.h
@@ -103,6 +103,10 @@ struct pt_regs {
#define thumb_mode(regs) (0)
#endif
+#define isa_mode(regs) \
+ ((((regs)->ARM_cpsr & PSR_J_BIT) >> 23) | \
+ (((regs)->ARM_cpsr & PSR_T_BIT) >> 5))
+
#define processor_mode(regs) \
((regs)->ARM_cpsr & MODE_MASK)