diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2008-04-24 09:33:34 -0700 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2008-04-24 09:33:34 -0700 |
commit | 346ad4b7fe392571f19314f153db9151dbc1d82b (patch) | |
tree | 2d4085338c9044bca2f6472893da60387db3c96f /include/asm-blackfin/time.h | |
parent | 845199f194306dbd69ca42d3b40a5125cdb50b89 (diff) | |
parent | 2dc63a84b2db23b9680646aff93917211613bf1a (diff) |
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cooloney/blackfin-2.6
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cooloney/blackfin-2.6: (85 commits)
Blackfin char driver for Blackfin on-chip OTP memory (v3)
Blackfin Serial Driver: fix bug - use mod_timer to replace only add_timer.
Blackfin Serial Driver: the uart break anomaly has been given its own number, so switch to it
Blackfin Serial Driver: use BFIN_UART_NR_PORTS to help SIR driver in uart port.
Blackfin Serial Driver: Fix bug - kernel hangs when accessing uart 0 on bf537 when booting u-boot and linux on uart 1
Blackfin Serial Driver: punt unused lsr variable
Blackfin Serial Driver: Enable IR function when user application (irattach /dev/ttyBFx -s) call TIOCSETD ioctl with line discipline N_IRDA
[Blackfin] arch: add include/boot .gitignore files
[Blackfin] arch: Functional power management support: Add support for cpu frequency scaling
[Blackfin] arch: Functional power management support: Remove broken cpu frequency scaling drivers
[Blackfin] arch: Equalize include files: Add PLL_DIV Masks
[Blackfin] arch: Add a warning about the value of CLKIN.
[Blackfin] arch: take DDR DEVWD into consideration as well for BF548
[Blackfin] arch: Remove the circular buffering mechanism for exceptions
[Blackfin] arch: lose unnecessary dependency on CONFIG_BFIN_ICACHE for MPU
[Blackfin] arch: fix bug - before assign new channel to the map register, need clear the bits first.
[Blackfin] arch: add Blackfin on-chip SIR IrDA driver support
[Blackfin] arch: BF54x memsizes are in mbits, not mbytes
[Blackfin] arch: try to remove condition that causes double fault, by checking current before it gets dereferenced
[Blackfin] arch: Update anomaly list.
...
Diffstat (limited to 'include/asm-blackfin/time.h')
-rw-r--r-- | include/asm-blackfin/time.h | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/include/asm-blackfin/time.h b/include/asm-blackfin/time.h new file mode 100644 index 00000000000..6e5859b6ea3 --- /dev/null +++ b/include/asm-blackfin/time.h @@ -0,0 +1,36 @@ +/* + * asm-blackfin/time.h: + * + * Copyright 2004-2008 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef _ASM_BLACKFIN_TIME_H +#define _ASM_BLACKFIN_TIME_H + +/* + * The way that the Blackfin core timer works is: + * - CCLK is divided by a programmable 8-bit pre-scaler (TSCALE) + * - Every time TSCALE ticks, a 32bit is counted down (TCOUNT) + * + * If you take the fastest clock (1ns, or 1GHz to make the math work easier) + * 10ms is 10,000,000 clock ticks, which fits easy into a 32-bit counter + * (32 bit counter is 4,294,967,296ns or 4.2 seconds) so, we don't need + * to use TSCALE, and program it to zero (which is pass CCLK through). + * If you feel like using it, try to keep HZ * TIMESCALE to some + * value that divides easy (like power of 2). + */ + +#ifndef CONFIG_CPU_FREQ +#define TIME_SCALE 1 +#else +/* + * Blackfin CPU frequency scaling supports max Core Clock 1, 1/2 and 1/4 . + * Whenever we change the Core Clock frequency changes we immediately + * adjust the Core Timer Presale Register. This way we don't lose time. + */ +#define TIME_SCALE 4 +#endif + +#endif |