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authorYoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>2007-09-13 23:51:26 +0900
committerRalf Baechle <ralf@linux-mips.org>2007-10-11 23:46:04 +0100
commitd5ab1a6910fe850fa092888f210cf6c43136a7ab (patch)
tree142f9f35f0d9fc6e675caf42a1cd8a82b56aa8e9 /include/asm-mips/mach-cobalt
parent718f05f6ddc171a90fb7a277be6f6f65b4ca82be (diff)
[MIPS] Add GT641xx IRQ routines.
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/mach-cobalt')
-rw-r--r--include/asm-mips/mach-cobalt/cobalt.h26
-rw-r--r--include/asm-mips/mach-cobalt/irq.h58
2 files changed, 58 insertions, 26 deletions
diff --git a/include/asm-mips/mach-cobalt/cobalt.h b/include/asm-mips/mach-cobalt/cobalt.h
index 9c9d2b998ca..408eeccbe51 100644
--- a/include/asm-mips/mach-cobalt/cobalt.h
+++ b/include/asm-mips/mach-cobalt/cobalt.h
@@ -12,32 +12,6 @@
#ifndef __ASM_COBALT_H
#define __ASM_COBALT_H
-#include <irq.h>
-
-/*
- * i8259 legacy interrupts used on Cobalt:
- *
- * 8 - RTC
- * 9 - PCI
- * 14 - IDE0
- * 15 - IDE1
- */
-#define COBALT_QUBE_SLOT_IRQ 9
-
-/*
- * CPU IRQs are 16 ... 23
- */
-#define COBALT_CPU_IRQ MIPS_CPU_IRQ_BASE
-
-#define COBALT_GALILEO_IRQ (COBALT_CPU_IRQ + 2)
-#define COBALT_RAQ_SCSI_IRQ (COBALT_CPU_IRQ + 3)
-#define COBALT_ETH0_IRQ (COBALT_CPU_IRQ + 3)
-#define COBALT_QUBE1_ETH0_IRQ (COBALT_CPU_IRQ + 4)
-#define COBALT_ETH1_IRQ (COBALT_CPU_IRQ + 4)
-#define COBALT_SERIAL_IRQ (COBALT_CPU_IRQ + 5)
-#define COBALT_SCSI_IRQ (COBALT_CPU_IRQ + 5)
-#define COBALT_VIA_IRQ (COBALT_CPU_IRQ + 6) /* Chained to VIA ISA bridge */
-
/*
* PCI configuration space manifest constants. These are wired into
* the board layout according to the PCI spec to enable the software
diff --git a/include/asm-mips/mach-cobalt/irq.h b/include/asm-mips/mach-cobalt/irq.h
new file mode 100644
index 00000000000..179d0e850b5
--- /dev/null
+++ b/include/asm-mips/mach-cobalt/irq.h
@@ -0,0 +1,58 @@
+/*
+ * Cobalt IRQ definitions.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1997 Cobalt Microserver
+ * Copyright (C) 1997, 2003 Ralf Baechle
+ * Copyright (C) 2001-2003 Liam Davies (ldavies@agile.tv)
+ * Copyright (C) 2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
+ */
+#ifndef _ASM_COBALT_IRQ_H
+#define _ASM_COBALT_IRQ_H
+
+/*
+ * i8259 interrupts used on Cobalt:
+ *
+ * 8 - RTC
+ * 9 - PCI slot
+ * 14 - IDE0
+ * 15 - IDE1(no connector on board)
+ */
+#define I8259A_IRQ_BASE 0
+
+#define PCISLOT_IRQ (I8259A_IRQ_BASE + 9)
+
+/*
+ * CPU interrupts used on Cobalt:
+ *
+ * 0 - Software interrupt 0 (unused)
+ * 1 - Software interrupt 0 (unused)
+ * 2 - cascade GT64111
+ * 3 - ethernet or SCSI host controller
+ * 4 - ethernet
+ * 5 - 16550 UART
+ * 6 - cascade i8259
+ * 7 - CP0 counter (unused)
+ */
+#define MIPS_CPU_IRQ_BASE 16
+
+#define GT641XX_CASCADE_IRQ (MIPS_CPU_IRQ_BASE + 2)
+#define RAQ2_SCSI_IRQ (MIPS_CPU_IRQ_BASE + 3)
+#define ETH0_IRQ (MIPS_CPU_IRQ_BASE + 3)
+#define QUBE1_ETH0_IRQ (MIPS_CPU_IRQ_BASE + 4)
+#define ETH1_IRQ (MIPS_CPU_IRQ_BASE + 4)
+#define SERIAL_IRQ (MIPS_CPU_IRQ_BASE + 5)
+#define SCSI_IRQ (MIPS_CPU_IRQ_BASE + 5)
+#define I8259_CASCADE_IRQ (MIPS_CPU_IRQ_BASE + 6)
+
+
+#define GT641XX_IRQ_BASE 24
+
+#include <asm/irq_gt641xx.h>
+
+#define NR_IRQS (GT641XX_PCI_INT3_IRQ + 1)
+
+#endif /* _ASM_COBALT_IRQ_H */