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authorJoe Perches <joe@perches.com>2008-02-03 16:57:20 +0200
committerAdrian Bunk <bunk@kernel.org>2008-02-03 16:57:20 +0200
commiteebfa976ad35b1a0debd359f1c4daed3856e21f8 (patch)
tree61a0c6c4ff7185c0d81cbcf5ae24770cca1ee9b7 /include/asm-mips/mach-wrppmc
parent603e82edf78ad6c0f836023f8db585620211947b (diff)
include/asm-mips/: Spelling fixes
Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: Adrian Bunk <bunk@kernel.org>
Diffstat (limited to 'include/asm-mips/mach-wrppmc')
-rw-r--r--include/asm-mips/mach-wrppmc/mach-gt64120.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/include/asm-mips/mach-wrppmc/mach-gt64120.h b/include/asm-mips/mach-wrppmc/mach-gt64120.h
index 00d8bf6164a..83746b84a5e 100644
--- a/include/asm-mips/mach-wrppmc/mach-gt64120.h
+++ b/include/asm-mips/mach-wrppmc/mach-gt64120.h
@@ -45,7 +45,7 @@
#define GT_PCI_IO_SIZE 0x02000000UL
/*
- * PCI interrupts will come in on either the INTA or INTD interrups lines,
+ * PCI interrupts will come in on either the INTA or INTD interrupt lines,
* which are mapped to the #2 and #5 interrupt pins of the MIPS. On our
* boards, they all either come in on IntD or they all come in on IntA, they
* aren't mixed. There can be numerous PCI interrupts, so we keep a list of the