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authorAtsushi Nemoto <anemo@mba.ocn.ne.jp>2006-05-23 00:47:41 +0900
committerRalf Baechle <ralf@linux-mips.org>2006-06-19 17:39:13 +0100
commitc138e12f3a2e0421a4c8edf02587d2d394418679 (patch)
tree66abbf27cbfc9030958b469aa4d826242417a752 /include/asm-mips
parent734996820fd02b52a3fa0fcc09bdb914934bea4c (diff)
[MIPS] Fix fpu_save_double on 64-bit.
> Without this fix, _save_fp() in 64-bit kernel is seriously broken. > > ffffffff8010bec0 <_save_fp>: > ffffffff8010bec0: 400d6000 mfc0 t1,c0_status > ffffffff8010bec4: 000c7140 sll t2,t0,0x5 > ffffffff8010bec8: 05c10011 bgez t2,ffffffff8010bf10 <_save_fp+0x50> > ffffffff8010becc: 00000000 nop > ffffffff8010bed0: f4810328 sdc1 $f1,808(a0) > ... Fix register usage in fpu_save_double() and make fpu_restore_double() more symmetric with fpu_save_double(). Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips')
-rw-r--r--include/asm-mips/asmmacro-32.h4
-rw-r--r--include/asm-mips/asmmacro-64.h19
2 files changed, 11 insertions, 12 deletions
diff --git a/include/asm-mips/asmmacro-32.h b/include/asm-mips/asmmacro-32.h
index 11daf5ceb7b..5de3963f511 100644
--- a/include/asm-mips/asmmacro-32.h
+++ b/include/asm-mips/asmmacro-32.h
@@ -12,7 +12,7 @@
#include <asm/fpregdef.h>
#include <asm/mipsregs.h>
- .macro fpu_save_double thread status tmp1=t0 tmp2
+ .macro fpu_save_double thread status tmp1=t0
cfc1 \tmp1, fcr31
sdc1 $f0, THREAD_FPR0(\thread)
sdc1 $f2, THREAD_FPR2(\thread)
@@ -70,7 +70,7 @@
sw \tmp, THREAD_FCR31(\thread)
.endm
- .macro fpu_restore_double thread tmp=t0
+ .macro fpu_restore_double thread status tmp=t0
lw \tmp, THREAD_FCR31(\thread)
ldc1 $f0, THREAD_FPR0(\thread)
ldc1 $f2, THREAD_FPR2(\thread)
diff --git a/include/asm-mips/asmmacro-64.h b/include/asm-mips/asmmacro-64.h
index 559c355b9b8..225feefcb25 100644
--- a/include/asm-mips/asmmacro-64.h
+++ b/include/asm-mips/asmmacro-64.h
@@ -53,12 +53,12 @@
sdc1 $f31, THREAD_FPR31(\thread)
.endm
- .macro fpu_save_double thread status tmp1 tmp2
- sll \tmp2, \tmp1, 5
- bgez \tmp2, 2f
+ .macro fpu_save_double thread status tmp
+ sll \tmp, \status, 5
+ bgez \tmp, 2f
fpu_save_16odd \thread
2:
- fpu_save_16even \thread \tmp1 # clobbers t1
+ fpu_save_16even \thread \tmp
.endm
.macro fpu_restore_16even thread tmp=t0
@@ -101,13 +101,12 @@
ldc1 $f31, THREAD_FPR31(\thread)
.endm
- .macro fpu_restore_double thread tmp
- mfc0 t0, CP0_STATUS
- sll t1, t0, 5
- bgez t1, 1f # 16 register mode?
+ .macro fpu_restore_double thread status tmp
+ sll \tmp, \status, 5
+ bgez \tmp, 1f # 16 register mode?
- fpu_restore_16odd a0
-1: fpu_restore_16even a0, t0 # clobbers t0
+ fpu_restore_16odd \thread
+1: fpu_restore_16even \thread \tmp
.endm
.macro cpu_save_nonscratch thread