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authorChris Dearman <chris@mips.com>2007-05-08 14:05:39 +0100
committerRalf Baechle <ralf@linux-mips.org>2007-05-11 14:28:31 +0100
commitd725cf3818b12a17d78b87a2de19e8eec17126ae (patch)
tree9d200020488b886201771bd6516c63ef43397baa /include/asm-mips
parentef300e42234eac066b193c871714203d999b481c (diff)
[MIPS] MT: Reenable EIC support and add support for SOCit SC.
Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips')
-rw-r--r--include/asm-mips/mips-boards/malta.h4
-rw-r--r--include/asm-mips/msc01_ic.h5
2 files changed, 5 insertions, 4 deletions
diff --git a/include/asm-mips/mips-boards/malta.h b/include/asm-mips/mips-boards/malta.h
index b0ba3c5a921..eec91001bb6 100644
--- a/include/asm-mips/mips-boards/malta.h
+++ b/include/asm-mips/mips-boards/malta.h
@@ -25,6 +25,10 @@
#include <asm/mips-boards/msc01_pci.h>
#include <asm/gt64120.h>
+/* Mips interrupt controller found in SOCit variations */
+#define MIPS_MSC01_IC_REG_BASE 0x1bc40000
+#define MIPS_SOCITSC_IC_REG_BASE 0x1ffa0000
+
/*
* Malta I/O ports base address for the Galileo GT64120 and Algorithmics
* Bonito system controllers.
diff --git a/include/asm-mips/msc01_ic.h b/include/asm-mips/msc01_ic.h
index aa7ad9a7176..7989b9ffc1d 100644
--- a/include/asm-mips/msc01_ic.h
+++ b/include/asm-mips/msc01_ic.h
@@ -94,10 +94,7 @@
/*
* MIPS System controller interrupt register base.
*
- * FIXME - are these macros specific to Malta and co or to the MSC? If the
- * latter, they should be moved elsewhere.
*/
-#define MIPS_MSC01_IC_REG_BASE 0x1bc40000
/*****************************************************************************
* Absolute register addresses
@@ -144,7 +141,7 @@ typedef struct msc_irqmap {
#define MSC01_IRQ_LEVEL 0
#define MSC01_IRQ_EDGE 1
-extern void __init init_msc_irqs(unsigned int base, msc_irqmap_t *imp, int nirq);
+extern void __init init_msc_irqs(unsigned long icubase, unsigned int base, msc_irqmap_t *imp, int nirq);
extern void ll_msc_irq(void);
#endif /* __ASM_MIPS_BOARDS_MSC01_IC_H */