Merge branch 'linus' into cpus4096

Conflicts:

	drivers/acpi/processor_throttling.c

Signed-off-by: Ingo Molnar <mingo@elte.hu>

74 files changed, 0 insertions, 16825 deletions

diff --git a/include/asm-ppc/8xx_immap.h b/include/asm-ppc/8xx_immap.h
deleted file mode 100644
index 4b0e1520600..00000000000
--- a/include/asm-ppc/8xx_immap.h
+++ /dev/null
@@ -1,564 +0,0 @@
-/*
- * MPC8xx Internal Memory Map
- * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
- *
- * The I/O on the MPC860 is comprised of blocks of special registers
- * and the dual port ram for the Communication Processor Module.
- * Within this space are functional units such as the SIU, memory
- * controller, system timers, and other control functions.  It is
- * a combination that I found difficult to separate into logical
- * functional files.....but anyone else is welcome to try.  -- Dan
- */
-#ifdef __KERNEL__
-#ifndef __IMMAP_8XX__
-#define __IMMAP_8XX__
-
-/* System configuration registers.
-*/
-typedef	struct sys_conf {
-	uint	sc_siumcr;
-	uint	sc_sypcr;
-	uint	sc_swt;
-	char	res1[2];
-	ushort	sc_swsr;
-	uint	sc_sipend;
-	uint	sc_simask;
-	uint	sc_siel;
-	uint	sc_sivec;
-	uint	sc_tesr;
-	char	res2[0xc];
-	uint	sc_sdcr;
-	char	res3[0x4c];
-} sysconf8xx_t;
-
-/* PCMCIA configuration registers.
-*/
-typedef struct pcmcia_conf {
-	uint	pcmc_pbr0;
-	uint	pcmc_por0;
-	uint	pcmc_pbr1;
-	uint	pcmc_por1;
-	uint	pcmc_pbr2;
-	uint	pcmc_por2;
-	uint	pcmc_pbr3;
-	uint	pcmc_por3;
-	uint	pcmc_pbr4;
-	uint	pcmc_por4;
-	uint	pcmc_pbr5;
-	uint	pcmc_por5;
-	uint	pcmc_pbr6;
-	uint	pcmc_por6;
-	uint	pcmc_pbr7;
-	uint	pcmc_por7;
-	char	res1[0x20];
-	uint	pcmc_pgcra;
-	uint	pcmc_pgcrb;
-	uint	pcmc_pscr;
-	char	res2[4];
-	uint	pcmc_pipr;
-	char	res3[4];
-	uint	pcmc_per;
-	char	res4[4];
-} pcmconf8xx_t;
-
-/* Memory controller registers.
-*/
-typedef struct	mem_ctlr {
-	uint	memc_br0;
-	uint	memc_or0;
-	uint	memc_br1;
-	uint	memc_or1;
-	uint	memc_br2;
-	uint	memc_or2;
-	uint	memc_br3;
-	uint	memc_or3;
-	uint	memc_br4;
-	uint	memc_or4;
-	uint	memc_br5;
-	uint	memc_or5;
-	uint	memc_br6;
-	uint	memc_or6;
-	uint	memc_br7;
-	uint	memc_or7;
-	char	res1[0x24];
-	uint	memc_mar;
-	uint	memc_mcr;
-	char	res2[4];
-	uint	memc_mamr;
-	uint	memc_mbmr;
-	ushort	memc_mstat;
-	ushort	memc_mptpr;
-	uint	memc_mdr;
-	char	res3[0x80];
-} memctl8xx_t;
-
-/*-----------------------------------------------------------------------
- * BR - Memory Controler: Base Register					16-9
- */
-#define BR_BA_MSK	0xffff8000	/* Base Address Mask			*/
-#define BR_AT_MSK	0x00007000	/* Address Type Mask			*/
-#define BR_PS_MSK	0x00000c00	/* Port Size Mask			*/
-#define BR_PS_32	0x00000000	/* 32 bit port size			*/
-#define BR_PS_16	0x00000800	/* 16 bit port size			*/
-#define BR_PS_8		0x00000400	/*  8 bit port size			*/
-#define BR_PARE		0x00000200	/* Parity Enable			*/
-#define BR_WP		0x00000100	/* Write Protect			*/
-#define BR_MS_MSK	0x000000c0	/* Machine Select Mask			*/
-#define BR_MS_GPCM	0x00000000	/* G.P.C.M. Machine Select		*/
-#define BR_MS_UPMA	0x00000080	/* U.P.M.A Machine Select		*/
-#define BR_MS_UPMB	0x000000c0	/* U.P.M.B Machine Select		*/
-#define BR_V		0x00000001	/* Bank Valid				*/
-
-/*-----------------------------------------------------------------------
- * OR - Memory Controler: Option Register				16-11
- */
-#define OR_AM_MSK	0xffff8000	/* Address Mask Mask			*/
-#define OR_ATM_MSK	0x00007000	/* Address Type Mask Mask		*/
-#define OR_CSNT_SAM	0x00000800	/* Chip Select Negation Time/ Start	*/
-					/* Address Multiplex			*/
-#define OR_ACS_MSK	0x00000600	/* Address to Chip Select Setup mask	*/
-#define OR_ACS_DIV1	0x00000000	/* CS is output at the same time	*/
-#define OR_ACS_DIV4	0x00000400	/* CS is output 1/4 a clock later	*/
-#define OR_ACS_DIV2	0x00000600	/* CS is output 1/2 a clock later	*/
-#define OR_G5LA		0x00000400	/* Output #GPL5 on #GPL_A5		*/
-#define OR_G5LS		0x00000200	/* Drive #GPL high on falling edge of...*/
-#define OR_BI		0x00000100	/* Burst inhibit			*/
-#define OR_SCY_MSK	0x000000f0	/* Cycle Length in Clocks		*/
-#define OR_SCY_0_CLK	0x00000000	/* 0 clock cycles wait states		*/
-#define OR_SCY_1_CLK	0x00000010	/* 1 clock cycles wait states		*/
-#define OR_SCY_2_CLK	0x00000020	/* 2 clock cycles wait states		*/
-#define OR_SCY_3_CLK	0x00000030	/* 3 clock cycles wait states		*/
-#define OR_SCY_4_CLK	0x00000040	/* 4 clock cycles wait states		*/
-#define OR_SCY_5_CLK	0x00000050	/* 5 clock cycles wait states		*/
-#define OR_SCY_6_CLK	0x00000060	/* 6 clock cycles wait states		*/
-#define OR_SCY_7_CLK	0x00000070	/* 7 clock cycles wait states		*/
-#define OR_SCY_8_CLK	0x00000080	/* 8 clock cycles wait states		*/
-#define OR_SCY_9_CLK	0x00000090	/* 9 clock cycles wait states		*/
-#define OR_SCY_10_CLK	0x000000a0	/* 10 clock cycles wait states		*/
-#define OR_SCY_11_CLK	0x000000b0	/* 11 clock cycles wait states		*/
-#define OR_SCY_12_CLK	0x000000c0	/* 12 clock cycles wait states		*/
-#define OR_SCY_13_CLK	0x000000d0	/* 13 clock cycles wait states		*/
-#define OR_SCY_14_CLK	0x000000e0	/* 14 clock cycles wait states		*/
-#define OR_SCY_15_CLK	0x000000f0	/* 15 clock cycles wait states		*/
-#define OR_SETA		0x00000008	/* External Transfer Acknowledge	*/
-#define OR_TRLX		0x00000004	/* Timing Relaxed			*/
-#define OR_EHTR		0x00000002	/* Extended Hold Time on Read		*/
-
-/* System Integration Timers.
-*/
-typedef struct	sys_int_timers {
-	ushort	sit_tbscr;
-	char	res0[0x02];
-	uint	sit_tbreff0;
-	uint	sit_tbreff1;
-	char	res1[0x14];
-	ushort	sit_rtcsc;
-	char	res2[0x02];
-	uint	sit_rtc;
-	uint	sit_rtsec;
-	uint	sit_rtcal;
-	char	res3[0x10];
-	ushort	sit_piscr;
-	char	res4[2];
-	uint	sit_pitc;
-	uint	sit_pitr;
-	char	res5[0x34];
-} sit8xx_t;
-
-#define TBSCR_TBIRQ_MASK	((ushort)0xff00)
-#define TBSCR_REFA		((ushort)0x0080)
-#define TBSCR_REFB		((ushort)0x0040)
-#define TBSCR_REFAE		((ushort)0x0008)
-#define TBSCR_REFBE		((ushort)0x0004)
-#define TBSCR_TBF		((ushort)0x0002)
-#define TBSCR_TBE		((ushort)0x0001)
-
-#define RTCSC_RTCIRQ_MASK	((ushort)0xff00)
-#define RTCSC_SEC		((ushort)0x0080)
-#define RTCSC_ALR		((ushort)0x0040)
-#define RTCSC_38K		((ushort)0x0010)
-#define RTCSC_SIE		((ushort)0x0008)
-#define RTCSC_ALE		((ushort)0x0004)
-#define RTCSC_RTF		((ushort)0x0002)
-#define RTCSC_RTE		((ushort)0x0001)
-
-#define PISCR_PIRQ_MASK		((ushort)0xff00)
-#define PISCR_PS		((ushort)0x0080)
-#define PISCR_PIE		((ushort)0x0004)
-#define PISCR_PTF		((ushort)0x0002)
-#define PISCR_PTE		((ushort)0x0001)
-
-/* Clocks and Reset.
-*/
-typedef struct clk_and_reset {
-	uint	car_sccr;
-	uint	car_plprcr;
-	uint	car_rsr;
-	char	res[0x74];        /* Reserved area                  */
-} car8xx_t;
-
-/* System Integration Timers keys.
-*/
-typedef struct sitk {
-	uint	sitk_tbscrk;
-	uint	sitk_tbreff0k;
-	uint	sitk_tbreff1k;
-	uint	sitk_tbk;
-	char	res1[0x10];
-	uint	sitk_rtcsck;
-	uint	sitk_rtck;
-	uint	sitk_rtseck;
-	uint	sitk_rtcalk;
-	char	res2[0x10];
-	uint	sitk_piscrk;
-	uint	sitk_pitck;
-	char	res3[0x38];
-} sitk8xx_t;
-
-/* Clocks and reset keys.
-*/
-typedef struct cark {
-	uint	cark_sccrk;
-	uint	cark_plprcrk;
-	uint	cark_rsrk;
-	char	res[0x474];
-} cark8xx_t;
-
-/* The key to unlock registers maintained by keep-alive power.
-*/
-#define KAPWR_KEY	((unsigned int)0x55ccaa33)
-
-/* Video interface.  MPC823 Only.
-*/
-typedef struct vid823 {
-	ushort	vid_vccr;
-	ushort	res1;
-	u_char	vid_vsr;
-	u_char	res2;
-	u_char	vid_vcmr;
-	u_char	res3;
-	uint	vid_vbcb;
-	uint	res4;
-	uint	vid_vfcr0;
-	uint	vid_vfaa0;
-	uint	vid_vfba0;
-	uint	vid_vfcr1;
-	uint	vid_vfaa1;
-	uint	vid_vfba1;
-	u_char	res5[0x18];
-} vid823_t;
-
-/* LCD interface.  823 Only.
-*/
-typedef struct lcd {
-	uint	lcd_lccr;
-	uint	lcd_lchcr;
-	uint	lcd_lcvcr;
-	char	res1[4];
-	uint	lcd_lcfaa;
-	uint	lcd_lcfba;
-	char	lcd_lcsr;
-	char	res2[0x7];
-} lcd823_t;
-
-/* I2C
-*/
-typedef struct i2c {
-	u_char	i2c_i2mod;
-	char	res1[3];
-	u_char	i2c_i2add;
-	char	res2[3];
-	u_char	i2c_i2brg;
-	char	res3[3];
-	u_char	i2c_i2com;
-	char	res4[3];
-	u_char	i2c_i2cer;
-	char	res5[3];
-	u_char	i2c_i2cmr;
-	char	res6[0x8b];
-} i2c8xx_t;
-
-/* DMA control/status registers.
-*/
-typedef struct sdma_csr {
-	char	res1[4];
-	uint	sdma_sdar;
-	u_char	sdma_sdsr;
-	char	res3[3];
-	u_char	sdma_sdmr;
-	char	res4[3];
-	u_char	sdma_idsr1;
-	char	res5[3];
-	u_char	sdma_idmr1;
-	char	res6[3];
-	u_char	sdma_idsr2;
-	char	res7[3];
-	u_char	sdma_idmr2;
-	char	res8[0x13];
-} sdma8xx_t;
-
-/* Communication Processor Module Interrupt Controller.
-*/
-typedef struct cpm_ic {
-	ushort	cpic_civr;
-	char	res[0xe];
-	uint	cpic_cicr;
-	uint	cpic_cipr;
-	uint	cpic_cimr;
-	uint	cpic_cisr;
-} cpic8xx_t;
-
-/* Input/Output Port control/status registers.
-*/
-typedef struct io_port {
-	ushort	iop_padir;
-	ushort	iop_papar;
-	ushort	iop_paodr;
-	ushort	iop_padat;
-	char	res1[8];
-	ushort	iop_pcdir;
-	ushort	iop_pcpar;
-	ushort	iop_pcso;
-	ushort	iop_pcdat;
-	ushort	iop_pcint;
-	char	res2[6];
-	ushort	iop_pddir;
-	ushort	iop_pdpar;
-	char	res3[2];
-	ushort	iop_pddat;
-	uint	utmode;
-	char	res4[4];
-} iop8xx_t;
-
-/* Communication Processor Module Timers
-*/
-typedef struct cpm_timers {
-	ushort	cpmt_tgcr;
-	char	res1[0xe];
-	ushort	cpmt_tmr1;
-	ushort	cpmt_tmr2;
-	ushort	cpmt_trr1;
-	ushort	cpmt_trr2;
-	ushort	cpmt_tcr1;
-	ushort	cpmt_tcr2;
-	ushort	cpmt_tcn1;
-	ushort	cpmt_tcn2;
-	ushort	cpmt_tmr3;
-	ushort	cpmt_tmr4;
-	ushort	cpmt_trr3;
-	ushort	cpmt_trr4;
-	ushort	cpmt_tcr3;
-	ushort	cpmt_tcr4;
-	ushort	cpmt_tcn3;
-	ushort	cpmt_tcn4;
-	ushort	cpmt_ter1;
-	ushort	cpmt_ter2;
-	ushort	cpmt_ter3;
-	ushort	cpmt_ter4;
-	char	res2[8];
-} cpmtimer8xx_t;
-
-/* Finally, the Communication Processor stuff.....
-*/
-typedef struct scc {		/* Serial communication channels */
-	uint	scc_gsmrl;
-	uint	scc_gsmrh;
-	ushort	scc_psmr;
-	char	res1[2];
-	ushort	scc_todr;
-	ushort	scc_dsr;
-	ushort	scc_scce;
-	char	res2[2];
-	ushort	scc_sccm;
-	char	res3;
-	u_char	scc_sccs;
-	char	res4[8];
-} scc_t;
-
-typedef struct smc {		/* Serial management channels */
-	char	res1[2];
-	ushort	smc_smcmr;
-	char	res2[2];
-	u_char	smc_smce;
-	char	res3[3];
-	u_char	smc_smcm;
-	char	res4[5];
-} smc_t;
-
-/* MPC860T Fast Ethernet Controller.  It isn't part of the CPM, but
- * it fits within the address space.
- */
-
-typedef struct fec {
-	uint	fec_addr_low;		/* lower 32 bits of station address	*/
-	ushort	fec_addr_high;		/* upper 16 bits of station address	*/
-	ushort	res1;			/* reserved				*/
-	uint	fec_hash_table_high;	/* upper 32-bits of hash table		*/
-	uint	fec_hash_table_low;	/* lower 32-bits of hash table		*/
-	uint	fec_r_des_start;	/* beginning of Rx descriptor ring	*/
-	uint	fec_x_des_start;	/* beginning of Tx descriptor ring	*/
-	uint	fec_r_buff_size;	/* Rx buffer size			*/
-	uint	res2[9];		/* reserved				*/
-	uint	fec_ecntrl;		/* ethernet control register		*/
-	uint	fec_ievent;		/* interrupt event register		*/
-	uint	fec_imask;		/* interrupt mask register		*/
-	uint	fec_ivec;		/* interrupt level and vector status	*/
-	uint	fec_r_des_active;	/* Rx ring updated flag			*/
-	uint	fec_x_des_active;	/* Tx ring updated flag			*/
-	uint	res3[10];		/* reserved				*/
-	uint	fec_mii_data;		/* MII data register			*/
-	uint	fec_mii_speed;		/* MII speed control register		*/
-	uint	res4[17];		/* reserved				*/
-	uint	fec_r_bound;		/* end of RAM (read-only)		*/
-	uint	fec_r_fstart;		/* Rx FIFO start address		*/
-	uint	res5[6];		/* reserved				*/
-	uint	fec_x_fstart;		/* Tx FIFO start address		*/
-	uint	res6[17];		/* reserved				*/
-	uint	fec_fun_code;		/* fec SDMA function code		*/
-	uint	res7[3];		/* reserved				*/
-	uint	fec_r_cntrl;		/* Rx control register			*/
-	uint	fec_r_hash;		/* Rx hash register			*/
-	uint	res8[14];		/* reserved				*/
-	uint	fec_x_cntrl;		/* Tx control register			*/
-	uint	res9[0x1e];		/* reserved				*/
-} fec_t;
-
-/* The FEC and LCD color map share the same address space....
- * I guess we will never see an 823T :-).
- */
-union fec_lcd {
-	fec_t	fl_un_fec;
-	u_char	fl_un_cmap[0x200];
-};
-
-typedef struct comm_proc {
-	/* General control and status registers.
-	*/
-	ushort	cp_cpcr;
-	u_char	res1[2];
-	ushort	cp_rccr;
-	u_char	res2;
-	u_char	cp_rmds;
-	u_char	res3[4];
-	ushort	cp_cpmcr1;
-	ushort	cp_cpmcr2;
-	ushort	cp_cpmcr3;
-	ushort	cp_cpmcr4;
-	u_char	res4[2];
-	ushort	cp_rter;
-	u_char	res5[2];
-	ushort	cp_rtmr;
-	u_char	res6[0x14];
-
-	/* Baud rate generators.
-	*/
-	uint	cp_brgc1;
-	uint	cp_brgc2;
-	uint	cp_brgc3;
-	uint	cp_brgc4;
-
-	/* Serial Communication Channels.
-	*/
-	scc_t	cp_scc[4];
-
-	/* Serial Management Channels.
-	*/
-	smc_t	cp_smc[2];
-
-	/* Serial Peripheral Interface.
-	*/
-	ushort	cp_spmode;
-	u_char	res7[4];
-	u_char	cp_spie;
-	u_char	res8[3];
-	u_char	cp_spim;
-	u_char	res9[2];
-	u_char	cp_spcom;
-	u_char	res10[2];
-
-	/* Parallel Interface Port.
-	*/
-	u_char	res11[2];
-	ushort	cp_pipc;
-	u_char	res12[2];
-	ushort	cp_ptpr;
-	uint	cp_pbdir;
-	uint	cp_pbpar;
-	u_char	res13[2];
-	ushort	cp_pbodr;
-	uint	cp_pbdat;
-
-	/* Port E - MPC87x/88x only.
-	 */
-	uint	cp_pedir;
-	uint	cp_pepar;
-	uint	cp_peso;
-	uint	cp_peodr;
-	uint	cp_pedat;
-
-	/* Communications Processor Timing Register -
-	   Contains RMII Timing for the FECs on MPC87x/88x only.
-	*/
-	uint	cp_cptr;
-
-	/* Serial Interface and Time Slot Assignment.
-	*/
-	uint	cp_simode;
-	u_char	cp_sigmr;
-	u_char	res15;
-	u_char	cp_sistr;
-	u_char	cp_sicmr;
-	u_char	res16[4];
-	uint	cp_sicr;
-	uint	cp_sirp;
-	u_char	res17[0xc];
-
-	/* 256 bytes of MPC823 video controller RAM array.
-	*/
-	u_char	cp_vcram[0x100];
-	u_char	cp_siram[0x200];
-
-	/* The fast ethernet controller is not really part of the CPM,
-	 * but it resides in the address space.
-	 * The LCD color map is also here.
-	 */
-	union	fec_lcd	fl_un;
-#define cp_fec		fl_un.fl_un_fec
-#define lcd_cmap	fl_un.fl_un_cmap
-	char	res18[0xE00];
-
-	/* The DUET family has a second FEC here */
-	fec_t	cp_fec2;
-#define cp_fec1	cp_fec	/* consistency macro */
-
-	/* Dual Ported RAM follows.
-	 * There are many different formats for this memory area
-	 * depending upon the devices used and options chosen.
-	 * Some processors don't have all of it populated.
-	 */
-	u_char	cp_dpmem[0x1C00];	/* BD / Data / ucode */
-	u_char	cp_dparam[0x400];	/* Parameter RAM */
-} cpm8xx_t;
-
-/* Internal memory map.
-*/
-typedef struct immap {
-	sysconf8xx_t	im_siu_conf;	/* SIU Configuration */
-	pcmconf8xx_t	im_pcmcia;	/* PCMCIA Configuration */
-	memctl8xx_t	im_memctl;	/* Memory Controller */
-	sit8xx_t	im_sit;		/* System integration timers */
-	car8xx_t	im_clkrst;	/* Clocks and reset */
-	sitk8xx_t	im_sitk;	/* Sys int timer keys */
-	cark8xx_t	im_clkrstk;	/* Clocks and reset keys */
-	vid823_t	im_vid;		/* Video (823 only) */
-	lcd823_t	im_lcd;		/* LCD (823 only) */
-	i2c8xx_t	im_i2c;		/* I2C control/status */
-	sdma8xx_t	im_sdma;	/* SDMA control/status */
-	cpic8xx_t	im_cpic;	/* CPM Interrupt Controller */
-	iop8xx_t	im_ioport;	/* IO Port control/status */
-	cpmtimer8xx_t	im_cpmtimer;	/* CPM timers */
-	cpm8xx_t	im_cpm;		/* Communication processor */
-} immap_t;
-
-#endif /* __IMMAP_8XX__ */
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/amigayle.h b/include/asm-ppc/amigayle.h
deleted file mode 100644
index 1fe0b87859b..00000000000
--- a/include/asm-ppc/amigayle.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-m68k/amigayle.h>
diff --git a/include/asm-ppc/amipcmcia.h b/include/asm-ppc/amipcmcia.h
deleted file mode 100644
index 3f65f63f508..00000000000
--- a/include/asm-ppc/amipcmcia.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-m68k/amipcmcia.h>
diff --git a/include/asm-ppc/bootinfo.h b/include/asm-ppc/bootinfo.h
deleted file mode 100644
index f6ed77aee32..00000000000
--- a/include/asm-ppc/bootinfo.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * Non-machine dependent bootinfo structure.  Basic idea
- * borrowed from the m68k.
- *
- * Copyright (C) 1999 Cort Dougan <cort@ppc.kernel.org>
- */
-
-#ifdef __KERNEL__
-#ifndef _PPC_BOOTINFO_H
-#define _PPC_BOOTINFO_H
-
-#include <asm/page.h>
-
-struct bi_record {
-	unsigned long tag;		/* tag ID */
-	unsigned long size;		/* size of record (in bytes) */
-	unsigned long data[0];		/* data */
-};
-
-#define BI_FIRST		0x1010  /* first record - marker */
-#define BI_LAST			0x1011	/* last record - marker */
-#define BI_CMD_LINE		0x1012
-#define BI_BOOTLOADER_ID	0x1013
-#define BI_INITRD		0x1014
-#define BI_SYSMAP		0x1015
-#define BI_MACHTYPE		0x1016
-#define BI_MEMSIZE		0x1017
-#define BI_BOARD_INFO		0x1018
-
-extern struct bi_record *find_bootinfo(void);
-extern void bootinfo_init(struct bi_record *rec);
-extern void bootinfo_append(unsigned long tag, unsigned long size, void * data);
-extern void parse_bootinfo(struct bi_record *rec);
-extern unsigned long boot_mem_size;
-
-static inline struct bi_record *
-bootinfo_addr(unsigned long offset)
-{
-
-	return (struct bi_record *)_ALIGN((offset) + (1 << 20) - 1,
-					  (1 << 20));
-}
-
-
-#endif /* _PPC_BOOTINFO_H */
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/bootx.h b/include/asm-ppc/bootx.h
deleted file mode 100644
index b0c51b45d7a..00000000000
--- a/include/asm-ppc/bootx.h
+++ /dev/null
@@ -1,135 +0,0 @@
-/*
- * This file describes the structure passed from the BootX application
- * (for MacOS) when it is used to boot Linux.
- *
- * Written by Benjamin Herrenschmidt.
- */
-
-
-#ifndef __ASM_BOOTX_H__
-#define __ASM_BOOTX_H__
-
-#ifdef macintosh
-#include <Types.h>
-#include "linux_type_defs.h"
-#endif
-
-#ifdef macintosh
-/* All this requires PowerPC alignment */
-#pragma options align=power
-#endif
-
-/* On kernel entry:
- *
- * r3 = 0x426f6f58    ('BooX')
- * r4 = pointer to boot_infos
- * r5 = NULL
- *
- * Data and instruction translation disabled, interrupts
- * disabled, kernel loaded at physical 0x00000000 on PCI
- * machines (will be different on NuBus).
- */
-
-#define BOOT_INFO_VERSION               5
-#define BOOT_INFO_COMPATIBLE_VERSION    1
-
-/* Bit in the architecture flag mask. More to be defined in
-   future versions. Note that either BOOT_ARCH_PCI or
-   BOOT_ARCH_NUBUS is set. The other BOOT_ARCH_NUBUS_xxx are
-   set additionally when BOOT_ARCH_NUBUS is set.
- */
-#define BOOT_ARCH_PCI                   0x00000001UL
-#define BOOT_ARCH_NUBUS                 0x00000002UL
-#define BOOT_ARCH_NUBUS_PDM             0x00000010UL
-#define BOOT_ARCH_NUBUS_PERFORMA        0x00000020UL
-#define BOOT_ARCH_NUBUS_POWERBOOK       0x00000040UL
-
-/*  Maximum number of ranges in phys memory map */
-#define MAX_MEM_MAP_SIZE				26
-
-/* This is the format of an element in the physical memory map. Note that
-   the map is optional and current BootX will only build it for pre-PCI
-   machines */
-typedef struct boot_info_map_entry
-{
-    __u32       physAddr;                /* Physical starting address */
-    __u32       size;                    /* Size in bytes */
-} boot_info_map_entry_t;
-
-
-/* Here are the boot informations that are passed to the bootstrap
- * Note that the kernel arguments and the device tree are appended
- * at the end of this structure. */
-typedef struct boot_infos
-{
-    /* Version of this structure */
-    __u32       version;
-    /* backward compatible down to version: */
-    __u32       compatible_version;
-
-    /* NEW (vers. 2) this holds the current _logical_ base addr of
-       the frame buffer (for use by early boot message) */
-    __u8*       logicalDisplayBase;
-
-    /* NEW (vers. 4) Apple's machine identification */
-    __u32       machineID;
-
-    /* NEW (vers. 4) Detected hw architecture */
-    __u32       architecture;
-
-    /* The device tree (internal addresses relative to the beginning of the tree,
-     * device tree offset relative to the beginning of this structure).
-     * On pre-PCI macintosh (BOOT_ARCH_PCI bit set to 0 in architecture), this
-     * field is 0.
-     */
-    __u32       deviceTreeOffset;        /* Device tree offset */
-    __u32       deviceTreeSize;          /* Size of the device tree */
-
-    /* Some infos about the current MacOS display */
-    __u32       dispDeviceRect[4];       /* left,top,right,bottom */
-    __u32       dispDeviceDepth;         /* (8, 16 or 32) */
-    __u8*       dispDeviceBase;          /* base address (physical) */
-    __u32       dispDeviceRowBytes;      /* rowbytes (in bytes) */
-    __u32       dispDeviceColorsOffset;  /* Colormap (8 bits only) or 0 (*) */
-    /* Optional offset in the registry to the current
-     * MacOS display. (Can be 0 when not detected) */
-     __u32      dispDeviceRegEntryOffset;
-
-    /* Optional pointer to boot ramdisk (offset from this structure) */
-    __u32       ramDisk;
-    __u32       ramDiskSize;             /* size of ramdisk image */
-
-    /* Kernel command line arguments (offset from this structure) */
-    __u32       kernelParamsOffset;
-
-    /* ALL BELOW NEW (vers. 4) */
-
-    /* This defines the physical memory. Valid with BOOT_ARCH_NUBUS flag
-       (non-PCI) only. On PCI, memory is contiguous and it's size is in the
-       device-tree. */
-    boot_info_map_entry_t
-    	        physMemoryMap[MAX_MEM_MAP_SIZE]; /* Where the phys memory is */
-    __u32       physMemoryMapSize;               /* How many entries in map */
-
-
-    /* The framebuffer size (optional, currently 0) */
-    __u32       frameBufferSize;         /* Represents a max size, can be 0. */
-
-    /* NEW (vers. 5) */
-
-    /* Total params size (args + colormap + device tree + ramdisk) */
-    __u32       totalParamsSize;
-
-} boot_infos_t;
-
-/* (*) The format of the colormap is 256 * 3 * 2 bytes. Each color index is represented
- * by 3 short words containing a 16 bits (unsigned) color component.
- * Later versions may contain the gamma table for direct-color devices here.
- */
-#define BOOTX_COLORTABLE_SIZE    (256UL*3UL*2UL)
-
-#ifdef macintosh
-#pragma options align=reset
-#endif
-
-#endif
diff --git a/include/asm-ppc/btext.h b/include/asm-ppc/btext.h
deleted file mode 100644
index ed3630251b3..00000000000
--- a/include/asm-ppc/btext.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * Definitions for using the procedures in btext.c.
- *
- * Benjamin Herrenschmidt <benh@kernel.crashing.org>
- */
-#ifndef __PPC_BTEXT_H
-#define __PPC_BTEXT_H
-#ifdef __KERNEL__
-
-#include <asm/bootx.h>
-
-extern void btext_clearscreen(void);
-extern void btext_flushscreen(void);
-
-extern unsigned long disp_BAT[2];
-
-extern boot_infos_t disp_bi;
-extern int boot_text_mapped;
-
-extern void btext_init(boot_infos_t *bi);
-extern void btext_welcome(void);
-extern void btext_prepare_BAT(void);
-extern void btext_setup_display(int width, int height, int depth, int pitch,
-				unsigned long address);
-extern void map_boot_text(void);
-extern void btext_update_display(unsigned long phys, int width, int height,
-				 int depth, int pitch);
-
-extern void btext_drawchar(char c);
-extern void btext_drawstring(const char *str);
-extern void btext_drawhex(unsigned long v);
-
-#endif /* __KERNEL__ */
-#endif /* __PPC_BTEXT_H */
diff --git a/include/asm-ppc/cpm1.h b/include/asm-ppc/cpm1.h
deleted file mode 100644
index 03035acd85c..00000000000
--- a/include/asm-ppc/cpm1.h
+++ /dev/null
@@ -1,688 +0,0 @@
-/*
- * MPC8xx Communication Processor Module.
- * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
- *
- * This file contains structures and information for the communication
- * processor channels.  Some CPM control and status is available
- * throught the MPC8xx internal memory map.  See immap.h for details.
- * This file only contains what I need for the moment, not the total
- * CPM capabilities.  I (or someone else) will add definitions as they
- * are needed.  -- Dan
- *
- * On the MBX board, EPPC-Bug loads CPM microcode into the first 512
- * bytes of the DP RAM and relocates the I2C parameter area to the
- * IDMA1 space.  The remaining DP RAM is available for buffer descriptors
- * or other use.
- */
-#ifndef __CPM1__
-#define __CPM1__
-
-#include <asm/8xx_immap.h>
-#include <asm/ptrace.h>
-
-/* CPM Command register.
-*/
-#define CPM_CR_RST	((ushort)0x8000)
-#define CPM_CR_OPCODE	((ushort)0x0f00)
-#define CPM_CR_CHAN	((ushort)0x00f0)
-#define CPM_CR_FLG	((ushort)0x0001)
-
-/* Some commands (there are more...later)
-*/
-#define CPM_CR_INIT_TRX		((ushort)0x0000)
-#define CPM_CR_INIT_RX		((ushort)0x0001)
-#define CPM_CR_INIT_TX		((ushort)0x0002)
-#define CPM_CR_HUNT_MODE	((ushort)0x0003)
-#define CPM_CR_STOP_TX		((ushort)0x0004)
-#define CPM_CR_GRA_STOP_TX	((ushort)0x0005)
-#define CPM_CR_RESTART_TX	((ushort)0x0006)
-#define CPM_CR_CLOSE_RX_BD	((ushort)0x0007)
-#define CPM_CR_SET_GADDR	((ushort)0x0008)
-#define CPM_CR_SET_TIMER	CPM_CR_SET_GADDR
-
-/* Channel numbers.
-*/
-#define CPM_CR_CH_SCC1		((ushort)0x0000)
-#define CPM_CR_CH_I2C		((ushort)0x0001)	/* I2C and IDMA1 */
-#define CPM_CR_CH_SCC2		((ushort)0x0004)
-#define CPM_CR_CH_SPI		((ushort)0x0005)	/* SPI / IDMA2 / Timers */
-#define CPM_CR_CH_TIMER		CPM_CR_CH_SPI
-#define CPM_CR_CH_SCC3		((ushort)0x0008)
-#define CPM_CR_CH_SMC1		((ushort)0x0009)	/* SMC1 / DSP1 */
-#define CPM_CR_CH_SCC4		((ushort)0x000c)
-#define CPM_CR_CH_SMC2		((ushort)0x000d)	/* SMC2 / DSP2 */
-
-#define mk_cr_cmd(CH, CMD)	((CMD << 8) | (CH << 4))
-
-/* The dual ported RAM is multi-functional.  Some areas can be (and are
- * being) used for microcode.  There is an area that can only be used
- * as data ram for buffer descriptors, which is all we use right now.
- * Currently the first 512 and last 256 bytes are used for microcode.
- */
-#define CPM_DATAONLY_BASE	((uint)0x0800)
-#define CPM_DATAONLY_SIZE	((uint)0x0700)
-#define CPM_DP_NOSPACE		((uint)0x7fffffff)
-
-/* Export the base address of the communication processor registers
- * and dual port ram.
- */
-extern	cpm8xx_t	*cpmp;		/* Pointer to comm processor */
-extern unsigned long cpm_dpalloc(uint size, uint align);
-extern int cpm_dpfree(unsigned long offset);
-extern unsigned long cpm_dpalloc_fixed(unsigned long offset, uint size, uint align);
-extern void cpm_dpdump(void);
-extern void *cpm_dpram_addr(unsigned long offset);
-extern uint cpm_dpram_phys(u8 *addr);
-extern void cpm_setbrg(uint brg, uint rate);
-
-extern void cpm_load_patch(volatile immap_t *immr);
-
-/* Buffer descriptors used by many of the CPM protocols.
-*/
-typedef struct cpm_buf_desc {
-	ushort	cbd_sc;		/* Status and Control */
-	ushort	cbd_datlen;	/* Data length in buffer */
-	uint	cbd_bufaddr;	/* Buffer address in host memory */
-} cbd_t;
-
-#define BD_SC_EMPTY	((ushort)0x8000)	/* Receive is empty */
-#define BD_SC_READY	((ushort)0x8000)	/* Transmit is ready */
-#define BD_SC_WRAP	((ushort)0x2000)	/* Last buffer descriptor */
-#define BD_SC_INTRPT	((ushort)0x1000)	/* Interrupt on change */
-#define BD_SC_LAST	((ushort)0x0800)	/* Last buffer in frame */
-#define BD_SC_TC	((ushort)0x0400)	/* Transmit CRC */
-#define BD_SC_CM	((ushort)0x0200)	/* Continous mode */
-#define BD_SC_ID	((ushort)0x0100)	/* Rec'd too many idles */
-#define BD_SC_P		((ushort)0x0100)	/* xmt preamble */
-#define BD_SC_BR	((ushort)0x0020)	/* Break received */
-#define BD_SC_FR	((ushort)0x0010)	/* Framing error */
-#define BD_SC_PR	((ushort)0x0008)	/* Parity error */
-#define BD_SC_NAK	((ushort)0x0004)	/* NAK - did not respond */
-#define BD_SC_OV	((ushort)0x0002)	/* Overrun */
-#define BD_SC_UN	((ushort)0x0002)	/* Underrun */
-#define BD_SC_CD	((ushort)0x0001)	/* ?? */
-#define BD_SC_CL	((ushort)0x0001)	/* Collision */
-
-/* Parameter RAM offsets.
-*/
-#define PROFF_SCC1	((uint)0x0000)
-#define PROFF_IIC	((uint)0x0080)
-#define PROFF_SCC2	((uint)0x0100)
-#define PROFF_SPI	((uint)0x0180)
-#define PROFF_SCC3	((uint)0x0200)
-#define PROFF_SMC1	((uint)0x0280)
-#define PROFF_SCC4	((uint)0x0300)
-#define PROFF_SMC2	((uint)0x0380)
-
-/* Define enough so I can at least use the serial port as a UART.
- * The MBX uses SMC1 as the host serial port.
- */
-typedef struct smc_uart {
-	ushort	smc_rbase;	/* Rx Buffer descriptor base address */
-	ushort	smc_tbase;	/* Tx Buffer descriptor base address */
-	u_char	smc_rfcr;	/* Rx function code */
-	u_char	smc_tfcr;	/* Tx function code */
-	ushort	smc_mrblr;	/* Max receive buffer length */
-	uint	smc_rstate;	/* Internal */
-	uint	smc_idp;	/* Internal */
-	ushort	smc_rbptr;	/* Internal */
-	ushort	smc_ibc;	/* Internal */
-	uint	smc_rxtmp;	/* Internal */
-	uint	smc_tstate;	/* Internal */
-	uint	smc_tdp;	/* Internal */
-	ushort	smc_tbptr;	/* Internal */
-	ushort	smc_tbc;	/* Internal */
-	uint	smc_txtmp;	/* Internal */
-	ushort	smc_maxidl;	/* Maximum idle characters */
-	ushort	smc_tmpidl;	/* Temporary idle counter */
-	ushort	smc_brklen;	/* Last received break length */
-	ushort	smc_brkec;	/* rcv'd break condition counter */
-	ushort	smc_brkcr;	/* xmt break count register */
-	ushort	smc_rmask;	/* Temporary bit mask */
-	char	res1[8];	/* Reserved */
-	ushort	smc_rpbase;	/* Relocation pointer */
-} smc_uart_t;
-
-/* Function code bits.
-*/
-#define SMC_EB	((u_char)0x10)	/* Set big endian byte order */
-
-/* SMC uart mode register.
-*/
-#define	SMCMR_REN	((ushort)0x0001)
-#define SMCMR_TEN	((ushort)0x0002)
-#define SMCMR_DM	((ushort)0x000c)
-#define SMCMR_SM_GCI	((ushort)0x0000)
-#define SMCMR_SM_UART	((ushort)0x0020)
-#define SMCMR_SM_TRANS	((ushort)0x0030)
-#define SMCMR_SM_MASK	((ushort)0x0030)
-#define SMCMR_PM_EVEN	((ushort)0x0100)	/* Even parity, else odd */
-#define SMCMR_REVD	SMCMR_PM_EVEN
-#define SMCMR_PEN	((ushort)0x0200)	/* Parity enable */
-#define SMCMR_BS	SMCMR_PEN
-#define SMCMR_SL	((ushort)0x0400)	/* Two stops, else one */
-#define SMCR_CLEN_MASK	((ushort)0x7800)	/* Character length */
-#define smcr_mk_clen(C)	(((C) << 11) & SMCR_CLEN_MASK)
-
-/* SMC2 as Centronics parallel printer.  It is half duplex, in that
- * it can only receive or transmit.  The parameter ram values for
- * each direction are either unique or properly overlap, so we can
- * include them in one structure.
- */
-typedef struct smc_centronics {
-	ushort	scent_rbase;
-	ushort	scent_tbase;
-	u_char	scent_cfcr;
-	u_char	scent_smask;
-	ushort	scent_mrblr;
-	uint	scent_rstate;
-	uint	scent_r_ptr;
-	ushort	scent_rbptr;
-	ushort	scent_r_cnt;
-	uint	scent_rtemp;
-	uint	scent_tstate;
-	uint	scent_t_ptr;
-	ushort	scent_tbptr;
-	ushort	scent_t_cnt;
-	uint	scent_ttemp;
-	ushort	scent_max_sl;
-	ushort	scent_sl_cnt;
-	ushort	scent_character1;
-	ushort	scent_character2;
-	ushort	scent_character3;
-	ushort	scent_character4;
-	ushort	scent_character5;
-	ushort	scent_character6;
-	ushort	scent_character7;
-	ushort	scent_character8;
-	ushort	scent_rccm;
-	ushort	scent_rccr;
-} smc_cent_t;
-
-/* Centronics Status Mask Register.
-*/
-#define SMC_CENT_F	((u_char)0x08)
-#define SMC_CENT_PE	((u_char)0x04)
-#define SMC_CENT_S	((u_char)0x02)
-
-/* SMC Event and Mask register.
-*/
-#define	SMCM_BRKE	((unsigned char)0x40)	/* When in UART Mode */
-#define	SMCM_BRK	((unsigned char)0x10)	/* When in UART Mode */
-#define	SMCM_TXE	((unsigned char)0x10)	/* When in Transparent Mode */
-#define	SMCM_BSY	((unsigned char)0x04)
-#define	SMCM_TX		((unsigned char)0x02)
-#define	SMCM_RX		((unsigned char)0x01)
-
-/* Baud rate generators.
-*/
-#define CPM_BRG_RST		((uint)0x00020000)
-#define CPM_BRG_EN		((uint)0x00010000)
-#define CPM_BRG_EXTC_INT	((uint)0x00000000)
-#define CPM_BRG_EXTC_CLK2	((uint)0x00004000)
-#define CPM_BRG_EXTC_CLK6	((uint)0x00008000)
-#define CPM_BRG_ATB		((uint)0x00002000)
-#define CPM_BRG_CD_MASK		((uint)0x00001ffe)
-#define CPM_BRG_DIV16		((uint)0x00000001)
-
-/* SI Clock Route Register
-*/
-#define SICR_RCLK_SCC1_BRG1	((uint)0x00000000)
-#define SICR_TCLK_SCC1_BRG1	((uint)0x00000000)
-#define SICR_RCLK_SCC2_BRG2	((uint)0x00000800)
-#define SICR_TCLK_SCC2_BRG2	((uint)0x00000100)
-#define SICR_RCLK_SCC3_BRG3	((uint)0x00100000)
-#define SICR_TCLK_SCC3_BRG3	((uint)0x00020000)
-#define SICR_RCLK_SCC4_BRG4	((uint)0x18000000)
-#define SICR_TCLK_SCC4_BRG4	((uint)0x03000000)
-
-/* SCCs.
-*/
-#define SCC_GSMRH_IRP		((uint)0x00040000)
-#define SCC_GSMRH_GDE		((uint)0x00010000)
-#define SCC_GSMRH_TCRC_CCITT	((uint)0x00008000)
-#define SCC_GSMRH_TCRC_BISYNC	((uint)0x00004000)
-#define SCC_GSMRH_TCRC_HDLC	((uint)0x00000000)
-#define SCC_GSMRH_REVD		((uint)0x00002000)
-#define SCC_GSMRH_TRX		((uint)0x00001000)
-#define SCC_GSMRH_TTX		((uint)0x00000800)
-#define SCC_GSMRH_CDP		((uint)0x00000400)
-#define SCC_GSMRH_CTSP		((uint)0x00000200)
-#define SCC_GSMRH_CDS		((uint)0x00000100)
-#define SCC_GSMRH_CTSS		((uint)0x00000080)
-#define SCC_GSMRH_TFL		((uint)0x00000040)
-#define SCC_GSMRH_RFW		((uint)0x00000020)
-#define SCC_GSMRH_TXSY		((uint)0x00000010)
-#define SCC_GSMRH_SYNL16	((uint)0x0000000c)
-#define SCC_GSMRH_SYNL8		((uint)0x00000008)
-#define SCC_GSMRH_SYNL4		((uint)0x00000004)
-#define SCC_GSMRH_RTSM		((uint)0x00000002)
-#define SCC_GSMRH_RSYN		((uint)0x00000001)
-
-#define SCC_GSMRL_SIR		((uint)0x80000000)	/* SCC2 only */
-#define SCC_GSMRL_EDGE_NONE	((uint)0x60000000)
-#define SCC_GSMRL_EDGE_NEG	((uint)0x40000000)
-#define SCC_GSMRL_EDGE_POS	((uint)0x20000000)
-#define SCC_GSMRL_EDGE_BOTH	((uint)0x00000000)
-#define SCC_GSMRL_TCI		((uint)0x10000000)
-#define SCC_GSMRL_TSNC_3	((uint)0x0c000000)
-#define SCC_GSMRL_TSNC_4	((uint)0x08000000)
-#define SCC_GSMRL_TSNC_14	((uint)0x04000000)
-#define SCC_GSMRL_TSNC_INF	((uint)0x00000000)
-#define SCC_GSMRL_RINV		((uint)0x02000000)
-#define SCC_GSMRL_TINV		((uint)0x01000000)
-#define SCC_GSMRL_TPL_128	((uint)0x00c00000)
-#define SCC_GSMRL_TPL_64	((uint)0x00a00000)
-#define SCC_GSMRL_TPL_48	((uint)0x00800000)
-#define SCC_GSMRL_TPL_32	((uint)0x00600000)
-#define SCC_GSMRL_TPL_16	((uint)0x00400000)
-#define SCC_GSMRL_TPL_8		((uint)0x00200000)
-#define SCC_GSMRL_TPL_NONE	((uint)0x00000000)
-#define SCC_GSMRL_TPP_ALL1	((uint)0x00180000)
-#define SCC_GSMRL_TPP_01	((uint)0x00100000)
-#define SCC_GSMRL_TPP_10	((uint)0x00080000)
-#define SCC_GSMRL_TPP_ZEROS	((uint)0x00000000)
-#define SCC_GSMRL_TEND		((uint)0x00040000)
-#define SCC_GSMRL_TDCR_32	((uint)0x00030000)
-#define SCC_GSMRL_TDCR_16	((uint)0x00020000)
-#define SCC_GSMRL_TDCR_8	((uint)0x00010000)
-#define SCC_GSMRL_TDCR_1	((uint)0x00000000)
-#define SCC_GSMRL_RDCR_32	((uint)0x0000c000)
-#define SCC_GSMRL_RDCR_16	((uint)0x00008000)
-#define SCC_GSMRL_RDCR_8	((uint)0x00004000)
-#define SCC_GSMRL_RDCR_1	((uint)0x00000000)
-#define SCC_GSMRL_RENC_DFMAN	((uint)0x00003000)
-#define SCC_GSMRL_RENC_MANCH	((uint)0x00002000)
-#define SCC_GSMRL_RENC_FM0	((uint)0x00001000)
-#define SCC_GSMRL_RENC_NRZI	((uint)0x00000800)
-#define SCC_GSMRL_RENC_NRZ	((uint)0x00000000)
-#define SCC_GSMRL_TENC_DFMAN	((uint)0x00000600)
-#define SCC_GSMRL_TENC_MANCH	((uint)0x00000400)
-#define SCC_GSMRL_TENC_FM0	((uint)0x00000200)
-#define SCC_GSMRL_TENC_NRZI	((uint)0x00000100)
-#define SCC_GSMRL_TENC_NRZ	((uint)0x00000000)
-#define SCC_GSMRL_DIAG_LE	((uint)0x000000c0)	/* Loop and echo */
-#define SCC_GSMRL_DIAG_ECHO	((uint)0x00000080)
-#define SCC_GSMRL_DIAG_LOOP	((uint)0x00000040)
-#define SCC_GSMRL_DIAG_NORM	((uint)0x00000000)
-#define SCC_GSMRL_ENR		((uint)0x00000020)
-#define SCC_GSMRL_ENT		((uint)0x00000010)
-#define SCC_GSMRL_MODE_ENET	((uint)0x0000000c)
-#define SCC_GSMRL_MODE_QMC	((uint)0x0000000a)
-#define SCC_GSMRL_MODE_DDCMP	((uint)0x00000009)
-#define SCC_GSMRL_MODE_BISYNC	((uint)0x00000008)
-#define SCC_GSMRL_MODE_V14	((uint)0x00000007)
-#define SCC_GSMRL_MODE_AHDLC	((uint)0x00000006)
-#define SCC_GSMRL_MODE_PROFIBUS	((uint)0x00000005)
-#define SCC_GSMRL_MODE_UART	((uint)0x00000004)
-#define SCC_GSMRL_MODE_SS7	((uint)0x00000003)
-#define SCC_GSMRL_MODE_ATALK	((uint)0x00000002)
-#define SCC_GSMRL_MODE_HDLC	((uint)0x00000000)
-
-#define SCC_TODR_TOD		((ushort)0x8000)
-
-/* SCC Event and Mask register.
-*/
-#define	SCCM_TXE	((unsigned char)0x10)
-#define	SCCM_BSY	((unsigned char)0x04)
-#define	SCCM_TX		((unsigned char)0x02)
-#define	SCCM_RX		((unsigned char)0x01)
-
-typedef struct scc_param {
-	ushort	scc_rbase;	/* Rx Buffer descriptor base address */
-	ushort	scc_tbase;	/* Tx Buffer descriptor base address */
-	u_char	scc_rfcr;	/* Rx function code */
-	u_char	scc_tfcr;	/* Tx function code */
-	ushort	scc_mrblr;	/* Max receive buffer length */
-	uint	scc_rstate;	/* Internal */
-	uint	scc_idp;	/* Internal */
-	ushort	scc_rbptr;	/* Internal */
-	ushort	scc_ibc;	/* Internal */
-	uint	scc_rxtmp;	/* Internal */
-	uint	scc_tstate;	/* Internal */
-	uint	scc_tdp;	/* Internal */
-	ushort	scc_tbptr;	/* Internal */
-	ushort	scc_tbc;	/* Internal */
-	uint	scc_txtmp;	/* Internal */
-	uint	scc_rcrc;	/* Internal */
-	uint	scc_tcrc;	/* Internal */
-} sccp_t;
-
-/* Function code bits.
-*/
-#define SCC_EB	((u_char)0x10)	/* Set big endian byte order */
-
-/* CPM Ethernet through SCCx.
- */
-typedef struct scc_enet {
-	sccp_t	sen_genscc;
-	uint	sen_cpres;	/* Preset CRC */
-	uint	sen_cmask;	/* Constant mask for CRC */
-	uint	sen_crcec;	/* CRC Error counter */
-	uint	sen_alec;	/* alignment error counter */
-	uint	sen_disfc;	/* discard frame counter */
-	ushort	sen_pads;	/* Tx short frame pad character */
-	ushort	sen_retlim;	/* Retry limit threshold */
-	ushort	sen_retcnt;	/* Retry limit counter */
-	ushort	sen_maxflr;	/* maximum frame length register */
-	ushort	sen_minflr;	/* minimum frame length register */
-	ushort	sen_maxd1;	/* maximum DMA1 length */
-	ushort	sen_maxd2;	/* maximum DMA2 length */
-	ushort	sen_maxd;	/* Rx max DMA */
-	ushort	sen_dmacnt;	/* Rx DMA counter */
-	ushort	sen_maxb;	/* Max BD byte count */
-	ushort	sen_gaddr1;	/* Group address filter */
-	ushort	sen_gaddr2;
-	ushort	sen_gaddr3;
-	ushort	sen_gaddr4;
-	uint	sen_tbuf0data0;	/* Save area 0 - current frame */
-	uint	sen_tbuf0data1;	/* Save area 1 - current frame */
-	uint	sen_tbuf0rba;	/* Internal */
-	uint	sen_tbuf0crc;	/* Internal */
-	ushort	sen_tbuf0bcnt;	/* Internal */
-	ushort	sen_paddrh;	/* physical address (MSB) */
-	ushort	sen_paddrm;
-	ushort	sen_paddrl;	/* physical address (LSB) */
-	ushort	sen_pper;	/* persistence */
-	ushort	sen_rfbdptr;	/* Rx first BD pointer */
-	ushort	sen_tfbdptr;	/* Tx first BD pointer */
-	ushort	sen_tlbdptr;	/* Tx last BD pointer */
-	uint	sen_tbuf1data0;	/* Save area 0 - current frame */
-	uint	sen_tbuf1data1;	/* Save area 1 - current frame */
-	uint	sen_tbuf1rba;	/* Internal */
-	uint	sen_tbuf1crc;	/* Internal */
-	ushort	sen_tbuf1bcnt;	/* Internal */
-	ushort	sen_txlen;	/* Tx Frame length counter */
-	ushort	sen_iaddr1;	/* Individual address filter */
-	ushort	sen_iaddr2;
-	ushort	sen_iaddr3;
-	ushort	sen_iaddr4;
-	ushort	sen_boffcnt;	/* Backoff counter */
-
-	/* NOTE: Some versions of the manual have the following items
-	 * incorrectly documented.  Below is the proper order.
-	 */
-	ushort	sen_taddrh;	/* temp address (MSB) */
-	ushort	sen_taddrm;
-	ushort	sen_taddrl;	/* temp address (LSB) */
-} scc_enet_t;
-
-/* SCC Event register as used by Ethernet.
-*/
-#define SCCE_ENET_GRA	((ushort)0x0080)	/* Graceful stop complete */
-#define SCCE_ENET_TXE	((ushort)0x0010)	/* Transmit Error */
-#define SCCE_ENET_RXF	((ushort)0x0008)	/* Full frame received */
-#define SCCE_ENET_BSY	((ushort)0x0004)	/* All incoming buffers full */
-#define SCCE_ENET_TXB	((ushort)0x0002)	/* A buffer was transmitted */
-#define SCCE_ENET_RXB	((ushort)0x0001)	/* A buffer was received */
-
-/* SCC Mode Register (PMSR) as used by Ethernet.
-*/
-#define SCC_PSMR_HBC	((ushort)0x8000)	/* Enable heartbeat */
-#define SCC_PSMR_FC	((ushort)0x4000)	/* Force collision */
-#define SCC_PSMR_RSH	((ushort)0x2000)	/* Receive short frames */
-#define SCC_PSMR_IAM	((ushort)0x1000)	/* Check individual hash */
-#define SCC_PSMR_ENCRC	((ushort)0x0800)	/* Ethernet CRC mode */
-#define SCC_PSMR_PRO	((ushort)0x0200)	/* Promiscuous mode */
-#define SCC_PSMR_BRO	((ushort)0x0100)	/* Catch broadcast pkts */
-#define SCC_PSMR_SBT	((ushort)0x0080)	/* Special backoff timer */
-#define SCC_PSMR_LPB	((ushort)0x0040)	/* Set Loopback mode */
-#define SCC_PSMR_SIP	((ushort)0x0020)	/* Sample Input Pins */
-#define SCC_PSMR_LCW	((ushort)0x0010)	/* Late collision window */
-#define SCC_PSMR_NIB22	((ushort)0x000a)	/* Start frame search */
-#define SCC_PSMR_FDE	((ushort)0x0001)	/* Full duplex enable */
-
-/* Buffer descriptor control/status used by Ethernet receive.
-*/
-#define BD_ENET_RX_EMPTY	((ushort)0x8000)
-#define BD_ENET_RX_WRAP		((ushort)0x2000)
-#define BD_ENET_RX_INTR		((ushort)0x1000)
-#define BD_ENET_RX_LAST		((ushort)0x0800)
-#define BD_ENET_RX_FIRST	((ushort)0x0400)
-#define BD_ENET_RX_MISS		((ushort)0x0100)
-#define BD_ENET_RX_LG		((ushort)0x0020)
-#define BD_ENET_RX_NO		((ushort)0x0010)
-#define BD_ENET_RX_SH		((ushort)0x0008)
-#define BD_ENET_RX_CR		((ushort)0x0004)
-#define BD_ENET_RX_OV		((ushort)0x0002)
-#define BD_ENET_RX_CL		((ushort)0x0001)
-#define BD_ENET_RX_BC		((ushort)0x0080)	/* DA is Broadcast */
-#define BD_ENET_RX_MC		((ushort)0x0040)	/* DA is Multicast */
-#define BD_ENET_RX_STATS	((ushort)0x013f)	/* All status bits */
-
-/* Buffer descriptor control/status used by Ethernet transmit.
-*/
-#define BD_ENET_TX_READY	((ushort)0x8000)
-#define BD_ENET_TX_PAD		((ushort)0x4000)
-#define BD_ENET_TX_WRAP		((ushort)0x2000)
-#define BD_ENET_TX_INTR		((ushort)0x1000)
-#define BD_ENET_TX_LAST		((ushort)0x0800)
-#define BD_ENET_TX_TC		((ushort)0x0400)
-#define BD_ENET_TX_DEF		((ushort)0x0200)
-#define BD_ENET_TX_HB		((ushort)0x0100)
-#define BD_ENET_TX_LC		((ushort)0x0080)
-#define BD_ENET_TX_RL		((ushort)0x0040)
-#define BD_ENET_TX_RCMASK	((ushort)0x003c)
-#define BD_ENET_TX_UN		((ushort)0x0002)
-#define BD_ENET_TX_CSL		((ushort)0x0001)
-#define BD_ENET_TX_STATS	((ushort)0x03ff)	/* All status bits */
-
-/* SCC as UART
-*/
-typedef struct scc_uart {
-	sccp_t	scc_genscc;
-	char	res1[8];	/* Reserved */
-	ushort	scc_maxidl;	/* Maximum idle chars */
-	ushort	scc_idlc;	/* temp idle counter */
-	ushort	scc_brkcr;	/* Break count register */
-	ushort	scc_parec;	/* receive parity error counter */
-	ushort	scc_frmec;	/* receive framing error counter */
-	ushort	scc_nosec;	/* receive noise counter */
-	ushort	scc_brkec;	/* receive break condition counter */
-	ushort	scc_brkln;	/* last received break length */
-	ushort	scc_uaddr1;	/* UART address character 1 */
-	ushort	scc_uaddr2;	/* UART address character 2 */
-	ushort	scc_rtemp;	/* Temp storage */
-	ushort	scc_toseq;	/* Transmit out of sequence char */
-	ushort	scc_char1;	/* control character 1 */
-	ushort	scc_char2;	/* control character 2 */
-	ushort	scc_char3;	/* control character 3 */
-	ushort	scc_char4;	/* control character 4 */
-	ushort	scc_char5;	/* control character 5 */
-	ushort	scc_char6;	/* control character 6 */
-	ushort	scc_char7;	/* control character 7 */
-	ushort	scc_char8;	/* control character 8 */
-	ushort	scc_rccm;	/* receive control character mask */
-	ushort	scc_rccr;	/* receive control character register */
-	ushort	scc_rlbc;	/* receive last break character */
-} scc_uart_t;
-
-/* SCC Event and Mask registers when it is used as a UART.
-*/
-#define UART_SCCM_GLR		((ushort)0x1000)
-#define UART_SCCM_GLT		((ushort)0x0800)
-#define UART_SCCM_AB		((ushort)0x0200)
-#define UART_SCCM_IDL		((ushort)0x0100)
-#define UART_SCCM_GRA		((ushort)0x0080)
-#define UART_SCCM_BRKE		((ushort)0x0040)
-#define UART_SCCM_BRKS		((ushort)0x0020)
-#define UART_SCCM_CCR		((ushort)0x0008)
-#define UART_SCCM_BSY		((ushort)0x0004)
-#define UART_SCCM_TX		((ushort)0x0002)
-#define UART_SCCM_RX		((ushort)0x0001)
-
-/* The SCC PMSR when used as a UART.
-*/
-#define SCU_PSMR_FLC		((ushort)0x8000)
-#define SCU_PSMR_SL		((ushort)0x4000)
-#define SCU_PSMR_CL		((ushort)0x3000)
-#define SCU_PSMR_UM		((ushort)0x0c00)
-#define SCU_PSMR_FRZ		((ushort)0x0200)
-#define SCU_PSMR_RZS		((ushort)0x0100)
-#define SCU_PSMR_SYN		((ushort)0x0080)
-#define SCU_PSMR_DRT		((ushort)0x0040)
-#define SCU_PSMR_PEN		((ushort)0x0010)
-#define SCU_PSMR_RPM		((ushort)0x000c)
-#define SCU_PSMR_REVP		((ushort)0x0008)
-#define SCU_PSMR_TPM		((ushort)0x0003)
-#define SCU_PSMR_TEVP		((ushort)0x0002)
-
-/* CPM Transparent mode SCC.
- */
-typedef struct scc_trans {
-	sccp_t	st_genscc;
-	uint	st_cpres;	/* Preset CRC */
-	uint	st_cmask;	/* Constant mask for CRC */
-} scc_trans_t;
-
-#define BD_SCC_TX_LAST		((ushort)0x0800)
-
-/* IIC parameter RAM.
-*/
-typedef struct iic {
-	ushort	iic_rbase;	/* Rx Buffer descriptor base address */
-	ushort	iic_tbase;	/* Tx Buffer descriptor base address */
-	u_char	iic_rfcr;	/* Rx function code */
-	u_char	iic_tfcr;	/* Tx function code */
-	ushort	iic_mrblr;	/* Max receive buffer length */
-	uint	iic_rstate;	/* Internal */
-	uint	iic_rdp;	/* Internal */
-	ushort	iic_rbptr;	/* Internal */
-	ushort	iic_rbc;	/* Internal */
-	uint	iic_rxtmp;	/* Internal */
-	uint	iic_tstate;	/* Internal */
-	uint	iic_tdp;	/* Internal */
-	ushort	iic_tbptr;	/* Internal */
-	ushort	iic_tbc;	/* Internal */
-	uint	iic_txtmp;	/* Internal */
-	char	res1[4];	/* Reserved */
-	ushort	iic_rpbase;	/* Relocation pointer */
-	char	res2[2];	/* Reserved */
-} iic_t;
-
-#define BD_IIC_START		((ushort)0x0400)
-
-/* SPI parameter RAM.
-*/
-typedef struct spi {
-	ushort	spi_rbase;	/* Rx Buffer descriptor base address */
-	ushort	spi_tbase;	/* Tx Buffer descriptor base address */
-	u_char	spi_rfcr;	/* Rx function code */
-	u_char	spi_tfcr;	/* Tx function code */
-	ushort	spi_mrblr;	/* Max receive buffer length */
-	uint	spi_rstate;	/* Internal */
-	uint	spi_rdp;	/* Internal */
-	ushort	spi_rbptr;	/* Internal */
-	ushort	spi_rbc;	/* Internal */
-	uint	spi_rxtmp;	/* Internal */
-	uint	spi_tstate;	/* Internal */
-	uint	spi_tdp;	/* Internal */
-	ushort	spi_tbptr;	/* Internal */
-	ushort	spi_tbc;	/* Internal */
-	uint	spi_txtmp;	/* Internal */
-	uint	spi_res;
-	ushort	spi_rpbase;	/* Relocation pointer */
-	ushort	spi_res2;
-} spi_t;
-
-/* SPI Mode register.
-*/
-#define SPMODE_LOOP	((ushort)0x4000)	/* Loopback */
-#define SPMODE_CI	((ushort)0x2000)	/* Clock Invert */
-#define SPMODE_CP	((ushort)0x1000)	/* Clock Phase */
-#define SPMODE_DIV16	((ushort)0x0800)	/* BRG/16 mode */
-#define SPMODE_REV	((ushort)0x0400)	/* Reversed Data */
-#define SPMODE_MSTR	((ushort)0x0200)	/* SPI Master */
-#define SPMODE_EN	((ushort)0x0100)	/* Enable */
-#define SPMODE_LENMSK	((ushort)0x00f0)	/* character length */
-#define SPMODE_LEN4	((ushort)0x0030)	/*  4 bits per char */
-#define SPMODE_LEN8	((ushort)0x0070)	/*  8 bits per char */
-#define SPMODE_LEN16	((ushort)0x00f0)	/* 16 bits per char */
-#define SPMODE_PMMSK	((ushort)0x000f)	/* prescale modulus */
-
-/* SPIE fields */
-#define SPIE_MME	0x20
-#define SPIE_TXE	0x10
-#define SPIE_BSY	0x04
-#define SPIE_TXB	0x02
-#define SPIE_RXB	0x01
-
-/*
- * RISC Controller Configuration Register definitons
- */
-#define RCCR_TIME	0x8000			/* RISC Timer Enable */
-#define RCCR_TIMEP(t)	(((t) & 0x3F)<<8)	/* RISC Timer Period */
-#define RCCR_TIME_MASK	0x00FF			/* not RISC Timer related bits */
-
-/* RISC Timer Parameter RAM offset */
-#define PROFF_RTMR	((uint)0x01B0)
-
-typedef struct risc_timer_pram {
-	unsigned short	tm_base;	/* RISC Timer Table Base Address */
-	unsigned short	tm_ptr;		/* RISC Timer Table Pointer (internal) */
-	unsigned short	r_tmr;		/* RISC Timer Mode Register */
-	unsigned short	r_tmv;		/* RISC Timer Valid Register */
-	unsigned long	tm_cmd;		/* RISC Timer Command Register */
-	unsigned long	tm_cnt;		/* RISC Timer Internal Count */
-} rt_pram_t;
-
-/* Bits in RISC Timer Command Register */
-#define TM_CMD_VALID	0x80000000	/* Valid - Enables the timer */
-#define TM_CMD_RESTART	0x40000000	/* Restart - for automatic restart */
-#define TM_CMD_PWM	0x20000000	/* Run in Pulse Width Modulation Mode */
-#define TM_CMD_NUM(n)	(((n)&0xF)<<16)	/* Timer Number */
-#define TM_CMD_PERIOD(p) ((p)&0xFFFF)	/* Timer Period */
-
-/* CPM interrupts.  There are nearly 32 interrupts generated by CPM
- * channels or devices.  All of these are presented to the PPC core
- * as a single interrupt.  The CPM interrupt handler dispatches its
- * own handlers, in a similar fashion to the PPC core handler.  We
- * use the table as defined in the manuals (i.e. no special high
- * priority and SCC1 == SCCa, etc...).
- */
-#define CPMVEC_NR		32
-#define	CPMVEC_PIO_PC15		((ushort)0x1f)
-#define	CPMVEC_SCC1		((ushort)0x1e)
-#define	CPMVEC_SCC2		((ushort)0x1d)
-#define	CPMVEC_SCC3		((ushort)0x1c)
-#define	CPMVEC_SCC4		((ushort)0x1b)
-#define	CPMVEC_PIO_PC14		((ushort)0x1a)
-#define	CPMVEC_TIMER1		((ushort)0x19)
-#define	CPMVEC_PIO_PC13		((ushort)0x18)
-#define	CPMVEC_PIO_PC12		((ushort)0x17)
-#define	CPMVEC_SDMA_CB_ERR	((ushort)0x16)
-#define CPMVEC_IDMA1		((ushort)0x15)
-#define CPMVEC_IDMA2		((ushort)0x14)
-#define CPMVEC_TIMER2		((ushort)0x12)
-#define CPMVEC_RISCTIMER	((ushort)0x11)
-#define CPMVEC_I2C		((ushort)0x10)
-#define	CPMVEC_PIO_PC11		((ushort)0x0f)
-#define	CPMVEC_PIO_PC10		((ushort)0x0e)
-#define CPMVEC_TIMER3		((ushort)0x0c)
-#define	CPMVEC_PIO_PC9		((ushort)0x0b)
-#define	CPMVEC_PIO_PC8		((ushort)0x0a)
-#define	CPMVEC_PIO_PC7		((ushort)0x09)
-#define CPMVEC_TIMER4		((ushort)0x07)
-#define	CPMVEC_PIO_PC6		((ushort)0x06)
-#define	CPMVEC_SPI		((ushort)0x05)
-#define	CPMVEC_SMC1		((ushort)0x04)
-#define	CPMVEC_SMC2		((ushort)0x03)
-#define	CPMVEC_PIO_PC5		((ushort)0x02)
-#define	CPMVEC_PIO_PC4		((ushort)0x01)
-#define	CPMVEC_ERROR		((ushort)0x00)
-
-/* CPM interrupt configuration vector.
-*/
-#define	CICR_SCD_SCC4		((uint)0x00c00000)	/* SCC4 @ SCCd */
-#define	CICR_SCC_SCC3		((uint)0x00200000)	/* SCC3 @ SCCc */
-#define	CICR_SCB_SCC2		((uint)0x00040000)	/* SCC2 @ SCCb */
-#define	CICR_SCA_SCC1		((uint)0x00000000)	/* SCC1 @ SCCa */
-#define CICR_IRL_MASK		((uint)0x0000e000)	/* Core interrupt */
-#define CICR_HP_MASK		((uint)0x00001f00)	/* Hi-pri int. */
-#define CICR_IEN		((uint)0x00000080)	/* Int. enable */
-#define CICR_SPS		((uint)0x00000001)	/* SCC Spread */
-
-extern void cpm_install_handler(int vec, void (*handler)(void *), void *dev_id);
-extern void cpm_free_handler(int vec);
-
-#endif /* __CPM1__ */
diff --git a/include/asm-ppc/cpm2.h b/include/asm-ppc/cpm2.h
deleted file mode 100644
index 4c538228e42..00000000000
--- a/include/asm-ppc/cpm2.h
+++ /dev/null
@@ -1,1248 +0,0 @@
-/*
- * Communication Processor Module v2.
- *
- * This file contains structures and information for the communication
- * processor channels found in the dual port RAM or parameter RAM.
- * All CPM control and status is available through the CPM2 internal
- * memory map.  See immap_cpm2.h for details.
- */
-#ifdef __KERNEL__
-#ifndef __CPM2__
-#define __CPM2__
-
-#include <asm/immap_cpm2.h>
-
-/* CPM Command register.
-*/
-#define CPM_CR_RST	((uint)0x80000000)
-#define CPM_CR_PAGE	((uint)0x7c000000)
-#define CPM_CR_SBLOCK	((uint)0x03e00000)
-#define CPM_CR_FLG	((uint)0x00010000)
-#define CPM_CR_MCN	((uint)0x00003fc0)
-#define CPM_CR_OPCODE	((uint)0x0000000f)
-
-/* Device sub-block and page codes.
-*/
-#define CPM_CR_SCC1_SBLOCK	(0x04)
-#define CPM_CR_SCC2_SBLOCK	(0x05)
-#define CPM_CR_SCC3_SBLOCK	(0x06)
-#define CPM_CR_SCC4_SBLOCK	(0x07)
-#define CPM_CR_SMC1_SBLOCK	(0x08)
-#define CPM_CR_SMC2_SBLOCK	(0x09)
-#define CPM_CR_SPI_SBLOCK	(0x0a)
-#define CPM_CR_I2C_SBLOCK	(0x0b)
-#define CPM_CR_TIMER_SBLOCK	(0x0f)
-#define CPM_CR_RAND_SBLOCK	(0x0e)
-#define CPM_CR_FCC1_SBLOCK	(0x10)
-#define CPM_CR_FCC2_SBLOCK	(0x11)
-#define CPM_CR_FCC3_SBLOCK	(0x12)
-#define CPM_CR_IDMA1_SBLOCK	(0x14)
-#define CPM_CR_IDMA2_SBLOCK	(0x15)
-#define CPM_CR_IDMA3_SBLOCK	(0x16)
-#define CPM_CR_IDMA4_SBLOCK	(0x17)
-#define CPM_CR_MCC1_SBLOCK	(0x1c)
-
-#define CPM_CR_FCC_SBLOCK(x)	(x + 0x10)
-
-#define CPM_CR_SCC1_PAGE	(0x00)
-#define CPM_CR_SCC2_PAGE	(0x01)
-#define CPM_CR_SCC3_PAGE	(0x02)
-#define CPM_CR_SCC4_PAGE	(0x03)
-#define CPM_CR_SMC1_PAGE	(0x07)
-#define CPM_CR_SMC2_PAGE	(0x08)
-#define CPM_CR_SPI_PAGE		(0x09)
-#define CPM_CR_I2C_PAGE		(0x0a)
-#define CPM_CR_TIMER_PAGE	(0x0a)
-#define CPM_CR_RAND_PAGE	(0x0a)
-#define CPM_CR_FCC1_PAGE	(0x04)
-#define CPM_CR_FCC2_PAGE	(0x05)
-#define CPM_CR_FCC3_PAGE	(0x06)
-#define CPM_CR_IDMA1_PAGE	(0x07)
-#define CPM_CR_IDMA2_PAGE	(0x08)
-#define CPM_CR_IDMA3_PAGE	(0x09)
-#define CPM_CR_IDMA4_PAGE	(0x0a)
-#define CPM_CR_MCC1_PAGE	(0x07)
-#define CPM_CR_MCC2_PAGE	(0x08)
-
-#define CPM_CR_FCC_PAGE(x)	(x + 0x04)
-
-/* Some opcodes (there are more...later)
-*/
-#define CPM_CR_INIT_TRX		((ushort)0x0000)
-#define CPM_CR_INIT_RX		((ushort)0x0001)
-#define CPM_CR_INIT_TX		((ushort)0x0002)
-#define CPM_CR_HUNT_MODE	((ushort)0x0003)
-#define CPM_CR_STOP_TX		((ushort)0x0004)
-#define CPM_CR_GRA_STOP_TX	((ushort)0x0005)
-#define CPM_CR_RESTART_TX	((ushort)0x0006)
-#define CPM_CR_SET_GADDR	((ushort)0x0008)
-#define CPM_CR_START_IDMA	((ushort)0x0009)
-#define CPM_CR_STOP_IDMA	((ushort)0x000b)
-
-#define mk_cr_cmd(PG, SBC, MCN, OP) \
-	((PG << 26) | (SBC << 21) | (MCN << 6) | OP)
-
-/* Dual Port RAM addresses.  The first 16K is available for almost
- * any CPM use, so we put the BDs there.  The first 128 bytes are
- * used for SMC1 and SMC2 parameter RAM, so we start allocating
- * BDs above that.  All of this must change when we start
- * downloading RAM microcode.
- */
-#define CPM_DATAONLY_BASE	((uint)128)
-#define CPM_DP_NOSPACE		((uint)0x7fffffff)
-#if defined(CONFIG_8272)
-#define CPM_DATAONLY_SIZE	((uint)(8 * 1024) - CPM_DATAONLY_BASE)
-#define CPM_FCC_SPECIAL_BASE	((uint)0x00009000)
-#else
-#define CPM_DATAONLY_SIZE	((uint)(16 * 1024) - CPM_DATAONLY_BASE)
-#define CPM_FCC_SPECIAL_BASE	((uint)0x0000b000)
-#endif
-
-/* The number of pages of host memory we allocate for CPM.  This is
- * done early in kernel initialization to get physically contiguous
- * pages.
- */
-#define NUM_CPM_HOST_PAGES	2
-
-/* Export the base address of the communication processor registers
- * and dual port ram.
- */
-extern		cpm_cpm2_t	*cpmp;	 /* Pointer to comm processor */
-
-extern unsigned long cpm_dpalloc(uint size, uint align);
-extern int cpm_dpfree(unsigned long offset);
-extern unsigned long cpm_dpalloc_fixed(unsigned long offset, uint size, uint align);
-extern void cpm_dpdump(void);
-extern void *cpm_dpram_addr(unsigned long offset);
-extern void cpm_setbrg(uint brg, uint rate);
-extern void cpm2_fastbrg(uint brg, uint rate, int div16);
-extern void cpm2_reset(void);
-
-
-/* Buffer descriptors used by many of the CPM protocols.
-*/
-typedef struct cpm_buf_desc {
-	ushort	cbd_sc;		/* Status and Control */
-	ushort	cbd_datlen;	/* Data length in buffer */
-	uint	cbd_bufaddr;	/* Buffer address in host memory */
-} cbd_t;
-
-#define BD_SC_EMPTY	((ushort)0x8000)	/* Receive is empty */
-#define BD_SC_READY	((ushort)0x8000)	/* Transmit is ready */
-#define BD_SC_WRAP	((ushort)0x2000)	/* Last buffer descriptor */
-#define BD_SC_INTRPT	((ushort)0x1000)	/* Interrupt on change */
-#define BD_SC_LAST	((ushort)0x0800)	/* Last buffer in frame */
-#define BD_SC_CM	((ushort)0x0200)	/* Continous mode */
-#define BD_SC_ID	((ushort)0x0100)	/* Rec'd too many idles */
-#define BD_SC_P		((ushort)0x0100)	/* xmt preamble */
-#define BD_SC_BR	((ushort)0x0020)	/* Break received */
-#define BD_SC_FR	((ushort)0x0010)	/* Framing error */
-#define BD_SC_PR	((ushort)0x0008)	/* Parity error */
-#define BD_SC_OV	((ushort)0x0002)	/* Overrun */
-#define BD_SC_CD	((ushort)0x0001)	/* ?? */
-
-/* Function code bits, usually generic to devices.
-*/
-#define CPMFCR_GBL	((u_char)0x20)	/* Set memory snooping */
-#define CPMFCR_EB	((u_char)0x10)	/* Set big endian byte order */
-#define CPMFCR_TC2	((u_char)0x04)	/* Transfer code 2 value */
-#define CPMFCR_DTB	((u_char)0x02)	/* Use local bus for data when set */
-#define CPMFCR_BDB	((u_char)0x01)	/* Use local bus for BD when set */
-
-/* Parameter RAM offsets from the base.
-*/
-#define PROFF_SCC1		((uint)0x8000)
-#define PROFF_SCC2		((uint)0x8100)
-#define PROFF_SCC3		((uint)0x8200)
-#define PROFF_SCC4		((uint)0x8300)
-#define PROFF_FCC1		((uint)0x8400)
-#define PROFF_FCC2		((uint)0x8500)
-#define PROFF_FCC3		((uint)0x8600)
-#define PROFF_MCC1		((uint)0x8700)
-#define PROFF_SMC1_BASE		((uint)0x87fc)
-#define PROFF_IDMA1_BASE	((uint)0x87fe)
-#define PROFF_MCC2		((uint)0x8800)
-#define PROFF_SMC2_BASE		((uint)0x88fc)
-#define PROFF_IDMA2_BASE	((uint)0x88fe)
-#define PROFF_SPI_BASE		((uint)0x89fc)
-#define PROFF_IDMA3_BASE	((uint)0x89fe)
-#define PROFF_TIMERS		((uint)0x8ae0)
-#define PROFF_REVNUM		((uint)0x8af0)
-#define PROFF_RAND		((uint)0x8af8)
-#define PROFF_I2C_BASE		((uint)0x8afc)
-#define PROFF_IDMA4_BASE	((uint)0x8afe)
-
-#define PROFF_SCC_SIZE		((uint)0x100)
-#define PROFF_FCC_SIZE		((uint)0x100)
-#define PROFF_SMC_SIZE		((uint)64)
-
-/* The SMCs are relocated to any of the first eight DPRAM pages.
- * We will fix these at the first locations of DPRAM, until we
- * get some microcode patches :-).
- * The parameter ram space for the SMCs is fifty-some bytes, and
- * they are required to start on a 64 byte boundary.
- */
-#define PROFF_SMC1	(0)
-#define PROFF_SMC2	(64)
-
-
-/* Define enough so I can at least use the serial port as a UART.
- */
-typedef struct smc_uart {
-	ushort	smc_rbase;	/* Rx Buffer descriptor base address */
-	ushort	smc_tbase;	/* Tx Buffer descriptor base address */
-	u_char	smc_rfcr;	/* Rx function code */
-	u_char	smc_tfcr;	/* Tx function code */
-	ushort	smc_mrblr;	/* Max receive buffer length */
-	uint	smc_rstate;	/* Internal */
-	uint	smc_idp;	/* Internal */
-	ushort	smc_rbptr;	/* Internal */
-	ushort	smc_ibc;	/* Internal */
-	uint	smc_rxtmp;	/* Internal */
-	uint	smc_tstate;	/* Internal */
-	uint	smc_tdp;	/* Internal */
-	ushort	smc_tbptr;	/* Internal */
-	ushort	smc_tbc;	/* Internal */
-	uint	smc_txtmp;	/* Internal */
-	ushort	smc_maxidl;	/* Maximum idle characters */
-	ushort	smc_tmpidl;	/* Temporary idle counter */
-	ushort	smc_brklen;	/* Last received break length */
-	ushort	smc_brkec;	/* rcv'd break condition counter */
-	ushort	smc_brkcr;	/* xmt break count register */
-	ushort	smc_rmask;	/* Temporary bit mask */
-	uint	smc_stmp;	/* SDMA Temp */
-} smc_uart_t;
-
-/* SMC uart mode register (Internal memory map).
-*/
-#define SMCMR_REN	((ushort)0x0001)
-#define SMCMR_TEN	((ushort)0x0002)
-#define SMCMR_DM	((ushort)0x000c)
-#define SMCMR_SM_GCI	((ushort)0x0000)
-#define SMCMR_SM_UART	((ushort)0x0020)
-#define SMCMR_SM_TRANS	((ushort)0x0030)
-#define SMCMR_SM_MASK	((ushort)0x0030)
-#define SMCMR_PM_EVEN	((ushort)0x0100)	/* Even parity, else odd */
-#define SMCMR_REVD	SMCMR_PM_EVEN
-#define SMCMR_PEN	((ushort)0x0200)	/* Parity enable */
-#define SMCMR_BS	SMCMR_PEN
-#define SMCMR_SL	((ushort)0x0400)	/* Two stops, else one */
-#define SMCR_CLEN_MASK	((ushort)0x7800)	/* Character length */
-#define smcr_mk_clen(C)	(((C) << 11) & SMCR_CLEN_MASK)
-
-/* SMC Event and Mask register.
-*/
-#define SMCM_BRKE       ((unsigned char)0x40)   /* When in UART Mode */
-#define SMCM_BRK        ((unsigned char)0x10)   /* When in UART Mode */
-#define SMCM_TXE	((unsigned char)0x10)
-#define SMCM_BSY	((unsigned char)0x04)
-#define SMCM_TX		((unsigned char)0x02)
-#define SMCM_RX		((unsigned char)0x01)
-
-/* Baud rate generators.
-*/
-#define CPM_BRG_RST		((uint)0x00020000)
-#define CPM_BRG_EN		((uint)0x00010000)
-#define CPM_BRG_EXTC_INT	((uint)0x00000000)
-#define CPM_BRG_EXTC_CLK3_9	((uint)0x00004000)
-#define CPM_BRG_EXTC_CLK5_15	((uint)0x00008000)
-#define CPM_BRG_ATB		((uint)0x00002000)
-#define CPM_BRG_CD_MASK		((uint)0x00001ffe)
-#define CPM_BRG_DIV16		((uint)0x00000001)
-
-/* SCCs.
-*/
-#define SCC_GSMRH_IRP		((uint)0x00040000)
-#define SCC_GSMRH_GDE		((uint)0x00010000)
-#define SCC_GSMRH_TCRC_CCITT	((uint)0x00008000)
-#define SCC_GSMRH_TCRC_BISYNC	((uint)0x00004000)
-#define SCC_GSMRH_TCRC_HDLC	((uint)0x00000000)
-#define SCC_GSMRH_REVD		((uint)0x00002000)
-#define SCC_GSMRH_TRX		((uint)0x00001000)
-#define SCC_GSMRH_TTX		((uint)0x00000800)
-#define SCC_GSMRH_CDP		((uint)0x00000400)
-#define SCC_GSMRH_CTSP		((uint)0x00000200)
-#define SCC_GSMRH_CDS		((uint)0x00000100)
-#define SCC_GSMRH_CTSS		((uint)0x00000080)
-#define SCC_GSMRH_TFL		((uint)0x00000040)
-#define SCC_GSMRH_RFW		((uint)0x00000020)
-#define SCC_GSMRH_TXSY		((uint)0x00000010)
-#define SCC_GSMRH_SYNL16	((uint)0x0000000c)
-#define SCC_GSMRH_SYNL8		((uint)0x00000008)
-#define SCC_GSMRH_SYNL4		((uint)0x00000004)
-#define SCC_GSMRH_RTSM		((uint)0x00000002)
-#define SCC_GSMRH_RSYN		((uint)0x00000001)
-
-#define SCC_GSMRL_SIR		((uint)0x80000000)	/* SCC2 only */
-#define SCC_GSMRL_EDGE_NONE	((uint)0x60000000)
-#define SCC_GSMRL_EDGE_NEG	((uint)0x40000000)
-#define SCC_GSMRL_EDGE_POS	((uint)0x20000000)
-#define SCC_GSMRL_EDGE_BOTH	((uint)0x00000000)
-#define SCC_GSMRL_TCI		((uint)0x10000000)
-#define SCC_GSMRL_TSNC_3	((uint)0x0c000000)
-#define SCC_GSMRL_TSNC_4	((uint)0x08000000)
-#define SCC_GSMRL_TSNC_14	((uint)0x04000000)
-#define SCC_GSMRL_TSNC_INF	((uint)0x00000000)
-#define SCC_GSMRL_RINV		((uint)0x02000000)
-#define SCC_GSMRL_TINV		((uint)0x01000000)
-#define SCC_GSMRL_TPL_128	((uint)0x00c00000)
-#define SCC_GSMRL_TPL_64	((uint)0x00a00000)
-#define SCC_GSMRL_TPL_48	((uint)0x00800000)
-#define SCC_GSMRL_TPL_32	((uint)0x00600000)
-#define SCC_GSMRL_TPL_16	((uint)0x00400000)
-#define SCC_GSMRL_TPL_8		((uint)0x00200000)
-#define SCC_GSMRL_TPL_NONE	((uint)0x00000000)
-#define SCC_GSMRL_TPP_ALL1	((uint)0x00180000)
-#define SCC_GSMRL_TPP_01	((uint)0x00100000)
-#define SCC_GSMRL_TPP_10	((uint)0x00080000)
-#define SCC_GSMRL_TPP_ZEROS	((uint)0x00000000)
-#define SCC_GSMRL_TEND		((uint)0x00040000)
-#define SCC_GSMRL_TDCR_32	((uint)0x00030000)
-#define SCC_GSMRL_TDCR_16	((uint)0x00020000)
-#define SCC_GSMRL_TDCR_8	((uint)0x00010000)
-#define SCC_GSMRL_TDCR_1	((uint)0x00000000)
-#define SCC_GSMRL_RDCR_32	((uint)0x0000c000)
-#define SCC_GSMRL_RDCR_16	((uint)0x00008000)
-#define SCC_GSMRL_RDCR_8	((uint)0x00004000)
-#define SCC_GSMRL_RDCR_1	((uint)0x00000000)
-#define SCC_GSMRL_RENC_DFMAN	((uint)0x00003000)
-#define SCC_GSMRL_RENC_MANCH	((uint)0x00002000)
-#define SCC_GSMRL_RENC_FM0	((uint)0x00001000)
-#define SCC_GSMRL_RENC_NRZI	((uint)0x00000800)
-#define SCC_GSMRL_RENC_NRZ	((uint)0x00000000)
-#define SCC_GSMRL_TENC_DFMAN	((uint)0x00000600)
-#define SCC_GSMRL_TENC_MANCH	((uint)0x00000400)
-#define SCC_GSMRL_TENC_FM0	((uint)0x00000200)
-#define SCC_GSMRL_TENC_NRZI	((uint)0x00000100)
-#define SCC_GSMRL_TENC_NRZ	((uint)0x00000000)
-#define SCC_GSMRL_DIAG_LE	((uint)0x000000c0)	/* Loop and echo */
-#define SCC_GSMRL_DIAG_ECHO	((uint)0x00000080)
-#define SCC_GSMRL_DIAG_LOOP	((uint)0x00000040)
-#define SCC_GSMRL_DIAG_NORM	((uint)0x00000000)
-#define SCC_GSMRL_ENR		((uint)0x00000020)
-#define SCC_GSMRL_ENT		((uint)0x00000010)
-#define SCC_GSMRL_MODE_ENET	((uint)0x0000000c)
-#define SCC_GSMRL_MODE_DDCMP	((uint)0x00000009)
-#define SCC_GSMRL_MODE_BISYNC	((uint)0x00000008)
-#define SCC_GSMRL_MODE_V14	((uint)0x00000007)
-#define SCC_GSMRL_MODE_AHDLC	((uint)0x00000006)
-#define SCC_GSMRL_MODE_PROFIBUS	((uint)0x00000005)
-#define SCC_GSMRL_MODE_UART	((uint)0x00000004)
-#define SCC_GSMRL_MODE_SS7	((uint)0x00000003)
-#define SCC_GSMRL_MODE_ATALK	((uint)0x00000002)
-#define SCC_GSMRL_MODE_HDLC	((uint)0x00000000)
-
-#define SCC_TODR_TOD		((ushort)0x8000)
-
-/* SCC Event and Mask register.
-*/
-#define SCCM_TXE	((unsigned char)0x10)
-#define SCCM_BSY	((unsigned char)0x04)
-#define SCCM_TX		((unsigned char)0x02)
-#define SCCM_RX		((unsigned char)0x01)
-
-typedef struct scc_param {
-	ushort	scc_rbase;	/* Rx Buffer descriptor base address */
-	ushort	scc_tbase;	/* Tx Buffer descriptor base address */
-	u_char	scc_rfcr;	/* Rx function code */
-	u_char	scc_tfcr;	/* Tx function code */
-	ushort	scc_mrblr;	/* Max receive buffer length */
-	uint	scc_rstate;	/* Internal */
-	uint	scc_idp;	/* Internal */
-	ushort	scc_rbptr;	/* Internal */
-	ushort	scc_ibc;	/* Internal */
-	uint	scc_rxtmp;	/* Internal */
-	uint	scc_tstate;	/* Internal */
-	uint	scc_tdp;	/* Internal */
-	ushort	scc_tbptr;	/* Internal */
-	ushort	scc_tbc;	/* Internal */
-	uint	scc_txtmp;	/* Internal */
-	uint	scc_rcrc;	/* Internal */
-	uint	scc_tcrc;	/* Internal */
-} sccp_t;
-
-/* CPM Ethernet through SCC1.
- */
-typedef struct scc_enet {
-	sccp_t	sen_genscc;
-	uint	sen_cpres;	/* Preset CRC */
-	uint	sen_cmask;	/* Constant mask for CRC */
-	uint	sen_crcec;	/* CRC Error counter */
-	uint	sen_alec;	/* alignment error counter */
-	uint	sen_disfc;	/* discard frame counter */
-	ushort	sen_pads;	/* Tx short frame pad character */
-	ushort	sen_retlim;	/* Retry limit threshold */
-	ushort	sen_retcnt;	/* Retry limit counter */
-	ushort	sen_maxflr;	/* maximum frame length register */
-	ushort	sen_minflr;	/* minimum frame length register */
-	ushort	sen_maxd1;	/* maximum DMA1 length */
-	ushort	sen_maxd2;	/* maximum DMA2 length */
-	ushort	sen_maxd;	/* Rx max DMA */
-	ushort	sen_dmacnt;	/* Rx DMA counter */
-	ushort	sen_maxb;	/* Max BD byte count */
-	ushort	sen_gaddr1;	/* Group address filter */
-	ushort	sen_gaddr2;
-	ushort	sen_gaddr3;
-	ushort	sen_gaddr4;
-	uint	sen_tbuf0data0;	/* Save area 0 - current frame */
-	uint	sen_tbuf0data1;	/* Save area 1 - current frame */
-	uint	sen_tbuf0rba;	/* Internal */
-	uint	sen_tbuf0crc;	/* Internal */
-	ushort	sen_tbuf0bcnt;	/* Internal */
-	ushort	sen_paddrh;	/* physical address (MSB) */
-	ushort	sen_paddrm;
-	ushort	sen_paddrl;	/* physical address (LSB) */
-	ushort	sen_pper;	/* persistence */
-	ushort	sen_rfbdptr;	/* Rx first BD pointer */
-	ushort	sen_tfbdptr;	/* Tx first BD pointer */
-	ushort	sen_tlbdptr;	/* Tx last BD pointer */
-	uint	sen_tbuf1data0;	/* Save area 0 - current frame */
-	uint	sen_tbuf1data1;	/* Save area 1 - current frame */
-	uint	sen_tbuf1rba;	/* Internal */
-	uint	sen_tbuf1crc;	/* Internal */
-	ushort	sen_tbuf1bcnt;	/* Internal */
-	ushort	sen_txlen;	/* Tx Frame length counter */
-	ushort	sen_iaddr1;	/* Individual address filter */
-	ushort	sen_iaddr2;
-	ushort	sen_iaddr3;
-	ushort	sen_iaddr4;
-	ushort	sen_boffcnt;	/* Backoff counter */
-
-	/* NOTE: Some versions of the manual have the following items
-	 * incorrectly documented.  Below is the proper order.
-	 */
-	ushort	sen_taddrh;	/* temp address (MSB) */
-	ushort	sen_taddrm;
-	ushort	sen_taddrl;	/* temp address (LSB) */
-} scc_enet_t;
-
-
-/* SCC Event register as used by Ethernet.
-*/
-#define SCCE_ENET_GRA	((ushort)0x0080)	/* Graceful stop complete */
-#define SCCE_ENET_TXE	((ushort)0x0010)	/* Transmit Error */
-#define SCCE_ENET_RXF	((ushort)0x0008)	/* Full frame received */
-#define SCCE_ENET_BSY	((ushort)0x0004)	/* All incoming buffers full */
-#define SCCE_ENET_TXB	((ushort)0x0002)	/* A buffer was transmitted */
-#define SCCE_ENET_RXB	((ushort)0x0001)	/* A buffer was received */
-
-/* SCC Mode Register (PSMR) as used by Ethernet.
-*/
-#define SCC_PSMR_HBC	((ushort)0x8000)	/* Enable heartbeat */
-#define SCC_PSMR_FC	((ushort)0x4000)	/* Force collision */
-#define SCC_PSMR_RSH	((ushort)0x2000)	/* Receive short frames */
-#define SCC_PSMR_IAM	((ushort)0x1000)	/* Check individual hash */
-#define SCC_PSMR_ENCRC	((ushort)0x0800)	/* Ethernet CRC mode */
-#define SCC_PSMR_PRO	((ushort)0x0200)	/* Promiscuous mode */
-#define SCC_PSMR_BRO	((ushort)0x0100)	/* Catch broadcast pkts */
-#define SCC_PSMR_SBT	((ushort)0x0080)	/* Special backoff timer */
-#define SCC_PSMR_LPB	((ushort)0x0040)	/* Set Loopback mode */
-#define SCC_PSMR_SIP	((ushort)0x0020)	/* Sample Input Pins */
-#define SCC_PSMR_LCW	((ushort)0x0010)	/* Late collision window */
-#define SCC_PSMR_NIB22	((ushort)0x000a)	/* Start frame search */
-#define SCC_PSMR_FDE	((ushort)0x0001)	/* Full duplex enable */
-
-/* Buffer descriptor control/status used by Ethernet receive.
- * Common to SCC and FCC.
- */
-#define BD_ENET_RX_EMPTY	((ushort)0x8000)
-#define BD_ENET_RX_WRAP		((ushort)0x2000)
-#define BD_ENET_RX_INTR		((ushort)0x1000)
-#define BD_ENET_RX_LAST		((ushort)0x0800)
-#define BD_ENET_RX_FIRST	((ushort)0x0400)
-#define BD_ENET_RX_MISS		((ushort)0x0100)
-#define BD_ENET_RX_BC		((ushort)0x0080)	/* FCC Only */
-#define BD_ENET_RX_MC		((ushort)0x0040)	/* FCC Only */
-#define BD_ENET_RX_LG		((ushort)0x0020)
-#define BD_ENET_RX_NO		((ushort)0x0010)
-#define BD_ENET_RX_SH		((ushort)0x0008)
-#define BD_ENET_RX_CR		((ushort)0x0004)
-#define BD_ENET_RX_OV		((ushort)0x0002)
-#define BD_ENET_RX_CL		((ushort)0x0001)
-#define BD_ENET_RX_STATS	((ushort)0x01ff)	/* All status bits */
-
-/* Buffer descriptor control/status used by Ethernet transmit.
- * Common to SCC and FCC.
- */
-#define BD_ENET_TX_READY	((ushort)0x8000)
-#define BD_ENET_TX_PAD		((ushort)0x4000)
-#define BD_ENET_TX_WRAP		((ushort)0x2000)
-#define BD_ENET_TX_INTR		((ushort)0x1000)
-#define BD_ENET_TX_LAST		((ushort)0x0800)
-#define BD_ENET_TX_TC		((ushort)0x0400)
-#define BD_ENET_TX_DEF		((ushort)0x0200)
-#define BD_ENET_TX_HB		((ushort)0x0100)
-#define BD_ENET_TX_LC		((ushort)0x0080)
-#define BD_ENET_TX_RL		((ushort)0x0040)
-#define BD_ENET_TX_RCMASK	((ushort)0x003c)
-#define BD_ENET_TX_UN		((ushort)0x0002)
-#define BD_ENET_TX_CSL		((ushort)0x0001)
-#define BD_ENET_TX_STATS	((ushort)0x03ff)	/* All status bits */
-
-/* SCC as UART
-*/
-typedef struct scc_uart {
-	sccp_t	scc_genscc;
-	uint	scc_res1;	/* Reserved */
-	uint	scc_res2;	/* Reserved */
-	ushort	scc_maxidl;	/* Maximum idle chars */
-	ushort	scc_idlc;	/* temp idle counter */
-	ushort	scc_brkcr;	/* Break count register */
-	ushort	scc_parec;	/* receive parity error counter */
-	ushort	scc_frmec;	/* receive framing error counter */
-	ushort	scc_nosec;	/* receive noise counter */
-	ushort	scc_brkec;	/* receive break condition counter */
-	ushort	scc_brkln;	/* last received break length */
-	ushort	scc_uaddr1;	/* UART address character 1 */
-	ushort	scc_uaddr2;	/* UART address character 2 */
-	ushort	scc_rtemp;	/* Temp storage */
-	ushort	scc_toseq;	/* Transmit out of sequence char */
-	ushort	scc_char1;	/* control character 1 */
-	ushort	scc_char2;	/* control character 2 */
-	ushort	scc_char3;	/* control character 3 */
-	ushort	scc_char4;	/* control character 4 */
-	ushort	scc_char5;	/* control character 5 */
-	ushort	scc_char6;	/* control character 6 */
-	ushort	scc_char7;	/* control character 7 */
-	ushort	scc_char8;	/* control character 8 */
-	ushort	scc_rccm;	/* receive control character mask */
-	ushort	scc_rccr;	/* receive control character register */
-	ushort	scc_rlbc;	/* receive last break character */
-} scc_uart_t;
-
-/* SCC Event and Mask registers when it is used as a UART.
-*/
-#define UART_SCCM_GLR		((ushort)0x1000)
-#define UART_SCCM_GLT		((ushort)0x0800)
-#define UART_SCCM_AB		((ushort)0x0200)
-#define UART_SCCM_IDL		((ushort)0x0100)
-#define UART_SCCM_GRA		((ushort)0x0080)
-#define UART_SCCM_BRKE		((ushort)0x0040)
-#define UART_SCCM_BRKS		((ushort)0x0020)
-#define UART_SCCM_CCR		((ushort)0x0008)
-#define UART_SCCM_BSY		((ushort)0x0004)
-#define UART_SCCM_TX		((ushort)0x0002)
-#define UART_SCCM_RX		((ushort)0x0001)
-
-/* The SCC PSMR when used as a UART.
-*/
-#define SCU_PSMR_FLC		((ushort)0x8000)
-#define SCU_PSMR_SL		((ushort)0x4000)
-#define SCU_PSMR_CL		((ushort)0x3000)
-#define SCU_PSMR_UM		((ushort)0x0c00)
-#define SCU_PSMR_FRZ		((ushort)0x0200)
-#define SCU_PSMR_RZS		((ushort)0x0100)
-#define SCU_PSMR_SYN		((ushort)0x0080)
-#define SCU_PSMR_DRT		((ushort)0x0040)
-#define SCU_PSMR_PEN		((ushort)0x0010)
-#define SCU_PSMR_RPM		((ushort)0x000c)
-#define SCU_PSMR_REVP		((ushort)0x0008)
-#define SCU_PSMR_TPM		((ushort)0x0003)
-#define SCU_PSMR_TEVP		((ushort)0x0002)
-
-/* CPM Transparent mode SCC.
- */
-typedef struct scc_trans {
-	sccp_t	st_genscc;
-	uint	st_cpres;	/* Preset CRC */
-	uint	st_cmask;	/* Constant mask for CRC */
-} scc_trans_t;
-
-#define BD_SCC_TX_LAST		((ushort)0x0800)
-
-/* How about some FCCs.....
-*/
-#define FCC_GFMR_DIAG_NORM	((uint)0x00000000)
-#define FCC_GFMR_DIAG_LE	((uint)0x40000000)
-#define FCC_GFMR_DIAG_AE	((uint)0x80000000)
-#define FCC_GFMR_DIAG_ALE	((uint)0xc0000000)
-#define FCC_GFMR_TCI		((uint)0x20000000)
-#define FCC_GFMR_TRX		((uint)0x10000000)
-#define FCC_GFMR_TTX		((uint)0x08000000)
-#define FCC_GFMR_TTX		((uint)0x08000000)
-#define FCC_GFMR_CDP		((uint)0x04000000)
-#define FCC_GFMR_CTSP		((uint)0x02000000)
-#define FCC_GFMR_CDS		((uint)0x01000000)
-#define FCC_GFMR_CTSS		((uint)0x00800000)
-#define FCC_GFMR_SYNL_NONE	((uint)0x00000000)
-#define FCC_GFMR_SYNL_AUTO	((uint)0x00004000)
-#define FCC_GFMR_SYNL_8		((uint)0x00008000)
-#define FCC_GFMR_SYNL_16	((uint)0x0000c000)
-#define FCC_GFMR_RTSM		((uint)0x00002000)
-#define FCC_GFMR_RENC_NRZ	((uint)0x00000000)
-#define FCC_GFMR_RENC_NRZI	((uint)0x00000800)
-#define FCC_GFMR_REVD		((uint)0x00000400)
-#define FCC_GFMR_TENC_NRZ	((uint)0x00000000)
-#define FCC_GFMR_TENC_NRZI	((uint)0x00000100)
-#define FCC_GFMR_TCRC_16	((uint)0x00000000)
-#define FCC_GFMR_TCRC_32	((uint)0x00000080)
-#define FCC_GFMR_ENR		((uint)0x00000020)
-#define FCC_GFMR_ENT		((uint)0x00000010)
-#define FCC_GFMR_MODE_ENET	((uint)0x0000000c)
-#define FCC_GFMR_MODE_ATM	((uint)0x0000000a)
-#define FCC_GFMR_MODE_HDLC	((uint)0x00000000)
-
-/* Generic FCC parameter ram.
-*/
-typedef struct fcc_param {
-	ushort	fcc_riptr;	/* Rx Internal temp pointer */
-	ushort	fcc_tiptr;	/* Tx Internal temp pointer */
-	ushort	fcc_res1;
-	ushort	fcc_mrblr;	/* Max receive buffer length, mod 32 bytes */
-	uint	fcc_rstate;	/* Upper byte is Func code, must be set */
-	uint	fcc_rbase;	/* Receive BD base */
-	ushort	fcc_rbdstat;	/* RxBD status */
-	ushort	fcc_rbdlen;	/* RxBD down counter */
-	uint	fcc_rdptr;	/* RxBD internal data pointer */
-	uint	fcc_tstate;	/* Upper byte is Func code, must be set */
-	uint	fcc_tbase;	/* Transmit BD base */
-	ushort	fcc_tbdstat;	/* TxBD status */
-	ushort	fcc_tbdlen;	/* TxBD down counter */
-	uint	fcc_tdptr;	/* TxBD internal data pointer */
-	uint	fcc_rbptr;	/* Rx BD Internal buf pointer */
-	uint	fcc_tbptr;	/* Tx BD Internal buf pointer */
-	uint	fcc_rcrc;	/* Rx temp CRC */
-	uint	fcc_res2;
-	uint	fcc_tcrc;	/* Tx temp CRC */
-} fccp_t;
-
-
-/* Ethernet controller through FCC.
-*/
-typedef struct fcc_enet {
-	fccp_t	fen_genfcc;
-	uint	fen_statbuf;	/* Internal status buffer */
-	uint	fen_camptr;	/* CAM address */
-	uint	fen_cmask;	/* Constant mask for CRC */
-	uint	fen_cpres;	/* Preset CRC */
-	uint	fen_crcec;	/* CRC Error counter */
-	uint	fen_alec;	/* alignment error counter */
-	uint	fen_disfc;	/* discard frame counter */
-	ushort	fen_retlim;	/* Retry limit */
-	ushort	fen_retcnt;	/* Retry counter */
-	ushort	fen_pper;	/* Persistence */
-	ushort	fen_boffcnt;	/* backoff counter */
-	uint	fen_gaddrh;	/* Group address filter, high 32-bits */
-	uint	fen_gaddrl;	/* Group address filter, low 32-bits */
-	ushort	fen_tfcstat;	/* out of sequence TxBD */
-	ushort	fen_tfclen;
-	uint	fen_tfcptr;
-	ushort	fen_mflr;	/* Maximum frame length (1518) */
-	ushort	fen_paddrh;	/* MAC address */
-	ushort	fen_paddrm;
-	ushort	fen_paddrl;
-	ushort	fen_ibdcount;	/* Internal BD counter */
-	ushort	fen_ibdstart;	/* Internal BD start pointer */
-	ushort	fen_ibdend;	/* Internal BD end pointer */
-	ushort	fen_txlen;	/* Internal Tx frame length counter */
-	uint	fen_ibdbase[8]; /* Internal use */
-	uint	fen_iaddrh;	/* Individual address filter */
-	uint	fen_iaddrl;
-	ushort	fen_minflr;	/* Minimum frame length (64) */
-	ushort	fen_taddrh;	/* Filter transfer MAC address */
-	ushort	fen_taddrm;
-	ushort	fen_taddrl;
-	ushort	fen_padptr;	/* Pointer to pad byte buffer */
-	ushort	fen_cftype;	/* control frame type */
-	ushort	fen_cfrange;	/* control frame range */
-	ushort	fen_maxb;	/* maximum BD count */
-	ushort	fen_maxd1;	/* Max DMA1 length (1520) */
-	ushort	fen_maxd2;	/* Max DMA2 length (1520) */
-	ushort	fen_maxd;	/* internal max DMA count */
-	ushort	fen_dmacnt;	/* internal DMA counter */
-	uint	fen_octc;	/* Total octect counter */
-	uint	fen_colc;	/* Total collision counter */
-	uint	fen_broc;	/* Total broadcast packet counter */
-	uint	fen_mulc;	/* Total multicast packet count */
-	uint	fen_uspc;	/* Total packets < 64 bytes */
-	uint	fen_frgc;	/* Total packets < 64 bytes with errors */
-	uint	fen_ospc;	/* Total packets > 1518 */
-	uint	fen_jbrc;	/* Total packets > 1518 with errors */
-	uint	fen_p64c;	/* Total packets == 64 bytes */
-	uint	fen_p65c;	/* Total packets 64 < bytes <= 127 */
-	uint	fen_p128c;	/* Total packets 127 < bytes <= 255 */
-	uint	fen_p256c;	/* Total packets 256 < bytes <= 511 */
-	uint	fen_p512c;	/* Total packets 512 < bytes <= 1023 */
-	uint	fen_p1024c;	/* Total packets 1024 < bytes <= 1518 */
-	uint	fen_cambuf;	/* Internal CAM buffer poiner */
-	ushort	fen_rfthr;	/* Received frames threshold */
-	ushort	fen_rfcnt;	/* Received frames count */
-} fcc_enet_t;
-
-/* FCC Event/Mask register as used by Ethernet.
-*/
-#define FCC_ENET_GRA	((ushort)0x0080)	/* Graceful stop complete */
-#define FCC_ENET_RXC	((ushort)0x0040)	/* Control Frame Received */
-#define FCC_ENET_TXC	((ushort)0x0020)	/* Out of seq. Tx sent */
-#define FCC_ENET_TXE	((ushort)0x0010)	/* Transmit Error */
-#define FCC_ENET_RXF	((ushort)0x0008)	/* Full frame received */
-#define FCC_ENET_BSY	((ushort)0x0004)	/* Busy.  Rx Frame dropped */
-#define FCC_ENET_TXB	((ushort)0x0002)	/* A buffer was transmitted */
-#define FCC_ENET_RXB	((ushort)0x0001)	/* A buffer was received */
-
-/* FCC Mode Register (FPSMR) as used by Ethernet.
-*/
-#define FCC_PSMR_HBC	((uint)0x80000000)	/* Enable heartbeat */
-#define FCC_PSMR_FC	((uint)0x40000000)	/* Force Collision */
-#define FCC_PSMR_SBT	((uint)0x20000000)	/* Stop backoff timer */
-#define FCC_PSMR_LPB	((uint)0x10000000)	/* Local protect. 1 = FDX */
-#define FCC_PSMR_LCW	((uint)0x08000000)	/* Late collision select */
-#define FCC_PSMR_FDE	((uint)0x04000000)	/* Full Duplex Enable */
-#define FCC_PSMR_MON	((uint)0x02000000)	/* RMON Enable */
-#define FCC_PSMR_PRO	((uint)0x00400000)	/* Promiscuous Enable */
-#define FCC_PSMR_FCE	((uint)0x00200000)	/* Flow Control Enable */
-#define FCC_PSMR_RSH	((uint)0x00100000)	/* Receive Short Frames */
-#define FCC_PSMR_CAM	((uint)0x00000400)	/* CAM enable */
-#define FCC_PSMR_BRO	((uint)0x00000200)	/* Broadcast pkt discard */
-#define FCC_PSMR_ENCRC	((uint)0x00000080)	/* Use 32-bit CRC */
-
-/* IIC parameter RAM.
-*/
-typedef struct iic {
-	ushort	iic_rbase;	/* Rx Buffer descriptor base address */
-	ushort	iic_tbase;	/* Tx Buffer descriptor base address */
-	u_char	iic_rfcr;	/* Rx function code */
-	u_char	iic_tfcr;	/* Tx function code */
-	ushort	iic_mrblr;	/* Max receive buffer length */
-	uint	iic_rstate;	/* Internal */
-	uint	iic_rdp;	/* Internal */
-	ushort	iic_rbptr;	/* Internal */
-	ushort	iic_rbc;	/* Internal */
-	uint	iic_rxtmp;	/* Internal */
-	uint	iic_tstate;	/* Internal */
-	uint	iic_tdp;	/* Internal */
-	ushort	iic_tbptr;	/* Internal */
-	ushort	iic_tbc;	/* Internal */
-	uint	iic_txtmp;	/* Internal */
-} iic_t;
-
-/* SPI parameter RAM.
-*/
-typedef struct spi {
-	ushort	spi_rbase;	/* Rx Buffer descriptor base address */
-	ushort	spi_tbase;	/* Tx Buffer descriptor base address */
-	u_char	spi_rfcr;	/* Rx function code */
-	u_char	spi_tfcr;	/* Tx function code */
-	ushort	spi_mrblr;	/* Max receive buffer length */
-	uint	spi_rstate;	/* Internal */
-	uint	spi_rdp;	/* Internal */
-	ushort	spi_rbptr;	/* Internal */
-	ushort	spi_rbc;	/* Internal */
-	uint	spi_rxtmp;	/* Internal */
-	uint	spi_tstate;	/* Internal */
-	uint	spi_tdp;	/* Internal */
-	ushort	spi_tbptr;	/* Internal */
-	ushort	spi_tbc;	/* Internal */
-	uint	spi_txtmp;	/* Internal */
-	uint	spi_res;	/* Tx temp. */
-	uint	spi_res1[4];	/* SDMA temp. */
-} spi_t;
-
-/* SPI Mode register.
-*/
-#define SPMODE_LOOP	((ushort)0x4000)	/* Loopback */
-#define SPMODE_CI	((ushort)0x2000)	/* Clock Invert */
-#define SPMODE_CP	((ushort)0x1000)	/* Clock Phase */
-#define SPMODE_DIV16	((ushort)0x0800)	/* BRG/16 mode */
-#define SPMODE_REV	((ushort)0x0400)	/* Reversed Data */
-#define SPMODE_MSTR	((ushort)0x0200)	/* SPI Master */
-#define SPMODE_EN	((ushort)0x0100)	/* Enable */
-#define SPMODE_LENMSK	((ushort)0x00f0)	/* character length */
-#define SPMODE_PMMSK	((ushort)0x000f)	/* prescale modulus */
-
-#define SPMODE_LEN(x)	((((x)-1)&0xF)<<4)
-#define SPMODE_PM(x)	((x) &0xF)
-
-#define SPI_EB		((u_char)0x10)		/* big endian byte order */
-
-#define BD_IIC_START		((ushort)0x0400)
-
-/* IDMA parameter RAM
-*/
-typedef struct idma {
-	ushort ibase;		/* IDMA buffer descriptor table base address */
-	ushort dcm;		/* DMA channel mode */
-	ushort ibdptr;		/* IDMA current buffer descriptor pointer */
-	ushort dpr_buf;		/* IDMA transfer buffer base address */
-	ushort buf_inv;		/* internal buffer inventory */
-	ushort ss_max;		/* steady-state maximum transfer size */
-	ushort dpr_in_ptr;	/* write pointer inside the internal buffer */
-	ushort sts;		/* source transfer size */
-	ushort dpr_out_ptr;	/* read pointer inside the internal buffer */
-	ushort seob;		/* source end of burst */
-	ushort deob;		/* destination end of burst */
-	ushort dts;		/* destination transfer size */
-	ushort ret_add;		/* return address when working in ERM=1 mode */
-	ushort res0;		/* reserved */
-	uint   bd_cnt;		/* internal byte count */
-	uint   s_ptr;		/* source internal data pointer */
-	uint   d_ptr;		/* destination internal data pointer */
-	uint   istate;		/* internal state */
-	u_char res1[20];	/* pad to 64-byte length */
-} idma_t;
-
-/* DMA channel mode bit fields
-*/
-#define IDMA_DCM_FB		((ushort)0x8000) /* fly-by mode */
-#define IDMA_DCM_LP		((ushort)0x4000) /* low priority */
-#define IDMA_DCM_TC2		((ushort)0x0400) /* value driven on TC[2] */
-#define IDMA_DCM_DMA_WRAP_MASK	((ushort)0x01c0) /* mask for DMA wrap */
-#define IDMA_DCM_DMA_WRAP_64	((ushort)0x0000) /* 64-byte DMA xfer buffer */
-#define IDMA_DCM_DMA_WRAP_128	((ushort)0x0040) /* 128-byte DMA xfer buffer */
-#define IDMA_DCM_DMA_WRAP_256	((ushort)0x0080) /* 256-byte DMA xfer buffer */
-#define IDMA_DCM_DMA_WRAP_512	((ushort)0x00c0) /* 512-byte DMA xfer buffer */
-#define IDMA_DCM_DMA_WRAP_1024	((ushort)0x0100) /* 1024-byte DMA xfer buffer */
-#define IDMA_DCM_DMA_WRAP_2048	((ushort)0x0140) /* 2048-byte DMA xfer buffer */
-#define IDMA_DCM_SINC		((ushort)0x0020) /* source inc addr */
-#define IDMA_DCM_DINC		((ushort)0x0010) /* destination inc addr */
-#define IDMA_DCM_ERM		((ushort)0x0008) /* external request mode */
-#define IDMA_DCM_DT		((ushort)0x0004) /* DONE treatment */
-#define IDMA_DCM_SD_MASK	((ushort)0x0003) /* mask for SD bit field */
-#define IDMA_DCM_SD_MEM2MEM	((ushort)0x0000) /* memory-to-memory xfer */
-#define IDMA_DCM_SD_PER2MEM	((ushort)0x0002) /* peripheral-to-memory xfer */
-#define IDMA_DCM_SD_MEM2PER	((ushort)0x0001) /* memory-to-peripheral xfer */
-
-/* IDMA Buffer Descriptors
-*/
-typedef struct idma_bd {
-	uint flags;
-	uint len;	/* data length */
-	uint src;	/* source data buffer pointer */
-	uint dst;	/* destination data buffer pointer */
-} idma_bd_t;
-
-/* IDMA buffer descriptor flag bit fields
-*/
-#define IDMA_BD_V	((uint)0x80000000)	/* valid */
-#define IDMA_BD_W	((uint)0x20000000)	/* wrap */
-#define IDMA_BD_I	((uint)0x10000000)	/* interrupt */
-#define IDMA_BD_L	((uint)0x08000000)	/* last */
-#define IDMA_BD_CM	((uint)0x02000000)	/* continuous mode */
-#define IDMA_BD_SDN	((uint)0x00400000)	/* source done */
-#define IDMA_BD_DDN	((uint)0x00200000)	/* destination done */
-#define IDMA_BD_DGBL	((uint)0x00100000)	/* destination global */
-#define IDMA_BD_DBO_LE	((uint)0x00040000)	/* little-end dest byte order */
-#define IDMA_BD_DBO_BE	((uint)0x00080000)	/* big-end dest byte order */
-#define IDMA_BD_DDTB	((uint)0x00010000)	/* destination data bus */
-#define IDMA_BD_SGBL	((uint)0x00002000)	/* source global */
-#define IDMA_BD_SBO_LE	((uint)0x00000800)	/* little-end src byte order */
-#define IDMA_BD_SBO_BE	((uint)0x00001000)	/* big-end src byte order */
-#define IDMA_BD_SDTB	((uint)0x00000200)	/* source data bus */
-
-/* per-channel IDMA registers
-*/
-typedef struct im_idma {
-	u_char idsr;			/* IDMAn event status register */
-	u_char res0[3];
-	u_char idmr;			/* IDMAn event mask register */
-	u_char res1[3];
-} im_idma_t;
-
-/* IDMA event register bit fields
-*/
-#define IDMA_EVENT_SC	((unsigned char)0x08)	/* stop completed */
-#define IDMA_EVENT_OB	((unsigned char)0x04)	/* out of buffers */
-#define IDMA_EVENT_EDN	((unsigned char)0x02)	/* external DONE asserted */
-#define IDMA_EVENT_BC	((unsigned char)0x01)	/* buffer descriptor complete */
-
-/* RISC Controller Configuration Register (RCCR) bit fields
-*/
-#define RCCR_TIME	((uint)0x80000000) /* timer enable */
-#define RCCR_TIMEP_MASK	((uint)0x3f000000) /* mask for timer period bit field */
-#define RCCR_DR0M	((uint)0x00800000) /* IDMA0 request mode */
-#define RCCR_DR1M	((uint)0x00400000) /* IDMA1 request mode */
-#define RCCR_DR2M	((uint)0x00000080) /* IDMA2 request mode */
-#define RCCR_DR3M	((uint)0x00000040) /* IDMA3 request mode */
-#define RCCR_DR0QP_MASK	((uint)0x00300000) /* mask for IDMA0 req priority */
-#define RCCR_DR0QP_HIGH ((uint)0x00000000) /* IDMA0 has high req priority */
-#define RCCR_DR0QP_MED	((uint)0x00100000) /* IDMA0 has medium req priority */
-#define RCCR_DR0QP_LOW	((uint)0x00200000) /* IDMA0 has low req priority */
-#define RCCR_DR1QP_MASK	((uint)0x00030000) /* mask for IDMA1 req priority */
-#define RCCR_DR1QP_HIGH ((uint)0x00000000) /* IDMA1 has high req priority */
-#define RCCR_DR1QP_MED	((uint)0x00010000) /* IDMA1 has medium req priority */
-#define RCCR_DR1QP_LOW	((uint)0x00020000) /* IDMA1 has low req priority */
-#define RCCR_DR2QP_MASK	((uint)0x00000030) /* mask for IDMA2 req priority */
-#define RCCR_DR2QP_HIGH ((uint)0x00000000) /* IDMA2 has high req priority */
-#define RCCR_DR2QP_MED	((uint)0x00000010) /* IDMA2 has medium req priority */
-#define RCCR_DR2QP_LOW	((uint)0x00000020) /* IDMA2 has low req priority */
-#define RCCR_DR3QP_MASK	((uint)0x00000003) /* mask for IDMA3 req priority */
-#define RCCR_DR3QP_HIGH ((uint)0x00000000) /* IDMA3 has high req priority */
-#define RCCR_DR3QP_MED	((uint)0x00000001) /* IDMA3 has medium req priority */
-#define RCCR_DR3QP_LOW	((uint)0x00000002) /* IDMA3 has low req priority */
-#define RCCR_EIE	((uint)0x00080000) /* external interrupt enable */
-#define RCCR_SCD	((uint)0x00040000) /* scheduler configuration */
-#define RCCR_ERAM_MASK	((uint)0x0000e000) /* mask for enable RAM microcode */
-#define RCCR_ERAM_0KB	((uint)0x00000000) /* use 0KB of dpram for microcode */
-#define RCCR_ERAM_2KB	((uint)0x00002000) /* use 2KB of dpram for microcode */
-#define RCCR_ERAM_4KB	((uint)0x00004000) /* use 4KB of dpram for microcode */
-#define RCCR_ERAM_6KB	((uint)0x00006000) /* use 6KB of dpram for microcode */
-#define RCCR_ERAM_8KB	((uint)0x00008000) /* use 8KB of dpram for microcode */
-#define RCCR_ERAM_10KB	((uint)0x0000a000) /* use 10KB of dpram for microcode */
-#define RCCR_ERAM_12KB	((uint)0x0000c000) /* use 12KB of dpram for microcode */
-#define RCCR_EDM0	((uint)0x00000800) /* DREQ0 edge detect mode */
-#define RCCR_EDM1	((uint)0x00000400) /* DREQ1 edge detect mode */
-#define RCCR_EDM2	((uint)0x00000200) /* DREQ2 edge detect mode */
-#define RCCR_EDM3	((uint)0x00000100) /* DREQ3 edge detect mode */
-#define RCCR_DEM01	((uint)0x00000008) /* DONE0/DONE1 edge detect mode */
-#define RCCR_DEM23	((uint)0x00000004) /* DONE2/DONE3 edge detect mode */
-
-/*-----------------------------------------------------------------------
- * CMXFCR - CMX FCC Clock Route Register
- */
-#define CMXFCR_FC1         0x40000000   /* FCC1 connection              */
-#define CMXFCR_RF1CS_MSK   0x38000000   /* Receive FCC1 Clock Source Mask */
-#define CMXFCR_TF1CS_MSK   0x07000000   /* Transmit FCC1 Clock Source Mask */
-#define CMXFCR_FC2         0x00400000   /* FCC2 connection              */
-#define CMXFCR_RF2CS_MSK   0x00380000   /* Receive FCC2 Clock Source Mask */
-#define CMXFCR_TF2CS_MSK   0x00070000   /* Transmit FCC2 Clock Source Mask */
-#define CMXFCR_FC3         0x00004000   /* FCC3 connection              */
-#define CMXFCR_RF3CS_MSK   0x00003800   /* Receive FCC3 Clock Source Mask */
-#define CMXFCR_TF3CS_MSK   0x00000700   /* Transmit FCC3 Clock Source Mask */
-
-#define CMXFCR_RF1CS_BRG5  0x00000000   /* Receive FCC1 Clock Source is BRG5 */
-#define CMXFCR_RF1CS_BRG6  0x08000000   /* Receive FCC1 Clock Source is BRG6 */
-#define CMXFCR_RF1CS_BRG7  0x10000000   /* Receive FCC1 Clock Source is BRG7 */
-#define CMXFCR_RF1CS_BRG8  0x18000000   /* Receive FCC1 Clock Source is BRG8 */
-#define CMXFCR_RF1CS_CLK9  0x20000000   /* Receive FCC1 Clock Source is CLK9 */
-#define CMXFCR_RF1CS_CLK10 0x28000000   /* Receive FCC1 Clock Source is CLK10 */
-#define CMXFCR_RF1CS_CLK11 0x30000000   /* Receive FCC1 Clock Source is CLK11 */
-#define CMXFCR_RF1CS_CLK12 0x38000000   /* Receive FCC1 Clock Source is CLK12 */
-
-#define CMXFCR_TF1CS_BRG5  0x00000000   /* Transmit FCC1 Clock Source is BRG5 */
-#define CMXFCR_TF1CS_BRG6  0x01000000   /* Transmit FCC1 Clock Source is BRG6 */
-#define CMXFCR_TF1CS_BRG7  0x02000000   /* Transmit FCC1 Clock Source is BRG7 */
-#define CMXFCR_TF1CS_BRG8  0x03000000   /* Transmit FCC1 Clock Source is BRG8 */
-#define CMXFCR_TF1CS_CLK9  0x04000000   /* Transmit FCC1 Clock Source is CLK9 */
-#define CMXFCR_TF1CS_CLK10 0x05000000   /* Transmit FCC1 Clock Source is CLK10 */
-#define CMXFCR_TF1CS_CLK11 0x06000000   /* Transmit FCC1 Clock Source is CLK11 */
-#define CMXFCR_TF1CS_CLK12 0x07000000   /* Transmit FCC1 Clock Source is CLK12 */
-
-#define CMXFCR_RF2CS_BRG5  0x00000000   /* Receive FCC2 Clock Source is BRG5 */
-#define CMXFCR_RF2CS_BRG6  0x00080000   /* Receive FCC2 Clock Source is BRG6 */
-#define CMXFCR_RF2CS_BRG7  0x00100000   /* Receive FCC2 Clock Source is BRG7 */
-#define CMXFCR_RF2CS_BRG8  0x00180000   /* Receive FCC2 Clock Source is BRG8 */
-#define CMXFCR_RF2CS_CLK13 0x00200000   /* Receive FCC2 Clock Source is CLK13 */
-#define CMXFCR_RF2CS_CLK14 0x00280000   /* Receive FCC2 Clock Source is CLK14 */
-#define CMXFCR_RF2CS_CLK15 0x00300000   /* Receive FCC2 Clock Source is CLK15 */
-#define CMXFCR_RF2CS_CLK16 0x00380000   /* Receive FCC2 Clock Source is CLK16 */
-
-#define CMXFCR_TF2CS_BRG5  0x00000000   /* Transmit FCC2 Clock Source is BRG5 */
-#define CMXFCR_TF2CS_BRG6  0x00010000   /* Transmit FCC2 Clock Source is BRG6 */
-#define CMXFCR_TF2CS_BRG7  0x00020000   /* Transmit FCC2 Clock Source is BRG7 */
-#define CMXFCR_TF2CS_BRG8  0x00030000   /* Transmit FCC2 Clock Source is BRG8 */
-#define CMXFCR_TF2CS_CLK13 0x00040000   /* Transmit FCC2 Clock Source is CLK13 */
-#define CMXFCR_TF2CS_CLK14 0x00050000   /* Transmit FCC2 Clock Source is CLK14 */
-#define CMXFCR_TF2CS_CLK15 0x00060000   /* Transmit FCC2 Clock Source is CLK15 */
-#define CMXFCR_TF2CS_CLK16 0x00070000   /* Transmit FCC2 Clock Source is CLK16 */
-
-#define CMXFCR_RF3CS_BRG5  0x00000000   /* Receive FCC3 Clock Source is BRG5 */
-#define CMXFCR_RF3CS_BRG6  0x00000800   /* Receive FCC3 Clock Source is BRG6 */
-#define CMXFCR_RF3CS_BRG7  0x00001000   /* Receive FCC3 Clock Source is BRG7 */
-#define CMXFCR_RF3CS_BRG8  0x00001800   /* Receive FCC3 Clock Source is BRG8 */
-#define CMXFCR_RF3CS_CLK13 0x00002000   /* Receive FCC3 Clock Source is CLK13 */
-#define CMXFCR_RF3CS_CLK14 0x00002800   /* Receive FCC3 Clock Source is CLK14 */
-#define CMXFCR_RF3CS_CLK15 0x00003000   /* Receive FCC3 Clock Source is CLK15 */
-#define CMXFCR_RF3CS_CLK16 0x00003800   /* Receive FCC3 Clock Source is CLK16 */
-
-#define CMXFCR_TF3CS_BRG5  0x00000000   /* Transmit FCC3 Clock Source is BRG5 */
-#define CMXFCR_TF3CS_BRG6  0x00000100   /* Transmit FCC3 Clock Source is BRG6 */
-#define CMXFCR_TF3CS_BRG7  0x00000200   /* Transmit FCC3 Clock Source is BRG7 */
-#define CMXFCR_TF3CS_BRG8  0x00000300   /* Transmit FCC3 Clock Source is BRG8 */
-#define CMXFCR_TF3CS_CLK13 0x00000400   /* Transmit FCC3 Clock Source is CLK13 */
-#define CMXFCR_TF3CS_CLK14 0x00000500   /* Transmit FCC3 Clock Source is CLK14 */
-#define CMXFCR_TF3CS_CLK15 0x00000600   /* Transmit FCC3 Clock Source is CLK15 */
-#define CMXFCR_TF3CS_CLK16 0x00000700   /* Transmit FCC3 Clock Source is CLK16 */
-
-/*-----------------------------------------------------------------------
- * CMXSCR - CMX SCC Clock Route Register
- */
-#define CMXSCR_GR1         0x80000000   /* Grant Support of SCC1        */
-#define CMXSCR_SC1         0x40000000   /* SCC1 connection              */
-#define CMXSCR_RS1CS_MSK   0x38000000   /* Receive SCC1 Clock Source Mask */
-#define CMXSCR_TS1CS_MSK   0x07000000   /* Transmit SCC1 Clock Source Mask */
-#define CMXSCR_GR2         0x00800000   /* Grant Support of SCC2        */
-#define CMXSCR_SC2         0x00400000   /* SCC2 connection              */
-#define CMXSCR_RS2CS_MSK   0x00380000   /* Receive SCC2 Clock Source Mask */
-#define CMXSCR_TS2CS_MSK   0x00070000   /* Transmit SCC2 Clock Source Mask */
-#define CMXSCR_GR3         0x00008000   /* Grant Support of SCC3        */
-#define CMXSCR_SC3         0x00004000   /* SCC3 connection              */
-#define CMXSCR_RS3CS_MSK   0x00003800   /* Receive SCC3 Clock Source Mask */
-#define CMXSCR_TS3CS_MSK   0x00000700   /* Transmit SCC3 Clock Source Mask */
-#define CMXSCR_GR4         0x00000080   /* Grant Support of SCC4        */
-#define CMXSCR_SC4         0x00000040   /* SCC4 connection              */
-#define CMXSCR_RS4CS_MSK   0x00000038   /* Receive SCC4 Clock Source Mask */
-#define CMXSCR_TS4CS_MSK   0x00000007   /* Transmit SCC4 Clock Source Mask */
-
-#define CMXSCR_RS1CS_BRG1  0x00000000   /* SCC1 Rx Clock Source is BRG1 */
-#define CMXSCR_RS1CS_BRG2  0x08000000   /* SCC1 Rx Clock Source is BRG2 */
-#define CMXSCR_RS1CS_BRG3  0x10000000   /* SCC1 Rx Clock Source is BRG3 */
-#define CMXSCR_RS1CS_BRG4  0x18000000   /* SCC1 Rx Clock Source is BRG4 */
-#define CMXSCR_RS1CS_CLK11 0x20000000   /* SCC1 Rx Clock Source is CLK11 */
-#define CMXSCR_RS1CS_CLK12 0x28000000   /* SCC1 Rx Clock Source is CLK12 */
-#define CMXSCR_RS1CS_CLK3  0x30000000   /* SCC1 Rx Clock Source is CLK3 */
-#define CMXSCR_RS1CS_CLK4  0x38000000   /* SCC1 Rx Clock Source is CLK4 */
-
-#define CMXSCR_TS1CS_BRG1  0x00000000   /* SCC1 Tx Clock Source is BRG1 */
-#define CMXSCR_TS1CS_BRG2  0x01000000   /* SCC1 Tx Clock Source is BRG2 */
-#define CMXSCR_TS1CS_BRG3  0x02000000   /* SCC1 Tx Clock Source is BRG3 */
-#define CMXSCR_TS1CS_BRG4  0x03000000   /* SCC1 Tx Clock Source is BRG4 */
-#define CMXSCR_TS1CS_CLK11 0x04000000   /* SCC1 Tx Clock Source is CLK11 */
-#define CMXSCR_TS1CS_CLK12 0x05000000   /* SCC1 Tx Clock Source is CLK12 */
-#define CMXSCR_TS1CS_CLK3  0x06000000   /* SCC1 Tx Clock Source is CLK3 */
-#define CMXSCR_TS1CS_CLK4  0x07000000   /* SCC1 Tx Clock Source is CLK4 */
-
-#define CMXSCR_RS2CS_BRG1  0x00000000   /* SCC2 Rx Clock Source is BRG1 */
-#define CMXSCR_RS2CS_BRG2  0x00080000   /* SCC2 Rx Clock Source is BRG2 */
-#define CMXSCR_RS2CS_BRG3  0x00100000   /* SCC2 Rx Clock Source is BRG3 */
-#define CMXSCR_RS2CS_BRG4  0x00180000   /* SCC2 Rx Clock Source is BRG4 */
-#define CMXSCR_RS2CS_CLK11 0x00200000   /* SCC2 Rx Clock Source is CLK11 */
-#define CMXSCR_RS2CS_CLK12 0x00280000   /* SCC2 Rx Clock Source is CLK12 */
-#define CMXSCR_RS2CS_CLK3  0x00300000   /* SCC2 Rx Clock Source is CLK3 */
-#define CMXSCR_RS2CS_CLK4  0x00380000   /* SCC2 Rx Clock Source is CLK4 */
-
-#define CMXSCR_TS2CS_BRG1  0x00000000   /* SCC2 Tx Clock Source is BRG1 */
-#define CMXSCR_TS2CS_BRG2  0x00010000   /* SCC2 Tx Clock Source is BRG2 */
-#define CMXSCR_TS2CS_BRG3  0x00020000   /* SCC2 Tx Clock Source is BRG3 */
-#define CMXSCR_TS2CS_BRG4  0x00030000   /* SCC2 Tx Clock Source is BRG4 */
-#define CMXSCR_TS2CS_CLK11 0x00040000   /* SCC2 Tx Clock Source is CLK11 */
-#define CMXSCR_TS2CS_CLK12 0x00050000   /* SCC2 Tx Clock Source is CLK12 */
-#define CMXSCR_TS2CS_CLK3  0x00060000   /* SCC2 Tx Clock Source is CLK3 */
-#define CMXSCR_TS2CS_CLK4  0x00070000   /* SCC2 Tx Clock Source is CLK4 */
-
-#define CMXSCR_RS3CS_BRG1  0x00000000   /* SCC3 Rx Clock Source is BRG1 */
-#define CMXSCR_RS3CS_BRG2  0x00000800   /* SCC3 Rx Clock Source is BRG2 */
-#define CMXSCR_RS3CS_BRG3  0x00001000   /* SCC3 Rx Clock Source is BRG3 */
-#define CMXSCR_RS3CS_BRG4  0x00001800   /* SCC3 Rx Clock Source is BRG4 */
-#define CMXSCR_RS3CS_CLK5  0x00002000   /* SCC3 Rx Clock Source is CLK5 */
-#define CMXSCR_RS3CS_CLK6  0x00002800   /* SCC3 Rx Clock Source is CLK6 */
-#define CMXSCR_RS3CS_CLK7  0x00003000   /* SCC3 Rx Clock Source is CLK7 */
-#define CMXSCR_RS3CS_CLK8  0x00003800   /* SCC3 Rx Clock Source is CLK8 */
-
-#define CMXSCR_TS3CS_BRG1  0x00000000   /* SCC3 Tx Clock Source is BRG1 */
-#define CMXSCR_TS3CS_BRG2  0x00000100   /* SCC3 Tx Clock Source is BRG2 */
-#define CMXSCR_TS3CS_BRG3  0x00000200   /* SCC3 Tx Clock Source is BRG3 */
-#define CMXSCR_TS3CS_BRG4  0x00000300   /* SCC3 Tx Clock Source is BRG4 */
-#define CMXSCR_TS3CS_CLK5  0x00000400   /* SCC3 Tx Clock Source is CLK5 */
-#define CMXSCR_TS3CS_CLK6  0x00000500   /* SCC3 Tx Clock Source is CLK6 */
-#define CMXSCR_TS3CS_CLK7  0x00000600   /* SCC3 Tx Clock Source is CLK7 */
-#define CMXSCR_TS3CS_CLK8  0x00000700   /* SCC3 Tx Clock Source is CLK8 */
-
-#define CMXSCR_RS4CS_BRG1  0x00000000   /* SCC4 Rx Clock Source is BRG1 */
-#define CMXSCR_RS4CS_BRG2  0x00000008   /* SCC4 Rx Clock Source is BRG2 */
-#define CMXSCR_RS4CS_BRG3  0x00000010   /* SCC4 Rx Clock Source is BRG3 */
-#define CMXSCR_RS4CS_BRG4  0x00000018   /* SCC4 Rx Clock Source is BRG4 */
-#define CMXSCR_RS4CS_CLK5  0x00000020   /* SCC4 Rx Clock Source is CLK5 */
-#define CMXSCR_RS4CS_CLK6  0x00000028   /* SCC4 Rx Clock Source is CLK6 */
-#define CMXSCR_RS4CS_CLK7  0x00000030   /* SCC4 Rx Clock Source is CLK7 */
-#define CMXSCR_RS4CS_CLK8  0x00000038   /* SCC4 Rx Clock Source is CLK8 */
-
-#define CMXSCR_TS4CS_BRG1  0x00000000   /* SCC4 Tx Clock Source is BRG1 */
-#define CMXSCR_TS4CS_BRG2  0x00000001   /* SCC4 Tx Clock Source is BRG2 */
-#define CMXSCR_TS4CS_BRG3  0x00000002   /* SCC4 Tx Clock Source is BRG3 */
-#define CMXSCR_TS4CS_BRG4  0x00000003   /* SCC4 Tx Clock Source is BRG4 */
-#define CMXSCR_TS4CS_CLK5  0x00000004   /* SCC4 Tx Clock Source is CLK5 */
-#define CMXSCR_TS4CS_CLK6  0x00000005   /* SCC4 Tx Clock Source is CLK6 */
-#define CMXSCR_TS4CS_CLK7  0x00000006   /* SCC4 Tx Clock Source is CLK7 */
-#define CMXSCR_TS4CS_CLK8  0x00000007   /* SCC4 Tx Clock Source is CLK8 */
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration Register				 4-31
- */
-#define SIUMCR_BBD	0x80000000	/* Bus Busy Disable		*/
-#define SIUMCR_ESE	0x40000000	/* External Snoop Enable	*/
-#define SIUMCR_PBSE	0x20000000	/* Parity Byte Select Enable	*/
-#define SIUMCR_CDIS	0x10000000	/* Core Disable			*/
-#define SIUMCR_DPPC00	0x00000000	/* Data Parity Pins Configuration*/
-#define SIUMCR_DPPC01	0x04000000	/* - " -			*/
-#define SIUMCR_DPPC10	0x08000000	/* - " -			*/
-#define SIUMCR_DPPC11	0x0c000000	/* - " -			*/
-#define SIUMCR_L2CPC00	0x00000000	/* L2 Cache Pins Configuration	*/
-#define SIUMCR_L2CPC01	0x01000000	/* - " -			*/
-#define SIUMCR_L2CPC10	0x02000000	/* - " -			*/
-#define SIUMCR_L2CPC11	0x03000000	/* - " -			*/
-#define SIUMCR_LBPC00	0x00000000	/* Local Bus Pins Configuration	*/
-#define SIUMCR_LBPC01	0x00400000	/* - " -			*/
-#define SIUMCR_LBPC10	0x00800000	/* - " -			*/
-#define SIUMCR_LBPC11	0x00c00000	/* - " -			*/
-#define SIUMCR_APPC00	0x00000000	/* Address Parity Pins Configuration*/
-#define SIUMCR_APPC01	0x00100000	/* - " -			*/
-#define SIUMCR_APPC10	0x00200000	/* - " -			*/
-#define SIUMCR_APPC11	0x00300000	/* - " -			*/
-#define SIUMCR_CS10PC00	0x00000000	/* CS10 Pin Configuration	*/
-#define SIUMCR_CS10PC01	0x00040000	/* - " -			*/
-#define SIUMCR_CS10PC10	0x00080000	/* - " -			*/
-#define SIUMCR_CS10PC11	0x000c0000	/* - " -			*/
-#define SIUMCR_BCTLC00	0x00000000	/* Buffer Control Configuration	*/
-#define SIUMCR_BCTLC01	0x00010000	/* - " -			*/
-#define SIUMCR_BCTLC10	0x00020000	/* - " -			*/
-#define SIUMCR_BCTLC11	0x00030000	/* - " -			*/
-#define SIUMCR_MMR00	0x00000000	/* Mask Masters Requests	*/
-#define SIUMCR_MMR01	0x00004000	/* - " -			*/
-#define SIUMCR_MMR10	0x00008000	/* - " -			*/
-#define SIUMCR_MMR11	0x0000c000	/* - " -			*/
-#define SIUMCR_LPBSE	0x00002000	/* LocalBus Parity Byte Select Enable*/
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock Control Register					 9-8
-*/
-#define SCCR_PCI_MODE	0x00000100	/* PCI Mode	*/
-#define SCCR_PCI_MODCK	0x00000080	/* Value of PCI_MODCK pin	*/
-#define SCCR_PCIDF_MSK	0x00000078	/* PCI division factor	*/
-#define SCCR_PCIDF_SHIFT 3
-
-#ifndef CPM_IMMR_OFFSET
-#define CPM_IMMR_OFFSET	0x101a8
-#endif
-
-#define FCC_PSMR_RMII	((uint)0x00020000)	/* Use RMII interface */
-
-/* FCC iop & clock configuration. BSP code is responsible to define Fx_RXCLK & Fx_TXCLK
- * in order to use clock-computing stuff below for the FCC x
- */
-
-/* Automatically generates register configurations */
-#define PC_CLK(x)	((uint)(1<<(x-1)))	/* FCC CLK I/O ports */
-
-#define CMXFCR_RF1CS(x)	((uint)((x-5)<<27))	/* FCC1 Receive Clock Source */
-#define CMXFCR_TF1CS(x)	((uint)((x-5)<<24))	/* FCC1 Transmit Clock Source */
-#define CMXFCR_RF2CS(x)	((uint)((x-9)<<19))	/* FCC2 Receive Clock Source */
-#define CMXFCR_TF2CS(x) ((uint)((x-9)<<16))	/* FCC2 Transmit Clock Source */
-#define CMXFCR_RF3CS(x)	((uint)((x-9)<<11))	/* FCC3 Receive Clock Source */
-#define CMXFCR_TF3CS(x) ((uint)((x-9)<<8))	/* FCC3 Transmit Clock Source */
-
-#define PC_F1RXCLK	PC_CLK(F1_RXCLK)
-#define PC_F1TXCLK	PC_CLK(F1_TXCLK)
-#define CMX1_CLK_ROUTE	(CMXFCR_RF1CS(F1_RXCLK) | CMXFCR_TF1CS(F1_TXCLK))
-#define CMX1_CLK_MASK	((uint)0xff000000)
-
-#define PC_F2RXCLK	PC_CLK(F2_RXCLK)
-#define PC_F2TXCLK	PC_CLK(F2_TXCLK)
-#define CMX2_CLK_ROUTE	(CMXFCR_RF2CS(F2_RXCLK) | CMXFCR_TF2CS(F2_TXCLK))
-#define CMX2_CLK_MASK	((uint)0x00ff0000)
-
-#define PC_F3RXCLK	PC_CLK(F3_RXCLK)
-#define PC_F3TXCLK	PC_CLK(F3_TXCLK)
-#define CMX3_CLK_ROUTE	(CMXFCR_RF3CS(F3_RXCLK) | CMXFCR_TF3CS(F3_TXCLK))
-#define CMX3_CLK_MASK	((uint)0x0000ff00)
-
-#define CPMUX_CLK_MASK (CMX3_CLK_MASK | CMX2_CLK_MASK)
-#define CPMUX_CLK_ROUTE (CMX3_CLK_ROUTE | CMX2_CLK_ROUTE)
-
-#define CLK_TRX (PC_F3TXCLK | PC_F3RXCLK | PC_F2TXCLK | PC_F2RXCLK)
-
-/* I/O Pin assignment for FCC1.  I don't yet know the best way to do this,
- * but there is little variation among the choices.
- */
-#define PA1_COL		0x00000001U
-#define PA1_CRS		0x00000002U
-#define PA1_TXER	0x00000004U
-#define PA1_TXEN	0x00000008U
-#define PA1_RXDV	0x00000010U
-#define PA1_RXER	0x00000020U
-#define PA1_TXDAT	0x00003c00U
-#define PA1_RXDAT	0x0003c000U
-#define PA1_PSORA0	(PA1_RXDAT | PA1_TXDAT)
-#define PA1_PSORA1	(PA1_COL | PA1_CRS | PA1_TXER | PA1_TXEN | \
-		PA1_RXDV | PA1_RXER)
-#define PA1_DIRA0	(PA1_RXDAT | PA1_CRS | PA1_COL | PA1_RXER | PA1_RXDV)
-#define PA1_DIRA1	(PA1_TXDAT | PA1_TXEN | PA1_TXER)
-
-
-/* I/O Pin assignment for FCC2.  I don't yet know the best way to do this,
- * but there is little variation among the choices.
- */
-#define PB2_TXER	0x00000001U
-#define PB2_RXDV	0x00000002U
-#define PB2_TXEN	0x00000004U
-#define PB2_RXER	0x00000008U
-#define PB2_COL		0x00000010U
-#define PB2_CRS		0x00000020U
-#define PB2_TXDAT	0x000003c0U
-#define PB2_RXDAT	0x00003c00U
-#define PB2_PSORB0	(PB2_RXDAT | PB2_TXDAT | PB2_CRS | PB2_COL | \
-		PB2_RXER | PB2_RXDV | PB2_TXER)
-#define PB2_PSORB1	(PB2_TXEN)
-#define PB2_DIRB0	(PB2_RXDAT | PB2_CRS | PB2_COL | PB2_RXER | PB2_RXDV)
-#define PB2_DIRB1	(PB2_TXDAT | PB2_TXEN | PB2_TXER)
-
-
-/* I/O Pin assignment for FCC3.  I don't yet know the best way to do this,
- * but there is little variation among the choices.
- */
-#define PB3_RXDV	0x00004000U
-#define PB3_RXER	0x00008000U
-#define PB3_TXER	0x00010000U
-#define PB3_TXEN	0x00020000U
-#define PB3_COL		0x00040000U
-#define PB3_CRS		0x00080000U
-#define PB3_TXDAT	0x0f000000U
-#define PC3_TXDAT	0x00000010U
-#define PB3_RXDAT	0x00f00000U
-#define PB3_PSORB0	(PB3_RXDAT | PB3_TXDAT | PB3_CRS | PB3_COL | \
-		PB3_RXER | PB3_RXDV | PB3_TXER | PB3_TXEN)
-#define PB3_PSORB1	0
-#define PB3_DIRB0	(PB3_RXDAT | PB3_CRS | PB3_COL | PB3_RXER | PB3_RXDV)
-#define PB3_DIRB1	(PB3_TXDAT | PB3_TXEN | PB3_TXER)
-#define PC3_DIRC1	(PC3_TXDAT)
-
-/* Handy macro to specify mem for FCCs*/
-#define FCC_MEM_OFFSET(x) (CPM_FCC_SPECIAL_BASE + (x*128))
-#define FCC1_MEM_OFFSET FCC_MEM_OFFSET(0)
-#define FCC2_MEM_OFFSET FCC_MEM_OFFSET(1)
-#define FCC3_MEM_OFFSET FCC_MEM_OFFSET(2)
-
-/* Clocks and GRG's */
-
-enum cpm_clk_dir {
-	CPM_CLK_RX,
-	CPM_CLK_TX,
-	CPM_CLK_RTX
-};
-
-enum cpm_clk_target {
-	CPM_CLK_SCC1,
-	CPM_CLK_SCC2,
-	CPM_CLK_SCC3,
-	CPM_CLK_SCC4,
-	CPM_CLK_FCC1,
-	CPM_CLK_FCC2,
-	CPM_CLK_FCC3
-};
-
-enum cpm_clk {
-	CPM_CLK_NONE = 0,
-	CPM_BRG1,	/* Baud Rate Generator  1 */
-	CPM_BRG2,	/* Baud Rate Generator  2 */
-	CPM_BRG3,	/* Baud Rate Generator  3 */
-	CPM_BRG4,	/* Baud Rate Generator  4 */
-	CPM_BRG5,	/* Baud Rate Generator  5 */
-	CPM_BRG6,	/* Baud Rate Generator  6 */
-	CPM_BRG7,	/* Baud Rate Generator  7 */
-	CPM_BRG8,	/* Baud Rate Generator  8 */
-	CPM_CLK1,	/* Clock  1 */
-	CPM_CLK2,	/* Clock  2 */
-	CPM_CLK3,	/* Clock  3 */
-	CPM_CLK4,	/* Clock  4 */
-	CPM_CLK5,	/* Clock  5 */
-	CPM_CLK6,	/* Clock  6 */
-	CPM_CLK7,	/* Clock  7 */
-	CPM_CLK8,	/* Clock  8 */
-	CPM_CLK9,	/* Clock  9 */
-	CPM_CLK10,	/* Clock 10 */
-	CPM_CLK11,	/* Clock 11 */
-	CPM_CLK12,	/* Clock 12 */
-	CPM_CLK13,	/* Clock 13 */
-	CPM_CLK14,	/* Clock 14 */
-	CPM_CLK15,	/* Clock 15 */
-	CPM_CLK16,	/* Clock 16 */
-	CPM_CLK17,	/* Clock 17 */
-	CPM_CLK18,	/* Clock 18 */
-	CPM_CLK19,	/* Clock 19 */
-	CPM_CLK20,	/* Clock 20 */
-	CPM_CLK_DUMMY
-};
-
-extern int cpm2_clk_setup(enum cpm_clk_target target, int clock, int mode);
-
-#endif /* __CPM2__ */
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/delay.h b/include/asm-ppc/delay.h
deleted file mode 100644
index badde6845af..00000000000
--- a/include/asm-ppc/delay.h
+++ /dev/null
@@ -1,66 +0,0 @@
-#ifdef __KERNEL__
-#ifndef _PPC_DELAY_H
-#define _PPC_DELAY_H
-
-#include <asm/param.h>
-
-/*
- * Copyright 1996, Paul Mackerras.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-extern unsigned long loops_per_jiffy;
-
-extern void __delay(unsigned int loops);
-
-/*
- * Note that 19 * 226 == 4294 ==~ 2^32 / 10^6, so
- * loops = (4294 * usecs * loops_per_jiffy * HZ) / 2^32.
- *
- * The mulhwu instruction gives us loops = (a * b) / 2^32.
- * We choose a = usecs * 19 * HZ and b = loops_per_jiffy * 226
- * because this lets us support a wide range of HZ and
- * loops_per_jiffy values without either a or b overflowing 2^32.
- * Thus we need usecs * HZ <= (2^32 - 1) / 19 = 226050910 and
- * loops_per_jiffy <= (2^32 - 1) / 226 = 19004280
- * (which corresponds to ~3800 bogomips at HZ = 100).
- *  -- paulus
- */
-#define __MAX_UDELAY	(226050910UL/HZ)	/* maximum udelay argument */
-#define __MAX_NDELAY	(4294967295UL/HZ)	/* maximum ndelay argument */
-
-extern __inline__ void __udelay(unsigned int x)
-{
-	unsigned int loops;
-
-	__asm__("mulhwu %0,%1,%2" : "=r" (loops) :
-		"r" (x), "r" (loops_per_jiffy * 226));
-	__delay(loops);
-}
-
-extern __inline__ void __ndelay(unsigned int x)
-{
-	unsigned int loops;
-
-	__asm__("mulhwu %0,%1,%2" : "=r" (loops) :
-		"r" (x), "r" (loops_per_jiffy * 5));
-	__delay(loops);
-}
-
-extern void __bad_udelay(void);		/* deliberately undefined */
-extern void __bad_ndelay(void);		/* deliberately undefined */
-
-#define udelay(n) (__builtin_constant_p(n)? \
-	((n) > __MAX_UDELAY? __bad_udelay(): __udelay((n) * (19 * HZ))) : \
-	__udelay((n) * (19 * HZ)))
-
-#define ndelay(n) (__builtin_constant_p(n)? \
-	((n) > __MAX_NDELAY? __bad_ndelay(): __ndelay((n) * HZ)) : \
-	__ndelay((n) * HZ))
-
-#endif /* defined(_PPC_DELAY_H) */
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/device.h b/include/asm-ppc/device.h
deleted file mode 100644
index d8f9872b0e2..00000000000
--- a/include/asm-ppc/device.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/*
- * Arch specific extensions to struct device
- *
- * This file is released under the GPLv2
- */
-#include <asm-generic/device.h>
-
diff --git a/include/asm-ppc/floppy.h b/include/asm-ppc/floppy.h
deleted file mode 100644
index 7d9b3f430d9..00000000000
--- a/include/asm-ppc/floppy.h
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
- * Architecture specific parts of the Floppy driver
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1995
- */
-#ifdef __KERNEL__
-#ifndef __ASM_PPC_FLOPPY_H
-#define __ASM_PPC_FLOPPY_H
-
-#define fd_inb(port)		inb_p(port)
-#define fd_outb(value,port)	outb_p(value,port)
-
-#define fd_disable_dma()	fd_ops->_disable_dma(FLOPPY_DMA)
-#define fd_free_dma()           fd_ops->_free_dma(FLOPPY_DMA)
-#define fd_get_dma_residue()    fd_ops->_get_dma_residue(FLOPPY_DMA)
-#define fd_dma_setup(addr, size, mode, io) fd_ops->_dma_setup(addr, size, mode, io)
-#define fd_enable_irq()         enable_irq(FLOPPY_IRQ)
-#define fd_disable_irq()        disable_irq(FLOPPY_IRQ)
-#define fd_free_irq()           free_irq(FLOPPY_IRQ, NULL);
-
-static int fd_request_dma(void);
-
-struct fd_dma_ops {
-	void (*_disable_dma)(unsigned int dmanr);
-	void (*_free_dma)(unsigned int dmanr);
-	int (*_get_dma_residue)(unsigned int dummy);
-	int (*_dma_setup)(char *addr, unsigned long size, int mode, int io);
-};
-
-static int virtual_dma_count;
-static int virtual_dma_residue;
-static char *virtual_dma_addr;
-static int virtual_dma_mode;
-static int doing_vdma;
-static struct fd_dma_ops *fd_ops;
-
-static irqreturn_t floppy_hardint(int irq, void *dev_id)
-{
-	unsigned char st;
-	int lcount;
-	char *lptr;
-
-	if (!doing_vdma)
-		return floppy_interrupt(irq, dev_id);
-
-
-	st = 1;
-	for (lcount=virtual_dma_count, lptr=virtual_dma_addr;
-	     lcount; lcount--, lptr++) {
-		st=inb(virtual_dma_port+4) & 0xa0 ;
-		if (st != 0xa0)
-			break;
-		if (virtual_dma_mode)
-			outb_p(*lptr, virtual_dma_port+5);
-		else
-			*lptr = inb_p(virtual_dma_port+5);
-	}
-	virtual_dma_count = lcount;
-	virtual_dma_addr = lptr;
-	st = inb(virtual_dma_port+4);
-
-	if (st == 0x20)
-		return IRQ_HANDLED;
-	if (!(st & 0x20)) {
-		virtual_dma_residue += virtual_dma_count;
-		virtual_dma_count=0;
-		doing_vdma = 0;
-		floppy_interrupt(irq, dev_id);
-		return IRQ_HANDLED;
-	}
-	return IRQ_HANDLED;
-}
-
-static void vdma_disable_dma(unsigned int dummy)
-{
-	doing_vdma = 0;
-	virtual_dma_residue += virtual_dma_count;
-	virtual_dma_count=0;
-}
-
-static void vdma_nop(unsigned int dummy)
-{
-}
-
-
-static int vdma_get_dma_residue(unsigned int dummy)
-{
-	return virtual_dma_count + virtual_dma_residue;
-}
-
-
-static int fd_request_irq(void)
-{
-	if (can_use_virtual_dma)
-		return request_irq(FLOPPY_IRQ, floppy_hardint,
-				   IRQF_DISABLED, "floppy", NULL);
-	else
-		return request_irq(FLOPPY_IRQ, floppy_interrupt,
-				   IRQF_DISABLED, "floppy", NULL);
-}
-
-static int vdma_dma_setup(char *addr, unsigned long size, int mode, int io)
-{
-	doing_vdma = 1;
-	virtual_dma_port = io;
-	virtual_dma_mode = (mode  == DMA_MODE_WRITE);
-	virtual_dma_addr = addr;
-	virtual_dma_count = size;
-	virtual_dma_residue = 0;
-	return 0;
-}
-
-static int hard_dma_setup(char *addr, unsigned long size, int mode, int io)
-{
-	/* actual, physical DMA */
-	doing_vdma = 0;
-	clear_dma_ff(FLOPPY_DMA);
-	set_dma_mode(FLOPPY_DMA,mode);
-	set_dma_addr(FLOPPY_DMA,(unsigned int)virt_to_bus(addr));
-	set_dma_count(FLOPPY_DMA,size);
-	enable_dma(FLOPPY_DMA);
-	return 0;
-}
-
-static struct fd_dma_ops real_dma_ops =
-{
-	._disable_dma = disable_dma,
-	._free_dma = free_dma,
-	._get_dma_residue = get_dma_residue,
-	._dma_setup = hard_dma_setup
-};
-
-static struct fd_dma_ops virt_dma_ops =
-{
-	._disable_dma = vdma_disable_dma,
-	._free_dma = vdma_nop,
-	._get_dma_residue = vdma_get_dma_residue,
-	._dma_setup = vdma_dma_setup
-};
-
-static int fd_request_dma()
-{
-	if (can_use_virtual_dma & 1) {
-		fd_ops = &virt_dma_ops;
-		return 0;
-	}
-	else {
-		fd_ops = &real_dma_ops;
-		return request_dma(FLOPPY_DMA, "floppy");
-	}
-}
-
-static int FDC1 = 0x3f0;
-static int FDC2 = -1;
-
-/*
- * Again, the CMOS information not available
- */
-#define FLOPPY0_TYPE 6
-#define FLOPPY1_TYPE 0
-
-#define N_FDC 2			/* Don't change this! */
-#define N_DRIVE 8
-
-/*
- * The PowerPC has no problems with floppy DMA crossing 64k borders.
- */
-#define CROSS_64KB(a,s)	(0)
-
-#endif /* __ASM_PPC_FLOPPY_H */
-
-#define EXTRA_FLOPPY_PARAMS
-
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/fs_pd.h b/include/asm-ppc/fs_pd.h
deleted file mode 100644
index 8691327653a..00000000000
--- a/include/asm-ppc/fs_pd.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * Platform information definitions.
- *
- * 2006 (c) MontaVista Software, Inc.
- * Vitaly Bordug <vbordug@ru.mvista.com>
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-#ifndef FS_PD_H
-#define FS_PD_H
-
-static inline int uart_baudrate(void)
-{
-	int baud;
-	bd_t *bd = (bd_t *) __res;
-
-	if (bd->bi_baudrate)
-		baud = bd->bi_baudrate;
-	else
-		baud = -1;
-	return baud;
-}
-
-static inline int uart_clock(void)
-{
-	return (((bd_t *) __res)->bi_intfreq);
-}
-
-#define cpm2_map(member)	(&cpm2_immr->member)
-#define cpm2_map_size(member, size)	(&cpm2_immr->member)
-#define cpm2_unmap(addr)        do {} while(0)
-
-#endif
diff --git a/include/asm-ppc/gg2.h b/include/asm-ppc/gg2.h
deleted file mode 100644
index 341ae55b99f..00000000000
--- a/include/asm-ppc/gg2.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- *  include/asm-ppc/gg2.h -- VLSI VAS96011/12 `Golden Gate 2' register definitions
- *
- *  Copyright (C) 1997 Geert Uytterhoeven
- *
- *  This file is based on the following documentation:
- *
- *	The VAS96011/12 Chipset, Data Book, Edition 1.0
- *	VLSI Technology, Inc.
- *
- *  This file is subject to the terms and conditions of the GNU General Public
- *  License.  See the file COPYING in the main directory of this archive
- *  for more details.
- */
-
-#ifndef _ASMPPC_GG2_H
-#define _ASMPPC_GG2_H
-
-    /*
-     *  Memory Map (CHRP mode)
-     */
-
-#define GG2_PCI_MEM_BASE	0xc0000000	/* Peripheral memory space */
-#define GG2_ISA_MEM_BASE	0xf7000000	/* Peripheral memory alias */
-#define GG2_ISA_IO_BASE		0xf8000000	/* Peripheral I/O space */
-#define GG2_PCI_CONFIG_BASE	0xfec00000	/* PCI configuration space */
-#define GG2_INT_ACK_SPECIAL	0xfec80000	/* Interrupt acknowledge and */
-						/* special PCI cycles */
-#define GG2_ROM_BASE0		0xff000000	/* ROM bank 0 */
-#define GG2_ROM_BASE1		0xff800000	/* ROM bank 1 */
-
-
-    /*
-     *  GG2 specific PCI Registers
-     */
-
-extern void __iomem *gg2_pci_config_base;	/* kernel virtual address */
-
-#define GG2_PCI_BUSNO		0x40	/* Bus number */
-#define GG2_PCI_SUBBUSNO	0x41	/* Subordinate bus number */
-#define GG2_PCI_DISCCTR		0x42	/* Disconnect counter */
-#define GG2_PCI_PPC_CTRL	0x50	/* PowerPC interface control register */
-#define GG2_PCI_ADDR_MAP	0x5c	/* Address map */
-#define GG2_PCI_PCI_CTRL	0x60	/* PCI interface control register */
-#define GG2_PCI_ROM_CTRL	0x70	/* ROM interface control register */
-#define GG2_PCI_ROM_TIME	0x74	/* ROM timing */
-#define GG2_PCI_CC_CTRL		0x80	/* Cache controller control register */
-#define GG2_PCI_DRAM_BANK0	0x90	/* Control register for DRAM bank #0 */
-#define GG2_PCI_DRAM_BANK1	0x94	/* Control register for DRAM bank #1 */
-#define GG2_PCI_DRAM_BANK2	0x98	/* Control register for DRAM bank #2 */
-#define GG2_PCI_DRAM_BANK3	0x9c	/* Control register for DRAM bank #3 */
-#define GG2_PCI_DRAM_BANK4	0xa0	/* Control register for DRAM bank #4 */
-#define GG2_PCI_DRAM_BANK5	0xa4	/* Control register for DRAM bank #5 */
-#define GG2_PCI_DRAM_TIME0	0xb0	/* Timing parameters set #0 */
-#define GG2_PCI_DRAM_TIME1	0xb4	/* Timing parameters set #1 */
-#define GG2_PCI_DRAM_CTRL	0xc0	/* DRAM control */
-#define GG2_PCI_ERR_CTRL	0xd0	/* Error control register */
-#define GG2_PCI_ERR_STATUS	0xd4	/* Error status register */
-					/* Cleared when read */
-
-#endif /* _ASMPPC_GG2_H */
diff --git a/include/asm-ppc/gt64260.h b/include/asm-ppc/gt64260.h
deleted file mode 100644
index 9e63b3cfffc..00000000000
--- a/include/asm-ppc/gt64260.h
+++ /dev/null
@@ -1,322 +0,0 @@
-/*
- * include/asm-ppc/gt64260.h
- *
- * Prototypes, etc. for the Marvell/Galileo GT64260 host bridge routines.
- *
- * Author: Mark A. Greer <mgreer@mvista.com>
- *
- * 2001 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifndef __ASMPPC_GT64260_H
-#define __ASMPPC_GT64260_H
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/pci.h>
-#include <linux/slab.h>
-
-#include <asm/byteorder.h>
-#include <asm/io.h>
-#include <asm/irq.h>
-#include <asm/uaccess.h>
-#include <asm/machdep.h>
-#include <asm/pci-bridge.h>
-#include <asm/gt64260_defs.h>
-
-
-extern u32     gt64260_base;
-extern u32     gt64260_irq_base;     /* We handle the next 96 IRQs from here */
-extern u32     gt64260_revision;
-extern u8      gt64260_pci_exclude_bridge;
-
-#ifndef	TRUE
-#define	TRUE	1
-#endif
-
-#ifndef	FALSE
-#define	FALSE	0
-#endif
-
-/* IRQs defined by the 64260 */
-#define	GT64260_IRQ_MPSC0		40
-#define	GT64260_IRQ_MPSC1		42
-#define	GT64260_IRQ_SDMA		36
-
-/*
- * Define a default physical memory map to be set up on the bridge.
- * Also define a struct to pass that info from board-specific routines to
- * GT64260 generic set up routines.  By passing this info in, the board
- * support developer can modify it at will.
- */
-
-/*
- * This is the default memory map:
- *			CPU			PCI
- *			---			---
- * PCI 0 I/O:	0xfa000000-0xfaffffff	0x00000000-0x00ffffff
- * PCI 1 I/O:	0xfb000000-0xfbffffff	0x01000000-0x01ffffff
- * PCI 0 MEM:	0x80000000-0x8fffffff	0x80000000-0x8fffffff
- * PCI 1 MEM:	0x90000000-0x9fffffff	0x90000000-0x9fffffff
- */
-
-/* Default physical memory map for the GT64260 bridge */
-
-/*
- * PCI Bus 0 Definitions
- */
-#define GT64260_PCI_0_IO_SIZE		0x01000000U
-#define	GT64260_PCI_0_MEM_SIZE		0x10000000U
-
-/* Processor Physical addresses */
-#define	GT64260_PCI_0_IO_START_PROC	0xfa000000U
-#define	GT64260_PCI_0_IO_END_PROC	(GT64260_PCI_0_IO_START_PROC + \
-					 GT64260_PCI_0_IO_SIZE - 1)
-
-/* PCI 0 addresses */
-#define	GT64260_PCI_0_IO_START		0x00000000U
-#define	GT64260_PCI_0_IO_END		(GT64260_PCI_0_IO_START + \
-					 GT64260_PCI_0_IO_SIZE - 1)
-
-/* Processor Physical addresses */
-#define	GT64260_PCI_0_MEM_START_PROC	0x80000000U
-#define	GT64260_PCI_0_MEM_END_PROC	(GT64260_PCI_0_MEM_START_PROC + \
-					 GT64260_PCI_0_MEM_SIZE - 1)
-
-/* PCI 0 addresses */
-#define	GT64260_PCI_0_MEM_START		0x80000000U
-#define	GT64260_PCI_0_MEM_END		(GT64260_PCI_0_MEM_START + \
-					 GT64260_PCI_0_MEM_SIZE - 1)
-
-/*
- * PCI Bus 1 Definitions
- */
-#define GT64260_PCI_1_IO_SIZE		0x01000000U
-#define	GT64260_PCI_1_MEM_SIZE		0x10000000U
-
-/* PCI 1 addresses */
-#define	GT64260_PCI_1_IO_START		0x01000000U
-#define	GT64260_PCI_1_IO_END		(GT64260_PCI_1_IO_START + \
-					 GT64260_PCI_1_IO_SIZE - 1)
-
-/* Processor Physical addresses */
-#define	GT64260_PCI_1_IO_START_PROC	0xfb000000U
-#define	GT64260_PCI_1_IO_END_PROC	(GT64260_PCI_1_IO_START_PROC + \
-					 GT64260_PCI_1_IO_SIZE - 1)
-
-/* PCI 1 addresses */
-#define	GT64260_PCI_1_MEM_START		0x90000000U
-#define	GT64260_PCI_1_MEM_END		(GT64260_PCI_1_MEM_START + \
-					 GT64260_PCI_1_MEM_SIZE - 1)
-
-/* Processor Physical addresses */
-#define	GT64260_PCI_1_MEM_START_PROC	0x90000000U
-#define	GT64260_PCI_1_MEM_END_PROC	(GT64260_PCI_1_MEM_START_PROC + \
-					 GT64260_PCI_1_MEM_SIZE - 1)
-
-/* Define struct to pass mem-map info into gt64260_common.c code */
-typedef struct {
-	struct pci_controller	*hose_a;
-	struct pci_controller	*hose_b;
-
-	u32	mem_size;
-
-	u32	pci_0_io_start_proc;
-	u32	pci_0_io_start_pci;
-	u32	pci_0_io_size;
-	u32	pci_0_io_swap;
-
-	u32	pci_0_mem_start_proc;
-	u32	pci_0_mem_start_pci_hi;
-	u32	pci_0_mem_start_pci_lo;
-	u32	pci_0_mem_size;
-	u32	pci_0_mem_swap;
-
-	u32	pci_1_io_start_proc;
-	u32	pci_1_io_start_pci;
-	u32	pci_1_io_size;
-	u32	pci_1_io_swap;
-
-	u32	pci_1_mem_start_proc;
-	u32	pci_1_mem_start_pci_hi;
-	u32	pci_1_mem_start_pci_lo;
-	u32	pci_1_mem_size;
-	u32	pci_1_mem_swap;
-} gt64260_bridge_info_t;
-
-#define	GT64260_BRIDGE_INFO_DEFAULT(ip, ms) {				\
-	(ip)->mem_size = (ms);						\
-									\
-	(ip)->pci_0_io_start_proc = GT64260_PCI_0_IO_START_PROC;	\
-	(ip)->pci_0_io_start_pci  = GT64260_PCI_0_IO_START;		\
-	(ip)->pci_0_io_size	  = GT64260_PCI_0_IO_SIZE;		\
-	(ip)->pci_0_io_swap	  = GT64260_CPU_PCI_SWAP_NONE;		\
-									\
-	(ip)->pci_0_mem_start_proc   = GT64260_PCI_0_MEM_START_PROC;	\
-	(ip)->pci_0_mem_start_pci_hi = 0x00000000;			\
-	(ip)->pci_0_mem_start_pci_lo = GT64260_PCI_0_MEM_START;		\
-	(ip)->pci_0_mem_size	     = GT64260_PCI_0_MEM_SIZE;		\
-	(ip)->pci_0_mem_swap	     = GT64260_CPU_PCI_SWAP_NONE;	\
-									\
-	(ip)->pci_1_io_start_proc = GT64260_PCI_1_IO_START_PROC;	\
-	(ip)->pci_1_io_start_pci  = GT64260_PCI_1_IO_START;		\
-	(ip)->pci_1_io_size	  = GT64260_PCI_1_IO_SIZE;		\
-	(ip)->pci_1_io_swap	  = GT64260_CPU_PCI_SWAP_NONE;		\
-									\
-	(ip)->pci_1_mem_start_proc   = GT64260_PCI_1_MEM_START_PROC;	\
-	(ip)->pci_1_mem_start_pci_hi = 0x00000000;			\
-	(ip)->pci_1_mem_start_pci_lo = GT64260_PCI_1_MEM_START;		\
-	(ip)->pci_1_mem_size	     = GT64260_PCI_1_MEM_SIZE;		\
-	(ip)->pci_1_mem_swap	     = GT64260_CPU_PCI_SWAP_NONE;	\
-}
-
-/*
- *****************************************************************************
- *
- *	I/O macros to access the 64260's registers
- *
- *****************************************************************************
- */
-
-extern inline uint32_t gt_read(uint32_t offs){
-	return (in_le32((volatile uint *)(gt64260_base + offs)));
-}
-extern inline void gt_write(uint32_t offs, uint32_t d){
-	out_le32((volatile uint *)(gt64260_base + offs), d);
-}
-
-#if 0 /* paranoid SMP version */
-extern inline void gt_modify(u32 offs, u32 data, u32 mask) \
-{
-	uint32_t reg;
-	spin_lock(&gt64260_lock);
-	reg = gt_read(offs) & (~mask); /* zero any bits we care about*/
-	reg |= data & mask; /* set bits from the data */
-	gt_write(offs, reg);
-	spin_unlock(&gt64260_lock);
-}
-#else
-extern inline void gt_modify(uint32_t offs, uint32_t data, uint32_t mask)
-{
-	uint32_t reg;
-	reg = gt_read(offs) & (~(mask)); /* zero any bits we care about*/
-	reg |= (data) & (mask); /* set bits from the data */
-	gt_write(offs, reg);
-}
-#endif
-#define	gt_set_bits(offs, bits) gt_modify(offs, ~0, bits)
-
-#define	gt_clr_bits(offs, bits) gt_modify(offs, 0, bits)
-
-
-/*
- *****************************************************************************
- *
- *	Function Prototypes
- *
- *****************************************************************************
- */
-
-int gt64260_find_bridges(u32 phys_base_addr, gt64260_bridge_info_t *info,
-	int ((*map_irq)(struct pci_dev *, unsigned char, unsigned char)));
-int gt64260_bridge_init(gt64260_bridge_info_t *info);
-int gt64260_cpu_scs_set_window(u32 window,
-			       u32 base_addr,
-			       u32 size);
-int gt64260_cpu_cs_set_window(u32 window,
-			      u32 base_addr,
-			      u32 size);
-int gt64260_cpu_boot_set_window(u32 base_addr,
-			        u32 size);
-int gt64260_cpu_set_pci_io_window(u32 pci_bus,
-			          u32 cpu_base_addr,
-			          u32 pci_base_addr,
-			          u32 size,
-			          u32 swap);
-int gt64260_cpu_set_pci_mem_window(u32 pci_bus,
-			           u32 window,
-			           u32 cpu_base_addr,
-			           u32 pci_base_addr_hi,
-			           u32 pci_base_addr_lo,
-			           u32 size,
-			           u32 swap_64bit);
-int gt64260_cpu_prot_set_window(u32 window,
-			        u32 base_addr,
-			        u32 size,
-			        u32 access_bits);
-int gt64260_cpu_snoop_set_window(u32 window,
-			         u32 base_addr,
-			         u32 size,
-			         u32  snoop_type);
-void gt64260_cpu_disable_all_windows(void);
-int gt64260_pci_bar_enable(u32 pci_bus, u32 enable_bits);
-int gt64260_pci_slave_scs_set_window(struct pci_controller *hose,
-				     u32 window,
-				     u32 pci_base_addr,
-				     u32 cpu_base_addr,
-				     u32 size);
-int gt64260_pci_slave_cs_set_window(struct pci_controller *hose,
-				    u32 window,
-				    u32 pci_base_addr,
-				    u32 cpu_base_addr,
-				    u32 size);
-int gt64260_pci_slave_boot_set_window(struct pci_controller *hose,
-				      u32 pci_base_addr,
-				      u32 cpu_base_addr,
-				      u32 size);
-int gt64260_pci_slave_p2p_mem_set_window(struct pci_controller *hose,
-				         u32 window,
-				         u32 pci_base_addr,
-				         u32 other_bus_base_addr,
-				         u32 size);
-int gt64260_pci_slave_p2p_io_set_window(struct pci_controller *hose,
-				        u32 pci_base_addr,
-				        u32 other_bus_base_addr,
-				        u32 size);
-int gt64260_pci_slave_dac_scs_set_window(struct pci_controller *hose,
-				         u32 window,
-				         u32 pci_base_addr_hi,
-				         u32 pci_base_addr_lo,
-				         u32 cpu_base_addr,
-				         u32 size);
-int gt64260_pci_slave_dac_cs_set_window(struct pci_controller *hose,
-				        u32 window,
-				        u32 pci_base_addr_hi,
-				        u32 pci_base_addr_lo,
-				        u32 cpu_base_addr,
-				        u32 size);
-int gt64260_pci_slave_dac_boot_set_window(struct pci_controller *hose,
-				          u32 pci_base_addr_hi,
-				          u32 pci_base_addr_lo,
-				          u32 cpu_base_addr,
-				          u32 size);
-int gt64260_pci_slave_dac_p2p_mem_set_window(struct pci_controller *hose,
-				             u32 window,
-				             u32 pci_base_addr_hi,
-				             u32 pci_base_addr_lo,
-				             u32 other_bus_base_addr,
-				             u32 size);
-int gt64260_pci_acc_cntl_set_window(u32 pci_bus,
-			            u32 window,
-			            u32 base_addr_hi,
-			            u32 base_addr_lo,
-			            u32 size,
-			            u32 features);
-int gt64260_pci_snoop_set_window(u32 pci_bus,
-			         u32 window,
-			         u32 base_addr_hi,
-			         u32 base_addr_lo,
-			         u32 size,
-			         u32 snoop_type);
-int gt64260_set_base(u32 new_base);
-int gt64260_get_base(u32 *base);
-int gt64260_pci_exclude_device(u8 bus, u8 devfn);
-
-void gt64260_init_irq(void);
-int gt64260_get_irq(void);
-
-void gt64260_mpsc_progress(char *s, unsigned short hex);
-
-#endif /* __ASMPPC_GT64260_H */
diff --git a/include/asm-ppc/gt64260_defs.h b/include/asm-ppc/gt64260_defs.h
deleted file mode 100644
index 6ffd01a5373..00000000000
--- a/include/asm-ppc/gt64260_defs.h
+++ /dev/null
@@ -1,1010 +0,0 @@
-/*
- * include/asm-ppc/gt64260_defs.h
- *
- * Register definitions for the Marvell/Galileo GT64260 host bridge.
- *
- * Author: Mark A. Greer <mgreer@mvista.com>
- *
- * 2001 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifndef __ASMPPC_GT64260_DEFS_H
-#define __ASMPPC_GT64260_DEFS_H
-
-/*
- * Define a macro to represent the supported version of the 64260.
- */
-#define	GT64260			0x01
-#define	GT64260A		0x10
-
-/*
- *****************************************************************************
- *
- *	CPU Interface Registers
- *
- *****************************************************************************
- */
-
-/* CPU physical address of 64260's registers */
-#define GT64260_INTERNAL_SPACE_DECODE			0x0068
-#define GT64260_INTERNAL_SPACE_SIZE			0x10000
-#define GT64260_INTERNAL_SPACE_DEFAULT_ADDR		0x14000000
-
-/* CPU Memory Controller Window Registers (4 windows) */
-#define	GT64260_CPU_SCS_DECODE_WINDOWS			4
-
-#define	GT64260_CPU_SCS_DECODE_0_BOT			0x0008
-#define	GT64260_CPU_SCS_DECODE_0_TOP			0x0010
-#define	GT64260_CPU_SCS_DECODE_1_BOT			0x0208
-#define	GT64260_CPU_SCS_DECODE_1_TOP			0x0210
-#define	GT64260_CPU_SCS_DECODE_2_BOT			0x0018
-#define	GT64260_CPU_SCS_DECODE_2_TOP			0x0020
-#define	GT64260_CPU_SCS_DECODE_3_BOT			0x0218
-#define	GT64260_CPU_SCS_DECODE_3_TOP			0x0220
-
-/* CPU Device Controller Window Registers (4 windows) */
-#define	GT64260_CPU_CS_DECODE_WINDOWS			4
-
-#define	GT64260_CPU_CS_DECODE_0_BOT			0x0028
-#define	GT64260_CPU_CS_DECODE_0_TOP			0x0030
-#define	GT64260_CPU_CS_DECODE_1_BOT			0x0228
-#define	GT64260_CPU_CS_DECODE_1_TOP			0x0230
-#define	GT64260_CPU_CS_DECODE_2_BOT			0x0248
-#define	GT64260_CPU_CS_DECODE_2_TOP			0x0250
-#define	GT64260_CPU_CS_DECODE_3_BOT			0x0038
-#define	GT64260_CPU_CS_DECODE_3_TOP			0x0040
-
-#define	GT64260_CPU_BOOT_CS_DECODE_0_BOT		0x0238
-#define	GT64260_CPU_BOOT_CS_DECODE_0_TOP		0x0240
-
-/* CPU Windows to PCI space (2 PCI buses each w/ 1 I/O & 4 MEM windows) */
-#define	GT64260_PCI_BUSES				2
-#define	GT64260_PCI_IO_WINDOWS_PER_BUS			1
-#define	GT64260_PCI_MEM_WINDOWS_PER_BUS			4
-
-#define	GT64260_CPU_PCI_SWAP_BYTE			0x00000000
-#define	GT64260_CPU_PCI_SWAP_NONE			0x01000000
-#define	GT64260_CPU_PCI_SWAP_BYTE_WORD			0x02000000
-#define	GT64260_CPU_PCI_SWAP_WORD			0x03000000
-#define	GT64260_CPU_PCI_SWAP_MASK			0x07000000
-
-#define	GT64260_CPU_PCI_MEM_REQ64			(1<<27)
-
-#define	GT64260_CPU_PCI_0_IO_DECODE_BOT			0x0048
-#define	GT64260_CPU_PCI_0_IO_DECODE_TOP			0x0050
-#define	GT64260_CPU_PCI_0_MEM_0_DECODE_BOT		0x0058
-#define	GT64260_CPU_PCI_0_MEM_0_DECODE_TOP		0x0060
-#define	GT64260_CPU_PCI_0_MEM_1_DECODE_BOT		0x0080
-#define	GT64260_CPU_PCI_0_MEM_1_DECODE_TOP		0x0088
-#define	GT64260_CPU_PCI_0_MEM_2_DECODE_BOT		0x0258
-#define	GT64260_CPU_PCI_0_MEM_2_DECODE_TOP		0x0260
-#define	GT64260_CPU_PCI_0_MEM_3_DECODE_BOT		0x0280
-#define	GT64260_CPU_PCI_0_MEM_3_DECODE_TOP		0x0288
-
-#define	GT64260_CPU_PCI_0_IO_REMAP			0x00f0
-#define	GT64260_CPU_PCI_0_MEM_0_REMAP_LO		0x00f8
-#define	GT64260_CPU_PCI_0_MEM_0_REMAP_HI		0x0320
-#define	GT64260_CPU_PCI_0_MEM_1_REMAP_LO		0x0100
-#define	GT64260_CPU_PCI_0_MEM_1_REMAP_HI		0x0328
-#define	GT64260_CPU_PCI_0_MEM_2_REMAP_LO		0x02f8
-#define	GT64260_CPU_PCI_0_MEM_2_REMAP_HI		0x0330
-#define	GT64260_CPU_PCI_0_MEM_3_REMAP_LO		0x0300
-#define	GT64260_CPU_PCI_0_MEM_3_REMAP_HI		0x0338
-
-#define	GT64260_CPU_PCI_1_IO_DECODE_BOT			0x0090
-#define	GT64260_CPU_PCI_1_IO_DECODE_TOP			0x0098
-#define	GT64260_CPU_PCI_1_MEM_0_DECODE_BOT		0x00a0
-#define	GT64260_CPU_PCI_1_MEM_0_DECODE_TOP		0x00a8
-#define	GT64260_CPU_PCI_1_MEM_1_DECODE_BOT		0x00b0
-#define	GT64260_CPU_PCI_1_MEM_1_DECODE_TOP		0x00b8
-#define	GT64260_CPU_PCI_1_MEM_2_DECODE_BOT		0x02a0
-#define	GT64260_CPU_PCI_1_MEM_2_DECODE_TOP		0x02a8
-#define	GT64260_CPU_PCI_1_MEM_3_DECODE_BOT		0x02b0
-#define	GT64260_CPU_PCI_1_MEM_3_DECODE_TOP		0x02b8
-
-#define	GT64260_CPU_PCI_1_IO_REMAP			0x0108
-#define	GT64260_CPU_PCI_1_MEM_0_REMAP_LO		0x0110
-#define	GT64260_CPU_PCI_1_MEM_0_REMAP_HI		0x0340
-#define	GT64260_CPU_PCI_1_MEM_1_REMAP_LO		0x0118
-#define	GT64260_CPU_PCI_1_MEM_1_REMAP_HI		0x0348
-#define	GT64260_CPU_PCI_1_MEM_2_REMAP_LO		0x0310
-#define	GT64260_CPU_PCI_1_MEM_2_REMAP_HI		0x0350
-#define	GT64260_CPU_PCI_1_MEM_3_REMAP_LO		0x0318
-#define	GT64260_CPU_PCI_1_MEM_3_REMAP_HI		0x0358
-
-/* CPU Control Registers */
-#define GT64260_CPU_CONFIG				0x0000
-#define GT64260_CPU_MODE				0x0120
-#define GT64260_CPU_MASTER_CNTL				0x0160
-#define GT64260_CPU_XBAR_CNTL_LO			0x0150
-#define GT64260_CPU_XBAR_CNTL_HI			0x0158
-#define GT64260_CPU_XBAR_TO				0x0168
-#define GT64260_CPU_RR_XBAR_CNTL_LO			0x0170
-#define GT64260_CPU_RR_XBAR_CNTL_HI			0x0178
-
-/* CPU Sync Barrier Registers */
-#define GT64260_CPU_SYNC_BARRIER_PCI_0			0x00c0
-#define GT64260_CPU_SYNC_BARRIER_PCI_1			0x00c8
-
-/* CPU Access Protection Registers */
-#define	GT64260_CPU_PROT_WINDOWS			8
-
-#define	GT64260_CPU_PROT_ACCPROTECT			(1<<16)
-#define	GT64260_CPU_PROT_WRPROTECT			(1<<17)
-#define	GT64260_CPU_PROT_CACHEPROTECT			(1<<18)
-
-#define GT64260_CPU_PROT_BASE_0				0x0180
-#define GT64260_CPU_PROT_TOP_0				0x0188
-#define GT64260_CPU_PROT_BASE_1				0x0190
-#define GT64260_CPU_PROT_TOP_1				0x0198
-#define GT64260_CPU_PROT_BASE_2				0x01a0
-#define GT64260_CPU_PROT_TOP_2				0x01a8
-#define GT64260_CPU_PROT_BASE_3				0x01b0
-#define GT64260_CPU_PROT_TOP_3				0x01b8
-#define GT64260_CPU_PROT_BASE_4				0x01c0
-#define GT64260_CPU_PROT_TOP_4				0x01c8
-#define GT64260_CPU_PROT_BASE_5				0x01d0
-#define GT64260_CPU_PROT_TOP_5				0x01d8
-#define GT64260_CPU_PROT_BASE_6				0x01e0
-#define GT64260_CPU_PROT_TOP_6				0x01e8
-#define GT64260_CPU_PROT_BASE_7				0x01f0
-#define GT64260_CPU_PROT_TOP_7				0x01f8
-
-/* CPU Snoop Control Registers */
-#define	GT64260_CPU_SNOOP_WINDOWS			4
-
-#define	GT64260_CPU_SNOOP_NONE				0x00000000
-#define	GT64260_CPU_SNOOP_WT				0x00010000
-#define	GT64260_CPU_SNOOP_WB				0x00020000
-#define	GT64260_CPU_SNOOP_MASK				0x00030000
-#define	GT64260_CPU_SNOOP_ALL_BITS			GT64260_CPU_SNOOP_MASK
-
-#define GT64260_CPU_SNOOP_BASE_0			0x0380
-#define GT64260_CPU_SNOOP_TOP_0				0x0388
-#define GT64260_CPU_SNOOP_BASE_1			0x0390
-#define GT64260_CPU_SNOOP_TOP_1				0x0398
-#define GT64260_CPU_SNOOP_BASE_2			0x03a0
-#define GT64260_CPU_SNOOP_TOP_2				0x03a8
-#define GT64260_CPU_SNOOP_BASE_3			0x03b0
-#define GT64260_CPU_SNOOP_TOP_3				0x03b8
-
-/* CPU Error Report Registers */
-#define GT64260_CPU_ERR_ADDR_LO				0x0070
-#define GT64260_CPU_ERR_ADDR_HI				0x0078
-#define GT64260_CPU_ERR_DATA_LO				0x0128
-#define GT64260_CPU_ERR_DATA_HI				0x0130
-#define GT64260_CPU_ERR_PARITY				0x0138
-#define GT64260_CPU_ERR_CAUSE				0x0140
-#define GT64260_CPU_ERR_MASK				0x0148
-
-
-/*
- *****************************************************************************
- *
- *	SDRAM Cotnroller Registers
- *
- *****************************************************************************
- */
-
-/* SDRAM Config Registers */
-#define	GT64260_SDRAM_CONFIG				0x0448
-#define	GT64260_SDRAM_OPERATION_MODE			0x0474
-#define	GT64260_SDRAM_ADDR_CNTL				0x047c
-#define	GT64260_SDRAM_TIMING_PARAMS			0x04b4
-#define	GT64260_SDRAM_UMA_CNTL				0x04a4
-#define	GT64260_SDRAM_XBAR_CNTL_LO			0x04a8
-#define	GT64260_SDRAM_XBAR_CNTL_HI			0x04ac
-#define	GT64260_SDRAM_XBAR_CNTL_TO			0x04b0
-
-/* SDRAM Banks Parameters Registers */
-#define	GT64260_SDRAM_BANK_PARAMS_0			0x044c
-#define	GT64260_SDRAM_BANK_PARAMS_1			0x0450
-#define	GT64260_SDRAM_BANK_PARAMS_2			0x0454
-#define	GT64260_SDRAM_BANK_PARAMS_3			0x0458
-
-/* SDRAM Error Report Registers */
-#define	GT64260_SDRAM_ERR_DATA_LO			0x0484
-#define	GT64260_SDRAM_ERR_DATA_HI			0x0480
-#define	GT64260_SDRAM_ERR_ADDR				0x0490
-#define	GT64260_SDRAM_ERR_ECC_RCVD			0x0488
-#define	GT64260_SDRAM_ERR_ECC_CALC			0x048c
-#define	GT64260_SDRAM_ERR_ECC_CNTL			0x0494
-#define	GT64260_SDRAM_ERR_ECC_ERR_CNT			0x0498
-
-
-/*
- *****************************************************************************
- *
- *	Device/BOOT Cotnroller Registers
- *
- *****************************************************************************
- */
-
-/* Device Control Registers */
-#define	GT64260_DEV_BANK_PARAMS_0			0x045c
-#define	GT64260_DEV_BANK_PARAMS_1			0x0460
-#define	GT64260_DEV_BANK_PARAMS_2			0x0464
-#define	GT64260_DEV_BANK_PARAMS_3			0x0468
-#define	GT64260_DEV_BOOT_PARAMS				0x046c
-#define	GT64260_DEV_IF_CNTL				0x04c0
-#define	GT64260_DEV_IF_XBAR_CNTL_LO			0x04c8
-#define	GT64260_DEV_IF_XBAR_CNTL_HI			0x04cc
-#define	GT64260_DEV_IF_XBAR_CNTL_TO			0x04c4
-
-/* Device Interrupt Registers */
-#define	GT64260_DEV_INTR_CAUSE				0x04d0
-#define	GT64260_DEV_INTR_MASK				0x04d4
-#define	GT64260_DEV_INTR_ERR_ADDR			0x04d8
-
-
-/*
- *****************************************************************************
- *
- *	PCI Bridge Interface Registers
- *
- *****************************************************************************
- */
-
-/* PCI Configuration Access Registers */
-#define	GT64260_PCI_0_CONFIG_ADDR			0x0cf8
-#define	GT64260_PCI_0_CONFIG_DATA			0x0cfc
-#define	GT64260_PCI_0_IACK				0x0c34
-
-#define	GT64260_PCI_1_CONFIG_ADDR			0x0c78
-#define	GT64260_PCI_1_CONFIG_DATA			0x0c7c
-#define	GT64260_PCI_1_IACK				0x0cb4
-
-/* PCI Control Registers */
-#define	GT64260_PCI_0_CMD				0x0c00
-#define	GT64260_PCI_0_MODE				0x0d00
-#define	GT64260_PCI_0_TO_RETRY				0x0c04
-#define	GT64260_PCI_0_RD_BUF_DISCARD_TIMER		0x0d04
-#define	GT64260_PCI_0_MSI_TRIGGER_TIMER			0x0c38
-#define	GT64260_PCI_0_ARBITER_CNTL			0x1d00
-#define	GT64260_PCI_0_XBAR_CNTL_LO			0x1d08
-#define	GT64260_PCI_0_XBAR_CNTL_HI			0x1d0c
-#define	GT64260_PCI_0_XBAR_CNTL_TO			0x1d04
-#define	GT64260_PCI_0_RD_RESP_XBAR_CNTL_LO		0x1d18
-#define	GT64260_PCI_0_RD_RESP_XBAR_CNTL_HI		0x1d1c
-#define	GT64260_PCI_0_SYNC_BARRIER			0x1d10
-#define	GT64260_PCI_0_P2P_CONFIG			0x1d14
-#define	GT64260_PCI_0_P2P_SWAP_CNTL			0x1d54
-
-#define	GT64260_PCI_1_CMD				0x0c80
-#define	GT64260_PCI_1_MODE				0x0d80
-#define	GT64260_PCI_1_TO_RETRY				0x0c84
-#define	GT64260_PCI_1_RD_BUF_DISCARD_TIMER		0x0d84
-#define	GT64260_PCI_1_MSI_TRIGGER_TIMER			0x0cb8
-#define	GT64260_PCI_1_ARBITER_CNTL			0x1d80
-#define	GT64260_PCI_1_XBAR_CNTL_LO			0x1d88
-#define	GT64260_PCI_1_XBAR_CNTL_HI			0x1d8c
-#define	GT64260_PCI_1_XBAR_CNTL_TO			0x1d84
-#define	GT64260_PCI_1_RD_RESP_XBAR_CNTL_LO		0x1d98
-#define	GT64260_PCI_1_RD_RESP_XBAR_CNTL_HI		0x1d9c
-#define	GT64260_PCI_1_SYNC_BARRIER			0x1d90
-#define	GT64260_PCI_1_P2P_CONFIG			0x1d94
-#define	GT64260_PCI_1_P2P_SWAP_CNTL			0x1dd4
-
-/* PCI Access Control Regions Registers */
-#define	GT64260_PCI_ACC_CNTL_WINDOWS			8
-
-#define	GT64260_PCI_ACC_CNTL_PREFETCHEN			(1<<12)
-#define	GT64260_PCI_ACC_CNTL_DREADEN			(1<<13)
-#define	GT64260_PCI_ACC_CNTL_RDPREFETCH			(1<<16)
-#define	GT64260_PCI_ACC_CNTL_RDLINEPREFETCH		(1<<17)
-#define	GT64260_PCI_ACC_CNTL_RDMULPREFETCH		(1<<18)
-#define	GT64260_PCI_ACC_CNTL_MBURST_4_WORDS		0x00000000
-#define	GT64260_PCI_ACC_CNTL_MBURST_8_WORDS		0x00100000
-#define	GT64260_PCI_ACC_CNTL_MBURST_16_WORDS		0x00200000
-#define	GT64260_PCI_ACC_CNTL_MBURST_MASK		0x00300000
-#define	GT64260_PCI_ACC_CNTL_SWAP_BYTE			0x00000000
-#define	GT64260_PCI_ACC_CNTL_SWAP_NONE			0x01000000
-#define	GT64260_PCI_ACC_CNTL_SWAP_BYTE_WORD		0x02000000
-#define	GT64260_PCI_ACC_CNTL_SWAP_WORD			0x03000000
-#define	GT64260_PCI_ACC_CNTL_SWAP_MASK			0x03000000
-#define	GT64260_PCI_ACC_CNTL_ACCPROT			(1<<28)
-#define	GT64260_PCI_ACC_CNTL_WRPROT			(1<<29)
-
-#define	GT64260_PCI_ACC_CNTL_ALL_BITS	(GT64260_PCI_ACC_CNTL_PREFETCHEN |    \
-					 GT64260_PCI_ACC_CNTL_DREADEN |       \
-					 GT64260_PCI_ACC_CNTL_RDPREFETCH |    \
-					 GT64260_PCI_ACC_CNTL_RDLINEPREFETCH |\
-					 GT64260_PCI_ACC_CNTL_RDMULPREFETCH | \
-					 GT64260_PCI_ACC_CNTL_MBURST_MASK |   \
-					 GT64260_PCI_ACC_CNTL_SWAP_MASK |     \
-					 GT64260_PCI_ACC_CNTL_ACCPROT|        \
-					 GT64260_PCI_ACC_CNTL_WRPROT)
-
-#define	GT64260_PCI_0_ACC_CNTL_0_BASE_LO		0x1e00
-#define	GT64260_PCI_0_ACC_CNTL_0_BASE_HI		0x1e04
-#define	GT64260_PCI_0_ACC_CNTL_0_TOP			0x1e08
-#define	GT64260_PCI_0_ACC_CNTL_1_BASE_LO		0x1e10
-#define	GT64260_PCI_0_ACC_CNTL_1_BASE_HI		0x1e14
-#define	GT64260_PCI_0_ACC_CNTL_1_TOP			0x1e18
-#define	GT64260_PCI_0_ACC_CNTL_2_BASE_LO		0x1e20
-#define	GT64260_PCI_0_ACC_CNTL_2_BASE_HI		0x1e24
-#define	GT64260_PCI_0_ACC_CNTL_2_TOP			0x1e28
-#define	GT64260_PCI_0_ACC_CNTL_3_BASE_LO		0x1e30
-#define	GT64260_PCI_0_ACC_CNTL_3_BASE_HI		0x1e34
-#define	GT64260_PCI_0_ACC_CNTL_3_TOP			0x1e38
-#define	GT64260_PCI_0_ACC_CNTL_4_BASE_LO		0x1e40
-#define	GT64260_PCI_0_ACC_CNTL_4_BASE_HI		0x1e44
-#define	GT64260_PCI_0_ACC_CNTL_4_TOP			0x1e48
-#define	GT64260_PCI_0_ACC_CNTL_5_BASE_LO		0x1e50
-#define	GT64260_PCI_0_ACC_CNTL_5_BASE_HI		0x1e54
-#define	GT64260_PCI_0_ACC_CNTL_5_TOP			0x1e58
-#define	GT64260_PCI_0_ACC_CNTL_6_BASE_LO		0x1e60
-#define	GT64260_PCI_0_ACC_CNTL_6_BASE_HI		0x1e64
-#define	GT64260_PCI_0_ACC_CNTL_6_TOP			0x1e68
-#define	GT64260_PCI_0_ACC_CNTL_7_BASE_LO		0x1e70
-#define	GT64260_PCI_0_ACC_CNTL_7_BASE_HI		0x1e74
-#define	GT64260_PCI_0_ACC_CNTL_7_TOP			0x1e78
-
-#define	GT64260_PCI_1_ACC_CNTL_0_BASE_LO		0x1e80
-#define	GT64260_PCI_1_ACC_CNTL_0_BASE_HI		0x1e84
-#define	GT64260_PCI_1_ACC_CNTL_0_TOP			0x1e88
-#define	GT64260_PCI_1_ACC_CNTL_1_BASE_LO		0x1e90
-#define	GT64260_PCI_1_ACC_CNTL_1_BASE_HI		0x1e94
-#define	GT64260_PCI_1_ACC_CNTL_1_TOP			0x1e98
-#define	GT64260_PCI_1_ACC_CNTL_2_BASE_LO		0x1ea0
-#define	GT64260_PCI_1_ACC_CNTL_2_BASE_HI		0x1ea4
-#define	GT64260_PCI_1_ACC_CNTL_2_TOP			0x1ea8
-#define	GT64260_PCI_1_ACC_CNTL_3_BASE_LO		0x1eb0
-#define	GT64260_PCI_1_ACC_CNTL_3_BASE_HI		0x1eb4
-#define	GT64260_PCI_1_ACC_CNTL_3_TOP			0x1eb8
-#define	GT64260_PCI_1_ACC_CNTL_4_BASE_LO		0x1ec0
-#define	GT64260_PCI_1_ACC_CNTL_4_BASE_HI		0x1ec4
-#define	GT64260_PCI_1_ACC_CNTL_4_TOP			0x1ec8
-#define	GT64260_PCI_1_ACC_CNTL_5_BASE_LO		0x1ed0
-#define	GT64260_PCI_1_ACC_CNTL_5_BASE_HI		0x1ed4
-#define	GT64260_PCI_1_ACC_CNTL_5_TOP			0x1ed8
-#define	GT64260_PCI_1_ACC_CNTL_6_BASE_LO		0x1ee0
-#define	GT64260_PCI_1_ACC_CNTL_6_BASE_HI		0x1ee4
-#define	GT64260_PCI_1_ACC_CNTL_6_TOP			0x1ee8
-#define	GT64260_PCI_1_ACC_CNTL_7_BASE_LO		0x1ef0
-#define	GT64260_PCI_1_ACC_CNTL_7_BASE_HI		0x1ef4
-#define	GT64260_PCI_1_ACC_CNTL_7_TOP			0x1ef8
-
-/* PCI Snoop Control Registers */
-#define	GT64260_PCI_SNOOP_WINDOWS			4
-
-#define	GT64260_PCI_SNOOP_NONE				0x00000000
-#define	GT64260_PCI_SNOOP_WT				0x00001000
-#define	GT64260_PCI_SNOOP_WB				0x00002000
-
-#define	GT64260_PCI_0_SNOOP_0_BASE_LO			0x1f00
-#define	GT64260_PCI_0_SNOOP_0_BASE_HI			0x1f04
-#define	GT64260_PCI_0_SNOOP_0_TOP			0x1f08
-#define	GT64260_PCI_0_SNOOP_1_BASE_LO			0x1f10
-#define	GT64260_PCI_0_SNOOP_1_BASE_HI			0x1f14
-#define	GT64260_PCI_0_SNOOP_1_TOP			0x1f18
-#define	GT64260_PCI_0_SNOOP_2_BASE_LO			0x1f20
-#define	GT64260_PCI_0_SNOOP_2_BASE_HI			0x1f24
-#define	GT64260_PCI_0_SNOOP_2_TOP			0x1f28
-#define	GT64260_PCI_0_SNOOP_3_BASE_LO			0x1f30
-#define	GT64260_PCI_0_SNOOP_3_BASE_HI			0x1f34
-#define	GT64260_PCI_0_SNOOP_3_TOP			0x1f38
-
-#define	GT64260_PCI_1_SNOOP_0_BASE_LO			0x1f80
-#define	GT64260_PCI_1_SNOOP_0_BASE_HI			0x1f84
-#define	GT64260_PCI_1_SNOOP_0_TOP			0x1f88
-#define	GT64260_PCI_1_SNOOP_1_BASE_LO			0x1f90
-#define	GT64260_PCI_1_SNOOP_1_BASE_HI			0x1f94
-#define	GT64260_PCI_1_SNOOP_1_TOP			0x1f98
-#define	GT64260_PCI_1_SNOOP_2_BASE_LO			0x1fa0
-#define	GT64260_PCI_1_SNOOP_2_BASE_HI			0x1fa4
-#define	GT64260_PCI_1_SNOOP_2_TOP			0x1fa8
-#define	GT64260_PCI_1_SNOOP_3_BASE_LO			0x1fb0
-#define	GT64260_PCI_1_SNOOP_3_BASE_HI			0x1fb4
-#define	GT64260_PCI_1_SNOOP_3_TOP			0x1fb8
-
-/* PCI Error Report Registers */
-#define GT64260_PCI_0_ERR_SERR_MASK			0x0c28
-#define GT64260_PCI_0_ERR_ADDR_LO			0x1d40
-#define GT64260_PCI_0_ERR_ADDR_HI			0x1d44
-#define GT64260_PCI_0_ERR_DATA_LO			0x1d48
-#define GT64260_PCI_0_ERR_DATA_HI			0x1d4c
-#define GT64260_PCI_0_ERR_CMD				0x1d50
-#define GT64260_PCI_0_ERR_CAUSE				0x1d58
-#define GT64260_PCI_0_ERR_MASK				0x1d5c
-
-#define GT64260_PCI_1_ERR_SERR_MASK			0x0ca8
-#define GT64260_PCI_1_ERR_ADDR_LO			0x1dc0
-#define GT64260_PCI_1_ERR_ADDR_HI			0x1dc4
-#define GT64260_PCI_1_ERR_DATA_LO			0x1dc8
-#define GT64260_PCI_1_ERR_DATA_HI			0x1dcc
-#define GT64260_PCI_1_ERR_CMD				0x1dd0
-#define GT64260_PCI_1_ERR_CAUSE				0x1dd8
-#define GT64260_PCI_1_ERR_MASK				0x1ddc
-
-/* PCI Slave Address Decoding Registers */
-#define	GT64260_PCI_SCS_WINDOWS				4
-#define	GT64260_PCI_CS_WINDOWS				4
-#define	GT64260_PCI_BOOT_WINDOWS			1
-#define	GT64260_PCI_P2P_MEM_WINDOWS			2
-#define	GT64260_PCI_P2P_IO_WINDOWS			1
-#define	GT64260_PCI_DAC_SCS_WINDOWS			4
-#define	GT64260_PCI_DAC_CS_WINDOWS			4
-#define	GT64260_PCI_DAC_BOOT_WINDOWS			1
-#define	GT64260_PCI_DAC_P2P_MEM_WINDOWS			2
-
-#define	GT64260_PCI_0_SLAVE_SCS_0_SIZE			0x0c08
-#define	GT64260_PCI_0_SLAVE_SCS_1_SIZE			0x0d08
-#define	GT64260_PCI_0_SLAVE_SCS_2_SIZE			0x0c0c
-#define	GT64260_PCI_0_SLAVE_SCS_3_SIZE			0x0d0c
-#define	GT64260_PCI_0_SLAVE_CS_0_SIZE			0x0c10
-#define	GT64260_PCI_0_SLAVE_CS_1_SIZE			0x0d10
-#define	GT64260_PCI_0_SLAVE_CS_2_SIZE			0x0d18
-#define	GT64260_PCI_0_SLAVE_CS_3_SIZE			0x0c14
-#define	GT64260_PCI_0_SLAVE_BOOT_SIZE			0x0d14
-#define	GT64260_PCI_0_SLAVE_P2P_MEM_0_SIZE		0x0d1c
-#define	GT64260_PCI_0_SLAVE_P2P_MEM_1_SIZE		0x0d20
-#define	GT64260_PCI_0_SLAVE_P2P_IO_SIZE			0x0d24
-#define	GT64260_PCI_0_SLAVE_CPU_SIZE			0x0d28
-
-#define	GT64260_PCI_0_SLAVE_DAC_SCS_0_SIZE		0x0e00
-#define	GT64260_PCI_0_SLAVE_DAC_SCS_1_SIZE		0x0e04
-#define	GT64260_PCI_0_SLAVE_DAC_SCS_2_SIZE		0x0e08
-#define	GT64260_PCI_0_SLAVE_DAC_SCS_3_SIZE		0x0e0c
-#define	GT64260_PCI_0_SLAVE_DAC_CS_0_SIZE		0x0e10
-#define	GT64260_PCI_0_SLAVE_DAC_CS_1_SIZE		0x0e14
-#define	GT64260_PCI_0_SLAVE_DAC_CS_2_SIZE		0x0e18
-#define	GT64260_PCI_0_SLAVE_DAC_CS_3_SIZE		0x0e1c
-#define	GT64260_PCI_0_SLAVE_DAC_BOOT_SIZE		0x0e20
-#define	GT64260_PCI_0_SLAVE_DAC_P2P_MEM_0_SIZE		0x0e24
-#define	GT64260_PCI_0_SLAVE_DAC_P2P_MEM_1_SIZE		0x0e28
-#define	GT64260_PCI_0_SLAVE_DAC_CPU_SIZE		0x0e2c
-
-#define	GT64260_PCI_0_SLAVE_EXP_ROM_SIZE		0x0d2c
-
-#define	GT64260_PCI_SLAVE_BAR_REG_ENABLES_SCS_0		(1<<0)
-#define	GT64260_PCI_SLAVE_BAR_REG_ENABLES_SCS_1		(1<<1)
-#define	GT64260_PCI_SLAVE_BAR_REG_ENABLES_SCS_2		(1<<2)
-#define	GT64260_PCI_SLAVE_BAR_REG_ENABLES_SCS_3		(1<<3)
-#define	GT64260_PCI_SLAVE_BAR_REG_ENABLES_CS_0		(1<<4)
-#define	GT64260_PCI_SLAVE_BAR_REG_ENABLES_CS_1		(1<<5)
-#define	GT64260_PCI_SLAVE_BAR_REG_ENABLES_CS_2		(1<<6)
-#define	GT64260_PCI_SLAVE_BAR_REG_ENABLES_CS_3		(1<<7)
-#define	GT64260_PCI_SLAVE_BAR_REG_ENABLES_BOOT		(1<<8)
-#define	GT64260_PCI_SLAVE_BAR_REG_ENABLES_REG_MEM	(1<<9)
-#define	GT64260_PCI_SLAVE_BAR_REG_ENABLES_REG_IO	(1<<10)
-#define	GT64260_PCI_SLAVE_BAR_REG_ENABLES_P2P_MEM_0	(1<<11)
-#define	GT64260_PCI_SLAVE_BAR_REG_ENABLES_P2P_MEM_1	(1<<12)
-#define	GT64260_PCI_SLAVE_BAR_REG_ENABLES_P2P_IO	(1<<13)
-#define	GT64260_PCI_SLAVE_BAR_REG_ENABLES_CPU		(1<<14)
-#define	GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_SCS_0	(1<<15)
-#define	GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_SCS_1	(1<<16)
-#define	GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_SCS_2	(1<<17)
-#define	GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_SCS_3	(1<<18)
-#define	GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_CS_0	(1<<19)
-#define	GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_CS_1	(1<<20)
-#define	GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_CS_2	(1<<21)
-#define	GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_CS_3	(1<<22)
-#define	GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_BOOT	(1<<23)
-#define	GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_P2P_MEM_0	(1<<24)
-#define	GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_P2P_MEM_1	(1<<25)
-#define	GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_CPU	(1<<26)
-
-#define	GT64260_PCI_0_SLAVE_BAR_REG_ENABLES		0x0c3c
-#define	GT64260_PCI_0_SLAVE_SCS_0_REMAP			0x0c48
-#define	GT64260_PCI_0_SLAVE_SCS_1_REMAP			0x0d48
-#define	GT64260_PCI_0_SLAVE_SCS_2_REMAP			0x0c4c
-#define	GT64260_PCI_0_SLAVE_SCS_3_REMAP			0x0d4c
-#define	GT64260_PCI_0_SLAVE_CS_0_REMAP			0x0c50
-#define	GT64260_PCI_0_SLAVE_CS_1_REMAP			0x0d50
-#define	GT64260_PCI_0_SLAVE_CS_2_REMAP			0x0d58
-#define	GT64260_PCI_0_SLAVE_CS_3_REMAP			0x0c54
-#define	GT64260_PCI_0_SLAVE_BOOT_REMAP			0x0d54
-#define	GT64260_PCI_0_SLAVE_P2P_MEM_0_REMAP_LO		0x0d5c
-#define	GT64260_PCI_0_SLAVE_P2P_MEM_0_REMAP_HI		0x0d60
-#define	GT64260_PCI_0_SLAVE_P2P_MEM_1_REMAP_LO		0x0d64
-#define	GT64260_PCI_0_SLAVE_P2P_MEM_1_REMAP_HI		0x0d68
-#define	GT64260_PCI_0_SLAVE_P2P_IO_REMAP		0x0d6c
-#define	GT64260_PCI_0_SLAVE_CPU_REMAP			0x0d70
-
-#define	GT64260_PCI_0_SLAVE_DAC_SCS_0_REMAP		0x0f00
-#define	GT64260_PCI_0_SLAVE_DAC_SCS_1_REMAP		0x0f04
-#define	GT64260_PCI_0_SLAVE_DAC_SCS_2_REMAP		0x0f08
-#define	GT64260_PCI_0_SLAVE_DAC_SCS_3_REMAP		0x0f0c
-#define	GT64260_PCI_0_SLAVE_DAC_CS_0_REMAP		0x0f10
-#define	GT64260_PCI_0_SLAVE_DAC_CS_1_REMAP		0x0f14
-#define	GT64260_PCI_0_SLAVE_DAC_CS_2_REMAP		0x0f18
-#define	GT64260_PCI_0_SLAVE_DAC_CS_3_REMAP		0x0f1c
-#define	GT64260_PCI_0_SLAVE_DAC_BOOT_REMAP		0x0f20
-#define	GT64260_PCI_0_SLAVE_DAC_P2P_MEM_0_REMAP_LO	0x0f24
-#define	GT64260_PCI_0_SLAVE_DAC_P2P_MEM_0_REMAP_HI	0x0f28
-#define	GT64260_PCI_0_SLAVE_DAC_P2P_MEM_1_REMAP_LO	0x0f2c
-#define	GT64260_PCI_0_SLAVE_DAC_P2P_MEM_1_REMAP_HI	0x0f30
-#define	GT64260_PCI_0_SLAVE_DAC_CPU_REMAP		0x0f34
-
-#define	GT64260_PCI_0_SLAVE_EXP_ROM_REMAP		0x0f38
-#define	GT64260_PCI_0_SLAVE_PCI_DECODE_CNTL		0x0d3c
-
-#define	GT64260_PCI_1_SLAVE_SCS_0_SIZE			0x0c88
-#define	GT64260_PCI_1_SLAVE_SCS_1_SIZE			0x0d88
-#define	GT64260_PCI_1_SLAVE_SCS_2_SIZE			0x0c8c
-#define	GT64260_PCI_1_SLAVE_SCS_3_SIZE			0x0d8c
-#define	GT64260_PCI_1_SLAVE_CS_0_SIZE			0x0c90
-#define	GT64260_PCI_1_SLAVE_CS_1_SIZE			0x0d90
-#define	GT64260_PCI_1_SLAVE_CS_2_SIZE			0x0d98
-#define	GT64260_PCI_1_SLAVE_CS_3_SIZE			0x0c94
-#define	GT64260_PCI_1_SLAVE_BOOT_SIZE			0x0d94
-#define	GT64260_PCI_1_SLAVE_P2P_MEM_0_SIZE		0x0d9c
-#define	GT64260_PCI_1_SLAVE_P2P_MEM_1_SIZE		0x0da0
-#define	GT64260_PCI_1_SLAVE_P2P_IO_SIZE			0x0da4
-#define	GT64260_PCI_1_SLAVE_CPU_SIZE			0x0da8
-
-#define	GT64260_PCI_1_SLAVE_DAC_SCS_0_SIZE		0x0e80
-#define	GT64260_PCI_1_SLAVE_DAC_SCS_1_SIZE		0x0e84
-#define	GT64260_PCI_1_SLAVE_DAC_SCS_2_SIZE		0x0e88
-#define	GT64260_PCI_1_SLAVE_DAC_SCS_3_SIZE		0x0e8c
-#define	GT64260_PCI_1_SLAVE_DAC_CS_0_SIZE		0x0e90
-#define	GT64260_PCI_1_SLAVE_DAC_CS_1_SIZE		0x0e94
-#define	GT64260_PCI_1_SLAVE_DAC_CS_2_SIZE		0x0e98
-#define	GT64260_PCI_1_SLAVE_DAC_CS_3_SIZE		0x0e9c
-#define	GT64260_PCI_1_SLAVE_DAC_BOOT_SIZE		0x0ea0
-#define	GT64260_PCI_1_SLAVE_DAC_P2P_MEM_0_SIZE		0x0ea4
-#define	GT64260_PCI_1_SLAVE_DAC_P2P_MEM_1_SIZE		0x0ea8
-#define	GT64260_PCI_1_SLAVE_DAC_CPU_SIZE		0x0eac
-
-#define	GT64260_PCI_1_SLAVE_EXP_ROM_SIZE		0x0dac
-
-#define	GT64260_PCI_1_SLAVE_BAR_REG_ENABLES		0x0cbc
-#define	GT64260_PCI_1_SLAVE_SCS_0_REMAP			0x0cc8
-#define	GT64260_PCI_1_SLAVE_SCS_1_REMAP			0x0dc8
-#define	GT64260_PCI_1_SLAVE_SCS_2_REMAP			0x0ccc
-#define	GT64260_PCI_1_SLAVE_SCS_3_REMAP			0x0dcc
-#define	GT64260_PCI_1_SLAVE_CS_0_REMAP			0x0cd0
-#define	GT64260_PCI_1_SLAVE_CS_1_REMAP			0x0dd0
-#define	GT64260_PCI_1_SLAVE_CS_2_REMAP			0x0dd8
-#define	GT64260_PCI_1_SLAVE_CS_3_REMAP			0x0cd4
-#define	GT64260_PCI_1_SLAVE_BOOT_REMAP			0x0dd4
-#define	GT64260_PCI_1_SLAVE_P2P_MEM_0_REMAP_LO		0x0ddc
-#define	GT64260_PCI_1_SLAVE_P2P_MEM_0_REMAP_HI		0x0de0
-#define	GT64260_PCI_1_SLAVE_P2P_MEM_1_REMAP_LO		0x0de4
-#define	GT64260_PCI_1_SLAVE_P2P_MEM_1_REMAP_HI		0x0de8
-#define	GT64260_PCI_1_SLAVE_P2P_IO_REMAP		0x0dec
-#define	GT64260_PCI_1_SLAVE_CPU_REMAP			0x0df0
-
-#define	GT64260_PCI_1_SLAVE_DAC_SCS_0_REMAP		0x0f80
-#define	GT64260_PCI_1_SLAVE_DAC_SCS_1_REMAP		0x0f84
-#define	GT64260_PCI_1_SLAVE_DAC_SCS_2_REMAP		0x0f88
-#define	GT64260_PCI_1_SLAVE_DAC_SCS_3_REMAP		0x0f8c
-#define	GT64260_PCI_1_SLAVE_DAC_CS_0_REMAP		0x0f90
-#define	GT64260_PCI_1_SLAVE_DAC_CS_1_REMAP		0x0f94
-#define	GT64260_PCI_1_SLAVE_DAC_CS_2_REMAP		0x0f98
-#define	GT64260_PCI_1_SLAVE_DAC_CS_3_REMAP		0x0f9c
-#define	GT64260_PCI_1_SLAVE_DAC_BOOT_REMAP		0x0fa0
-#define	GT64260_PCI_1_SLAVE_DAC_P2P_MEM_0_REMAP_LO	0x0fa4
-#define	GT64260_PCI_1_SLAVE_DAC_P2P_MEM_0_REMAP_HI	0x0fa8
-#define	GT64260_PCI_1_SLAVE_DAC_P2P_MEM_1_REMAP_LO	0x0fac
-#define	GT64260_PCI_1_SLAVE_DAC_P2P_MEM_1_REMAP_HI	0x0fb0
-#define	GT64260_PCI_1_SLAVE_DAC_CPU_REMAP		0x0fb4
-
-#define	GT64260_PCI_1_SLAVE_EXP_ROM_REMAP		0x0fb8
-#define	GT64260_PCI_1_SLAVE_PCI_DECODE_CNTL		0x0dbc
-
-
-/*
- *****************************************************************************
- *
- *	I2O Controller Interface Registers
- *
- *****************************************************************************
- */
-
-/* FIXME: fill in */
-
-
-
-/*
- *****************************************************************************
- *
- *	DMA Controller Interface Registers
- *
- *****************************************************************************
- */
-
-/* FIXME: fill in */
-
-
-/*
- *****************************************************************************
- *
- *	Timer/Counter Interface Registers
- *
- *****************************************************************************
- */
-
-/* FIXME: fill in */
-
-
-/*
- *****************************************************************************
- *
- *	Communications Controller (Enet, Serial, etc.) Interface Registers
- *
- *****************************************************************************
- */
-
-#define	GT64260_ENET_0_CNTL_LO				0xf200
-#define	GT64260_ENET_0_CNTL_HI				0xf204
-#define	GT64260_ENET_0_RX_BUF_PCI_ADDR_HI		0xf208
-#define	GT64260_ENET_0_TX_BUF_PCI_ADDR_HI		0xf20c
-#define	GT64260_ENET_0_RX_DESC_ADDR_HI			0xf210
-#define	GT64260_ENET_0_TX_DESC_ADDR_HI			0xf214
-#define	GT64260_ENET_0_HASH_TAB_PCI_ADDR_HI		0xf218
-#define	GT64260_ENET_1_CNTL_LO				0xf220
-#define	GT64260_ENET_1_CNTL_HI				0xf224
-#define	GT64260_ENET_1_RX_BUF_PCI_ADDR_HI		0xf228
-#define	GT64260_ENET_1_TX_BUF_PCI_ADDR_HI		0xf22c
-#define	GT64260_ENET_1_RX_DESC_ADDR_HI			0xf230
-#define	GT64260_ENET_1_TX_DESC_ADDR_HI			0xf234
-#define	GT64260_ENET_1_HASH_TAB_PCI_ADDR_HI		0xf238
-#define	GT64260_ENET_2_CNTL_LO				0xf240
-#define	GT64260_ENET_2_CNTL_HI				0xf244
-#define	GT64260_ENET_2_RX_BUF_PCI_ADDR_HI		0xf248
-#define	GT64260_ENET_2_TX_BUF_PCI_ADDR_HI		0xf24c
-#define	GT64260_ENET_2_RX_DESC_ADDR_HI			0xf250
-#define	GT64260_ENET_2_TX_DESC_ADDR_HI			0xf254
-#define	GT64260_ENET_2_HASH_TAB_PCI_ADDR_HI		0xf258
-
-#define	GT64260_MPSC_0_CNTL_LO				0xf280
-#define	GT64260_MPSC_0_CNTL_HI				0xf284
-#define	GT64260_MPSC_0_RX_BUF_PCI_ADDR_HI		0xf288
-#define	GT64260_MPSC_0_TX_BUF_PCI_ADDR_HI		0xf28c
-#define	GT64260_MPSC_0_RX_DESC_ADDR_HI			0xf290
-#define	GT64260_MPSC_0_TX_DESC_ADDR_HI			0xf294
-#define	GT64260_MPSC_1_CNTL_LO				0xf2c0
-#define	GT64260_MPSC_1_CNTL_HI				0xf2c4
-#define	GT64260_MPSC_1_RX_BUF_PCI_ADDR_HI		0xf2c8
-#define	GT64260_MPSC_1_TX_BUF_PCI_ADDR_HI		0xf2cc
-#define	GT64260_MPSC_1_RX_DESC_ADDR_HI			0xf2d0
-#define	GT64260_MPSC_1_TX_DESC_ADDR_HI			0xf2d4
-
-#define	GT64260_SER_INIT_PCI_ADDR_HI			0xf320
-#define	GT64260_SER_INIT_LAST_DATA			0xf324
-#define	GT64260_SER_INIT_CONTROL			0xf328
-#define	GT64260_SER_INIT_STATUS				0xf32c
-
-#define	GT64260_COMM_ARBITER_CNTL			0xf300
-#define	GT64260_COMM_CONFIG				0xb40c
-#define	GT64260_COMM_XBAR_TO				0xf304
-#define	GT64260_COMM_INTR_CAUSE				0xf310
-#define	GT64260_COMM_INTR_MASK				0xf314
-#define	GT64260_COMM_ERR_ADDR				0xf318
-
-
-/*
- *****************************************************************************
- *
- *	Fast Ethernet Controller Interface Registers
- *
- *****************************************************************************
- */
-
-#define	GT64260_ENET_PHY_ADDR				0x2000
-#define	GT64260_ENET_ESMIR				0x2010
-
-#define	GT64260_ENET_E0PCR				0x2400
-#define	GT64260_ENET_E0PCXR				0x2408
-#define	GT64260_ENET_E0PCMR				0x2410
-#define	GT64260_ENET_E0PSR				0x2418
-#define	GT64260_ENET_E0SPR				0x2420
-#define	GT64260_ENET_E0HTPR				0x2428
-#define	GT64260_ENET_E0FCSAL				0x2430
-#define	GT64260_ENET_E0FCSAH				0x2438
-#define	GT64260_ENET_E0SDCR				0x2440
-#define	GT64260_ENET_E0SDCMR				0x2448
-#define	GT64260_ENET_E0ICR				0x2450
-#define	GT64260_ENET_E0IMR				0x2458
-#define	GT64260_ENET_E0FRDP0				0x2480
-#define	GT64260_ENET_E0FRDP1				0x2484
-#define	GT64260_ENET_E0FRDP2				0x2488
-#define	GT64260_ENET_E0FRDP3				0x248c
-#define	GT64260_ENET_E0CRDP0				0x24a0
-#define	GT64260_ENET_E0CRDP1				0x24a4
-#define	GT64260_ENET_E0CRDP2				0x24a8
-#define	GT64260_ENET_E0CRDP3				0x24ac
-#define	GT64260_ENET_E0CTDP0				0x24e0
-#define	GT64260_ENET_E0CTDP1				0x24e4
-#define	GT64260_ENET_0_DSCP2P0L				0x2460
-#define	GT64260_ENET_0_DSCP2P0H				0x2464
-#define	GT64260_ENET_0_DSCP2P1L				0x2468
-#define	GT64260_ENET_0_DSCP2P1H				0x246c
-#define	GT64260_ENET_0_VPT2P				0x2470
-#define	GT64260_ENET_0_MIB_CTRS				0x2500
-
-#define	GT64260_ENET_E1PCR				0x2800
-#define	GT64260_ENET_E1PCXR				0x2808
-#define	GT64260_ENET_E1PCMR				0x2810
-#define	GT64260_ENET_E1PSR				0x2818
-#define	GT64260_ENET_E1SPR				0x2820
-#define	GT64260_ENET_E1HTPR				0x2828
-#define	GT64260_ENET_E1FCSAL				0x2830
-#define	GT64260_ENET_E1FCSAH				0x2838
-#define	GT64260_ENET_E1SDCR				0x2840
-#define	GT64260_ENET_E1SDCMR				0x2848
-#define	GT64260_ENET_E1ICR				0x2850
-#define	GT64260_ENET_E1IMR				0x2858
-#define	GT64260_ENET_E1FRDP0				0x2880
-#define	GT64260_ENET_E1FRDP1				0x2884
-#define	GT64260_ENET_E1FRDP2				0x2888
-#define	GT64260_ENET_E1FRDP3				0x288c
-#define	GT64260_ENET_E1CRDP0				0x28a0
-#define	GT64260_ENET_E1CRDP1				0x28a4
-#define	GT64260_ENET_E1CRDP2				0x28a8
-#define	GT64260_ENET_E1CRDP3				0x28ac
-#define	GT64260_ENET_E1CTDP0				0x28e0
-#define	GT64260_ENET_E1CTDP1				0x28e4
-#define	GT64260_ENET_1_DSCP2P0L				0x2860
-#define	GT64260_ENET_1_DSCP2P0H				0x2864
-#define	GT64260_ENET_1_DSCP2P1L				0x2868
-#define	GT64260_ENET_1_DSCP2P1H				0x286c
-#define	GT64260_ENET_1_VPT2P				0x2870
-#define	GT64260_ENET_1_MIB_CTRS				0x2900
-
-#define	GT64260_ENET_E2PCR				0x2c00
-#define	GT64260_ENET_E2PCXR				0x2c08
-#define	GT64260_ENET_E2PCMR				0x2c10
-#define	GT64260_ENET_E2PSR				0x2c18
-#define	GT64260_ENET_E2SPR				0x2c20
-#define	GT64260_ENET_E2HTPR				0x2c28
-#define	GT64260_ENET_E2FCSAL				0x2c30
-#define	GT64260_ENET_E2FCSAH				0x2c38
-#define	GT64260_ENET_E2SDCR				0x2c40
-#define	GT64260_ENET_E2SDCMR				0x2c48
-#define	GT64260_ENET_E2ICR				0x2c50
-#define	GT64260_ENET_E2IMR				0x2c58
-#define	GT64260_ENET_E2FRDP0				0x2c80
-#define	GT64260_ENET_E2FRDP1				0x2c84
-#define	GT64260_ENET_E2FRDP2				0x2c88
-#define	GT64260_ENET_E2FRDP3				0x2c8c
-#define	GT64260_ENET_E2CRDP0				0x2ca0
-#define	GT64260_ENET_E2CRDP1				0x2ca4
-#define	GT64260_ENET_E2CRDP2				0x2ca8
-#define	GT64260_ENET_E2CRDP3				0x2cac
-#define	GT64260_ENET_E2CTDP0				0x2ce0
-#define	GT64260_ENET_E2CTDP1				0x2ce4
-#define	GT64260_ENET_2_DSCP2P0L				0x2c60
-#define	GT64260_ENET_2_DSCP2P0H				0x2c64
-#define	GT64260_ENET_2_DSCP2P1L				0x2c68
-#define	GT64260_ENET_2_DSCP2P1H				0x2c6c
-#define	GT64260_ENET_2_VPT2P				0x2c70
-#define	GT64260_ENET_2_MIB_CTRS				0x2d00
-
-
-/*
- *****************************************************************************
- *
- *	Multi-Protocol Serial Controller Interface Registers
- *
- *****************************************************************************
- */
-
-/* Signal Routing */
-#define	GT64260_MPSC_MRR				0xb400
-#define	GT64260_MPSC_RCRR				0xb404
-#define	GT64260_MPSC_TCRR				0xb408
-
-/* Main Configuratino Registers */
-#define	GT64260_MPSC_0_MMCRL				0x8000
-#define	GT64260_MPSC_0_MMCRH				0x8004
-#define	GT64260_MPSC_0_MPCR				0x8008
-#define	GT64260_MPSC_0_CHR_1				0x800c
-#define	GT64260_MPSC_0_CHR_2				0x8010
-#define	GT64260_MPSC_0_CHR_3				0x8014
-#define	GT64260_MPSC_0_CHR_4				0x8018
-#define	GT64260_MPSC_0_CHR_5				0x801c
-#define	GT64260_MPSC_0_CHR_6				0x8020
-#define	GT64260_MPSC_0_CHR_7				0x8024
-#define	GT64260_MPSC_0_CHR_8				0x8028
-#define	GT64260_MPSC_0_CHR_9				0x802c
-#define	GT64260_MPSC_0_CHR_10				0x8030
-#define	GT64260_MPSC_0_CHR_11				0x8034
-
-#define	GT64260_MPSC_1_MMCRL				0x9000
-#define	GT64260_MPSC_1_MMCRH				0x9004
-#define	GT64260_MPSC_1_MPCR				0x9008
-#define	GT64260_MPSC_1_CHR_1				0x900c
-#define	GT64260_MPSC_1_CHR_2				0x9010
-#define	GT64260_MPSC_1_CHR_3				0x9014
-#define	GT64260_MPSC_1_CHR_4				0x9018
-#define	GT64260_MPSC_1_CHR_5				0x901c
-#define	GT64260_MPSC_1_CHR_6				0x9020
-#define	GT64260_MPSC_1_CHR_7				0x9024
-#define	GT64260_MPSC_1_CHR_8				0x9028
-#define	GT64260_MPSC_1_CHR_9				0x902c
-#define	GT64260_MPSC_1_CHR_10				0x9030
-#define	GT64260_MPSC_1_CHR_11				0x9034
-
-#define	GT64260_MPSC_0_INTR_CAUSE			0xb804
-#define	GT64260_MPSC_0_INTR_MASK			0xb884
-#define	GT64260_MPSC_1_INTR_CAUSE			0xb80c
-#define	GT64260_MPSC_1_INTR_MASK			0xb88c
-
-#define	GT64260_MPSC_UART_CR_TEV			(1<<1)
-#define	GT64260_MPSC_UART_CR_TA				(1<<7)
-#define	GT64260_MPSC_UART_CR_TTCS			(1<<9)
-#define	GT64260_MPSC_UART_CR_REV			(1<<17)
-#define	GT64260_MPSC_UART_CR_RA				(1<<23)
-#define	GT64260_MPSC_UART_CR_CRD			(1<<25)
-#define	GT64260_MPSC_UART_CR_EH				(1<<31)
-
-#define	GT64260_MPSC_UART_ESR_CTS			(1<<0)
-#define	GT64260_MPSC_UART_ESR_CD			(1<<1)
-#define	GT64260_MPSC_UART_ESR_TIDLE			(1<<3)
-#define	GT64260_MPSC_UART_ESR_RHS			(1<<5)
-#define	GT64260_MPSC_UART_ESR_RLS			(1<<7)
-#define	GT64260_MPSC_UART_ESR_RLIDL			(1<<11)
-
-
-/*
- *****************************************************************************
- *
- *	Serial DMA Controller Interface Registers
- *
- *****************************************************************************
- */
-
-#define	GT64260_SDMA_0_SDC				0x4000
-#define	GT64260_SDMA_0_SDCM				0x4008
-#define	GT64260_SDMA_0_RX_DESC				0x4800
-#define	GT64260_SDMA_0_RX_BUF_PTR			0x4808
-#define	GT64260_SDMA_0_SCRDP				0x4810
-#define	GT64260_SDMA_0_TX_DESC				0x4c00
-#define	GT64260_SDMA_0_SCTDP				0x4c10
-#define	GT64260_SDMA_0_SFTDP				0x4c14
-
-#define	GT64260_SDMA_1_SDC				0x6000
-#define	GT64260_SDMA_1_SDCM				0x6008
-#define	GT64260_SDMA_1_RX_DESC				0x6800
-#define GT64260_SDMA_1_RX_BUF_PTR                       0x6808
-#define	GT64260_SDMA_1_SCRDP				0x6810
-#define	GT64260_SDMA_1_TX_DESC				0x6c00
-#define	GT64260_SDMA_1_SCTDP				0x6c10
-#define	GT64260_SDMA_1_SFTDP				0x6c14
-
-#define	GT64260_SDMA_INTR_CAUSE				0xb800
-#define	GT64260_SDMA_INTR_MASK				0xb880
-
-#define	GT64260_SDMA_DESC_CMDSTAT_PE			(1<<0)
-#define	GT64260_SDMA_DESC_CMDSTAT_CDL			(1<<1)
-#define	GT64260_SDMA_DESC_CMDSTAT_FR			(1<<3)
-#define	GT64260_SDMA_DESC_CMDSTAT_OR			(1<<6)
-#define	GT64260_SDMA_DESC_CMDSTAT_BR			(1<<9)
-#define	GT64260_SDMA_DESC_CMDSTAT_MI			(1<<10)
-#define	GT64260_SDMA_DESC_CMDSTAT_A			(1<<11)
-#define	GT64260_SDMA_DESC_CMDSTAT_AM			(1<<12)
-#define	GT64260_SDMA_DESC_CMDSTAT_CT			(1<<13)
-#define	GT64260_SDMA_DESC_CMDSTAT_C			(1<<14)
-#define	GT64260_SDMA_DESC_CMDSTAT_ES			(1<<15)
-#define	GT64260_SDMA_DESC_CMDSTAT_L			(1<<16)
-#define	GT64260_SDMA_DESC_CMDSTAT_F			(1<<17)
-#define	GT64260_SDMA_DESC_CMDSTAT_P			(1<<18)
-#define	GT64260_SDMA_DESC_CMDSTAT_EI			(1<<23)
-#define	GT64260_SDMA_DESC_CMDSTAT_O			(1<<31)
-
-#define	GT64260_SDMA_SDC_RFT				(1<<0)
-#define	GT64260_SDMA_SDC_SFM				(1<<1)
-#define	GT64260_SDMA_SDC_BLMR				(1<<6)
-#define	GT64260_SDMA_SDC_BLMT				(1<<7)
-#define	GT64260_SDMA_SDC_POVR				(1<<8)
-#define	GT64260_SDMA_SDC_RIFB				(1<<9)
-
-#define	GT64260_SDMA_SDCM_ERD				(1<<7)
-#define	GT64260_SDMA_SDCM_AR				(1<<15)
-#define	GT64260_SDMA_SDCM_STD				(1<<16)
-#define	GT64260_SDMA_SDCM_TXD				(1<<23)
-#define	GT64260_SDMA_SDCM_AT				(1<<31)
-
-#define	GT64260_SDMA_0_CAUSE_RXBUF			(1<<0)
-#define	GT64260_SDMA_0_CAUSE_RXERR			(1<<1)
-#define	GT64260_SDMA_0_CAUSE_TXBUF			(1<<2)
-#define	GT64260_SDMA_0_CAUSE_TXEND			(1<<3)
-#define	GT64260_SDMA_1_CAUSE_RXBUF			(1<<8)
-#define	GT64260_SDMA_1_CAUSE_RXERR			(1<<9)
-#define	GT64260_SDMA_1_CAUSE_TXBUF			(1<<10)
-#define	GT64260_SDMA_1_CAUSE_TXEND			(1<<11)
-
-
-/*
- *****************************************************************************
- *
- *	Baud Rate Generator Interface Registers
- *
- *****************************************************************************
- */
-
-#define	GT64260_BRG_0_BCR				0xb200
-#define	GT64260_BRG_0_BTR				0xb204
-#define	GT64260_BRG_1_BCR				0xb208
-#define	GT64260_BRG_1_BTR				0xb20c
-#define	GT64260_BRG_2_BCR				0xb210
-#define	GT64260_BRG_2_BTR				0xb214
-
-#define	GT64260_BRG_INTR_CAUSE				0xb834
-#define	GT64260_BRG_INTR_MASK				0xb8b4
-
-
-/*
- *****************************************************************************
- *
- *	Watchdog Timer Interface Registers
- *
- *****************************************************************************
- */
-
-#define	GT64260_WDT_WDC					0xb410
-#define	GT64260_WDT_WDV					0xb414
-
-
-/*
- *****************************************************************************
- *
- *	 General Purpose Pins Controller Interface Registers
- *
- *****************************************************************************
- */
-
-#define	GT64260_GPP_IO_CNTL				0xf100
-#define	GT64260_GPP_LEVEL_CNTL				0xf110
-#define	GT64260_GPP_VALUE				0xf104
-#define	GT64260_GPP_INTR_CAUSE				0xf108
-#define	GT64260_GPP_INTR_MASK				0xf10c
-
-
-/*
- *****************************************************************************
- *
- *	Multi-Purpose Pins Controller Interface Registers
- *
- *****************************************************************************
- */
-
-#define	GT64260_MPP_CNTL_0				0xf000
-#define	GT64260_MPP_CNTL_1				0xf004
-#define	GT64260_MPP_CNTL_2				0xf008
-#define	GT64260_MPP_CNTL_3				0xf00c
-#define	GT64260_MPP_SERIAL_PORTS_MULTIPLEX		0xf010
-
-
-/*
- *****************************************************************************
- *
- *	I2C Controller Interface Registers
- *
- *****************************************************************************
- */
-
-/* FIXME: fill in */
-
-
-/*
- *****************************************************************************
- *
- *	Interrupt Controller Interface Registers
- *
- *****************************************************************************
- */
-
-#define	GT64260_IC_MAIN_CAUSE_LO			0x0c18
-#define	GT64260_IC_MAIN_CAUSE_HI			0x0c68
-#define	GT64260_IC_CPU_INTR_MASK_LO			0x0c1c
-#define	GT64260_IC_CPU_INTR_MASK_HI			0x0c6c
-#define	GT64260_IC_CPU_SELECT_CAUSE			0x0c70
-#define	GT64260_IC_PCI_0_INTR_MASK_LO			0x0c24
-#define	GT64260_IC_PCI_0_INTR_MASK_HI			0x0c64
-#define	GT64260_IC_PCI_0_SELECT_CAUSE			0x0c74
-#define	GT64260_IC_PCI_1_INTR_MASK_LO			0x0ca4
-#define	GT64260_IC_PCI_1_INTR_MASK_HI			0x0ce4
-#define	GT64260_IC_PCI_1_SELECT_CAUSE			0x0cf4
-#define	GT64260_IC_CPU_INT_0_MASK			0x0e60
-#define	GT64260_IC_CPU_INT_1_MASK			0x0e64
-#define	GT64260_IC_CPU_INT_2_MASK			0x0e68
-#define	GT64260_IC_CPU_INT_3_MASK			0x0e6c
-
-
-#endif /* __ASMPPC_GT64260_DEFS_H */
diff --git a/include/asm-ppc/harrier.h b/include/asm-ppc/harrier.h
deleted file mode 100644
index 7acd7fc126e..00000000000
--- a/include/asm-ppc/harrier.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * Definitions for Motorola MCG Harrier North Bridge & Memory controller
- *
- * Author: Dale Farnsworth
- *         dale.farnsworth@mvista.com
- *
- * Modified by: Randy Vinson
- * 	   rvinson@mvista.com
- *
- * Copyright 2001-2002 MontaVista Software Inc.
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-
-#ifndef __ASMPPC_HARRIER_H
-#define __ASMPPC_HARRIER_H
-
-#include <linux/types.h>
-#include <asm/pci-bridge.h>
-
-struct pci_controller;
-int harrier_init(struct pci_controller *hose,
-		 uint ppc_reg_base,
-		 ulong processor_pci_mem_start,
-		 ulong processor_pci_mem_end,
-		 ulong processor_pci_io_start,
-		 ulong processor_pci_io_end,
-		 ulong processor_mpic_base);
-
-unsigned long harrier_get_mem_size(uint smc_base);
-
-int harrier_mpic_init(unsigned int pci_mem_offset);
-
-void harrier_setup_nonmonarch(uint ppc_reg_base,
-			      uint in0_size);
-void harrier_release_eready(uint ppc_reg_base);
-
-void harrier_wait_eready(uint ppc_reg_base);
-
-#endif /* __ASMPPC_HARRIER_H */
diff --git a/include/asm-ppc/hawk.h b/include/asm-ppc/hawk.h
deleted file mode 100644
index f347007d22a..00000000000
--- a/include/asm-ppc/hawk.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * include/asm-ppc/hawk.h
- *
- * Support functions for MCG Falcon/Raven & HAWK North Bridge & Memory ctlr.
- *
- * Author: Mark A. Greer
- *         mgreer@mvista.com
- *
- * Modified by Randy Vinson (rvinson@mvista.com)
- *
- * 2001,2004 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#ifndef __ASMPPC_HAWK_H
-#define __ASMPPC_HAWK_H
-
-#include <asm/pci-bridge.h>
-#include <asm/hawk_defs.h>
-
-extern int hawk_init(struct pci_controller *hose,
-	      unsigned int ppc_reg_base, unsigned long processor_pci_mem_start,
-	      unsigned long processor_pci_mem_end,
-	      unsigned long processor_pci_io_start,
-	      unsigned long processor_pci_io_end,
-	      unsigned long processor_mpic_base);
-extern unsigned long hawk_get_mem_size(unsigned int smc_base);
-extern int hawk_mpic_init(unsigned int pci_mem_offset);
-
-#endif	/* __ASMPPC_HAWK_H */
diff --git a/include/asm-ppc/hawk_defs.h b/include/asm-ppc/hawk_defs.h
deleted file mode 100644
index 6d1d2baf648..00000000000
--- a/include/asm-ppc/hawk_defs.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * include/asm-ppc/hawk_defs.h
- *
- * Definitions for Motorola MCG Falcon/Raven & HAWK North Bridge & Memory ctlr.
- *
- * Author: Mark A. Greer
- *         mgreer@mvista.com
- *
- * Modified by Randy Vinson (rvinson@mvista.com)
- *
- * 2001-2004 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#ifndef __ASMPPC_HAWK_DEFS_H
-#define __ASMPPC_HAWK_DEFS_H
-
-#include <asm/pci-bridge.h>
-
-/*
- * The Falcon/Raven and HAWK have 4 sets of registers:
- *   1) PPC Registers which define the mappings from PPC bus to PCI bus,
- *      etc.
- *   2) PCI Registers which define the mappings from PCI bus to PPC bus and the
- *      MPIC base address.
- *   3) MPIC registers
- *   4) System Memory Controller (SMC) registers.
- */
-
-#define HAWK_PCI_CONFIG_ADDR_OFF	0x00000cf8
-#define HAWK_PCI_CONFIG_DATA_OFF	0x00000cfc
-
-#define HAWK_MPIC_SIZE			0x00040000U
-#define HAWK_SMC_SIZE			0x00001000U
-
-/*
- * Define PPC register offsets.
- */
-#define HAWK_PPC_XSADD0_OFF			0x40
-#define HAWK_PPC_XSOFF0_OFF			0x44
-#define HAWK_PPC_XSADD1_OFF			0x48
-#define HAWK_PPC_XSOFF1_OFF			0x4c
-#define HAWK_PPC_XSADD2_OFF			0x50
-#define HAWK_PPC_XSOFF2_OFF			0x54
-#define HAWK_PPC_XSADD3_OFF			0x58
-#define HAWK_PPC_XSOFF3_OFF			0x5c
-
-/*
- * Define PCI register offsets.
- */
-#define HAWK_PCI_PSADD0_OFF			0x80
-#define HAWK_PCI_PSOFF0_OFF			0x84
-#define HAWK_PCI_PSADD1_OFF			0x88
-#define HAWK_PCI_PSOFF1_OFF			0x8c
-#define HAWK_PCI_PSADD2_OFF			0x90
-#define HAWK_PCI_PSOFF2_OFF			0x94
-#define HAWK_PCI_PSADD3_OFF			0x98
-#define HAWK_PCI_PSOFF3_OFF			0x9c
-
-/*
- * Define the System Memory Controller (SMC) register offsets.
- */
-#define HAWK_SMC_RAM_A_SIZE_REG_OFF		0x10
-#define HAWK_SMC_RAM_B_SIZE_REG_OFF		0x11
-#define HAWK_SMC_RAM_C_SIZE_REG_OFF		0x12
-#define HAWK_SMC_RAM_D_SIZE_REG_OFF		0x13
-#define HAWK_SMC_RAM_E_SIZE_REG_OFF		0xc0	/* HAWK Only */
-#define HAWK_SMC_RAM_F_SIZE_REG_OFF		0xc1	/* HAWK Only */
-#define HAWK_SMC_RAM_G_SIZE_REG_OFF		0xc2	/* HAWK Only */
-#define HAWK_SMC_RAM_H_SIZE_REG_OFF		0xc3	/* HAWK Only */
-
-#define FALCON_SMC_REG_COUNT			4
-#define HAWK_SMC_REG_COUNT			8
-#endif				/* __ASMPPC_HAWK_DEFS_H */
diff --git a/include/asm-ppc/highmem.h b/include/asm-ppc/highmem.h
deleted file mode 100644
index f7b21ee302b..00000000000
--- a/include/asm-ppc/highmem.h
+++ /dev/null
@@ -1,135 +0,0 @@
-/*
- * highmem.h: virtual kernel memory mappings for high memory
- *
- * PowerPC version, stolen from the i386 version.
- *
- * Used in CONFIG_HIGHMEM systems for memory pages which
- * are not addressable by direct kernel virtual addresses.
- *
- * Copyright (C) 1999 Gerhard Wichert, Siemens AG
- *		      Gerhard.Wichert@pdb.siemens.de
- *
- *
- * Redesigned the x86 32-bit VM architecture to deal with
- * up to 16 Terrabyte physical memory. With current x86 CPUs
- * we now support up to 64 Gigabytes physical RAM.
- *
- * Copyright (C) 1999 Ingo Molnar <mingo@redhat.com>
- */
-
-#ifndef _ASM_HIGHMEM_H
-#define _ASM_HIGHMEM_H
-
-#ifdef __KERNEL__
-
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <asm/kmap_types.h>
-#include <asm/tlbflush.h>
-#include <asm/page.h>
-
-/* undef for production */
-#define HIGHMEM_DEBUG 1
-
-extern pte_t *kmap_pte;
-extern pgprot_t kmap_prot;
-extern pte_t *pkmap_page_table;
-
-/*
- * Right now we initialize only a single pte table. It can be extended
- * easily, subsequent pte tables have to be allocated in one physical
- * chunk of RAM.
- */
-#define PKMAP_BASE 	CONFIG_HIGHMEM_START
-#define LAST_PKMAP 	(1 << PTE_SHIFT)
-#define LAST_PKMAP_MASK (LAST_PKMAP-1)
-#define PKMAP_NR(virt)  ((virt-PKMAP_BASE) >> PAGE_SHIFT)
-#define PKMAP_ADDR(nr)  (PKMAP_BASE + ((nr) << PAGE_SHIFT))
-
-#define KMAP_FIX_BEGIN	(PKMAP_BASE + 0x00400000UL)
-
-extern void *kmap_high(struct page *page);
-extern void kunmap_high(struct page *page);
-
-static inline void *kmap(struct page *page)
-{
-	might_sleep();
-	if (!PageHighMem(page))
-		return page_address(page);
-	return kmap_high(page);
-}
-
-static inline void kunmap(struct page *page)
-{
-	BUG_ON(in_interrupt());
-	if (!PageHighMem(page))
-		return;
-	kunmap_high(page);
-}
-
-/*
- * The use of kmap_atomic/kunmap_atomic is discouraged - kmap/kunmap
- * gives a more generic (and caching) interface. But kmap_atomic can
- * be used in IRQ contexts, so in some (very limited) cases we need
- * it.
- */
-static inline void *kmap_atomic(struct page *page, enum km_type type)
-{
-	unsigned int idx;
-	unsigned long vaddr;
-
-	/* even !CONFIG_PREEMPT needs this, for in_atomic in do_page_fault */
-	pagefault_disable();
-	if (!PageHighMem(page))
-		return page_address(page);
-
-	idx = type + KM_TYPE_NR*smp_processor_id();
-	vaddr = KMAP_FIX_BEGIN + idx * PAGE_SIZE;
-#ifdef HIGHMEM_DEBUG
-	BUG_ON(!pte_none(*(kmap_pte+idx)));
-#endif
-	set_pte_at(&init_mm, vaddr, kmap_pte+idx, mk_pte(page, kmap_prot));
-	flush_tlb_page(NULL, vaddr);
-
-	return (void*) vaddr;
-}
-
-static inline void kunmap_atomic(void *kvaddr, enum km_type type)
-{
-#ifdef HIGHMEM_DEBUG
-	unsigned long vaddr = (unsigned long) kvaddr & PAGE_MASK;
-	unsigned int idx = type + KM_TYPE_NR*smp_processor_id();
-
-	if (vaddr < KMAP_FIX_BEGIN) { // FIXME
-		pagefault_enable();
-		return;
-	}
-
-	BUG_ON(vaddr != KMAP_FIX_BEGIN + idx * PAGE_SIZE);
-
-	/*
-	 * force other mappings to Oops if they'll try to access
-	 * this pte without first remap it
-	 */
-	pte_clear(&init_mm, vaddr, kmap_pte+idx);
-	flush_tlb_page(NULL, vaddr);
-#endif
-	pagefault_enable();
-}
-
-static inline struct page *kmap_atomic_to_page(void *ptr)
-{
-	unsigned long idx, vaddr = (unsigned long) ptr;
-
-	if (vaddr < KMAP_FIX_BEGIN)
-		return virt_to_page(ptr);
-
-	idx = (vaddr - KMAP_FIX_BEGIN) >> PAGE_SHIFT;
-	return pte_page(kmap_pte[idx]);
-}
-
-#define flush_cache_kmaps()	flush_cache_all()
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_HIGHMEM_H */
diff --git a/include/asm-ppc/hydra.h b/include/asm-ppc/hydra.h
deleted file mode 100644
index 1ad4eed07fb..00000000000
--- a/include/asm-ppc/hydra.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- *  include/asm-ppc/hydra.h -- Mac I/O `Hydra' definitions
- *
- *  Copyright (C) 1997 Geert Uytterhoeven
- *
- *  This file is based on the following documentation:
- *
- *	Macintosh Technology in the Common Hardware Reference Platform
- *	Apple Computer, Inc.
- *
- *	© Copyright 1995 Apple Computer, Inc. All rights reserved.
- *
- *  It's available online from http://chrp.apple.com/MacTech.pdf.
- *  You can obtain paper copies of this book from computer bookstores or by
- *  writing Morgan Kaufmann Publishers, Inc., 340 Pine Street, Sixth Floor, San
- *  Francisco, CA 94104. Reference ISBN 1-55860-393-X.
- *
- *  This file is subject to the terms and conditions of the GNU General Public
- *  License.  See the file COPYING in the main directory of this archive
- *  for more details.
- */
-
-#ifndef _ASMPPC_HYDRA_H
-#define _ASMPPC_HYDRA_H
-
-#ifdef __KERNEL__
-
-struct Hydra {
-    /* DBDMA Controller Register Space */
-    char Pad1[0x30];
-    u_int CachePD;
-    u_int IDs;
-    u_int Feature_Control;
-    char Pad2[0x7fc4];
-    /* DBDMA Channel Register Space */
-    char SCSI_DMA[0x100];
-    char Pad3[0x300];
-    char SCCA_Tx_DMA[0x100];
-    char SCCA_Rx_DMA[0x100];
-    char SCCB_Tx_DMA[0x100];
-    char SCCB_Rx_DMA[0x100];
-    char Pad4[0x7800];
-    /* Device Register Space */
-    char SCSI[0x1000];
-    char ADB[0x1000];
-    char SCC_Legacy[0x1000];
-    char SCC[0x1000];
-    char Pad9[0x2000];
-    char VIA[0x2000];
-    char Pad10[0x28000];
-    char OpenPIC[0x40000];
-};
-
-extern volatile struct Hydra __iomem *Hydra;
-
-
-    /*
-     *  Feature Control Register
-     */
-
-#define HYDRA_FC_SCC_CELL_EN	0x00000001	/* Enable SCC Clock */
-#define HYDRA_FC_SCSI_CELL_EN	0x00000002	/* Enable SCSI Clock */
-#define HYDRA_FC_SCCA_ENABLE	0x00000004	/* Enable SCC A Lines */
-#define HYDRA_FC_SCCB_ENABLE	0x00000008	/* Enable SCC B Lines */
-#define HYDRA_FC_ARB_BYPASS	0x00000010	/* Bypass Internal Arbiter */
-#define HYDRA_FC_RESET_SCC	0x00000020	/* Reset SCC */
-#define HYDRA_FC_MPIC_ENABLE	0x00000040	/* Enable OpenPIC */
-#define HYDRA_FC_SLOW_SCC_PCLK	0x00000080	/* 1=15.6672, 0=25 MHz */
-#define HYDRA_FC_MPIC_IS_MASTER	0x00000100	/* OpenPIC Master Mode */
-
-
-    /*
-     *  OpenPIC Interrupt Sources
-     */
-
-#define HYDRA_INT_SIO		0
-#define HYDRA_INT_SCSI_DMA	1
-#define HYDRA_INT_SCCA_TX_DMA	2
-#define HYDRA_INT_SCCA_RX_DMA	3
-#define HYDRA_INT_SCCB_TX_DMA	4
-#define HYDRA_INT_SCCB_RX_DMA	5
-#define HYDRA_INT_SCSI		6
-#define HYDRA_INT_SCCA		7
-#define HYDRA_INT_SCCB		8
-#define HYDRA_INT_VIA		9
-#define HYDRA_INT_ADB		10
-#define HYDRA_INT_ADB_NMI	11
-#define HYDRA_INT_EXT1		12	/* PCI IRQW */
-#define HYDRA_INT_EXT2		13	/* PCI IRQX */
-#define HYDRA_INT_EXT3		14	/* PCI IRQY */
-#define HYDRA_INT_EXT4		15	/* PCI IRQZ */
-#define HYDRA_INT_EXT5		16	/* IDE Primay/Secondary */
-#define HYDRA_INT_EXT6		17	/* IDE Secondary */
-#define HYDRA_INT_EXT7		18	/* Power Off Request */
-#define HYDRA_INT_SPARE		19
-
-extern int hydra_init(void);
-extern void macio_adb_init(void);
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASMPPC_HYDRA_H */
diff --git a/include/asm-ppc/ibm403.h b/include/asm-ppc/ibm403.h
deleted file mode 100644
index c9c5d539cfd..00000000000
--- a/include/asm-ppc/ibm403.h
+++ /dev/null
@@ -1,478 +0,0 @@
-/*
- * Authors: Armin Kuster <akuster@mvista.com> and Tom Rini <trini@mvista.com>
- *
- * 2001 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-
-#ifdef __KERNEL__
-#ifndef __ASM_IBM403_H__
-#define __ASM_IBM403_H__
-
-
-#if defined(CONFIG_403GCX)
-
-#define	DCRN_BE_BASE		0x090
-#define	DCRN_DMA0_BASE		0x0C0
-#define	DCRN_DMA1_BASE		0x0C8
-#define	DCRN_DMA2_BASE		0x0D0
-#define	DCRN_DMA3_BASE		0x0D8
-#define DCRNCAP_DMA_CC		1	/* have DMA chained count capability */
-#define	DCRN_DMASR_BASE		0x0E0
-
-#define	DCRN_EXIER_BASE		0x042
-#define	DCRN_EXISR_BASE		0x040
-#define	DCRN_IOCR_BASE		0x0A0
-
-
-/* ------------------------------------------------------------------------- */
-#endif
-
-
-
-#ifdef DCRN_BE_BASE
-#define	DCRN_BEAR	(DCRN_BE_BASE + 0x0)	/* Bus Error Address Register */
-#define	DCRN_BESR	(DCRN_BE_BASE + 0x1)	/* Bus Error Syndrome Register*/
-#endif
-/* DCRN_BESR */
-#define BESR_DSES	0x80000000	/* Data-Side Error Status */
-#define BESR_DMES	0x40000000	/* DMA Error Status */
-#define BESR_RWS	0x20000000	/* Read/Write Status */
-#define BESR_ETMASK	0x1C000000	/* Error Type */
-#define ET_PROT	0
-#define ET_PARITY	1
-#define ET_NCFG	2
-#define ET_BUSERR	4
-#define ET_BUSTO	6
-
-#ifdef DCRN_CHCR_BASE
-#define DCRN_CHCR0	(DCRN_CHCR_BASE + 0x0)	/* Chip Control Register 1 */
-#define DCRN_CHCR1	(DCRN_CHCR_BASE + 0x1)	/* Chip Control Register 2 */
-#endif
-#define CHR1_CETE	0x00800000		 /* CPU external timer enable */
-#define CHR1_PCIPW	0x00008000 /* PCI Int enable/Peripheral Write enable */
-
-#ifdef DCRN_CHPSR_BASE
-#define DCRN_CHPSR	(DCRN_CHPSR_BASE + 0x0)	/* Chip Pin Strapping */
-#endif
-
-#ifdef DCRN_CIC_BASE
-#define DCRN_CICCR	(DCRN_CIC_BASE + 0x0)	/* CIC Control Register */
-#define DCRN_DMAS1	(DCRN_CIC_BASE + 0x1)	/* DMA Select1 Register */
-#define DCRN_DMAS2	(DCRN_CIC_BASE + 0x2)	/* DMA Select2 Register */
-#define DCRN_CICVCR	(DCRN_CIC_BASE + 0x3)	/* CIC Video COntro Register */
-#define DCRN_CICSEL3	(DCRN_CIC_BASE + 0x5)	/* CIC Select 3 Register */
-#define DCRN_SGPO	(DCRN_CIC_BASE + 0x6)	/* CIC GPIO Output Register */
-#define DCRN_SGPOD	(DCRN_CIC_BASE + 0x7)	/* CIC GPIO OD Register */
-#define DCRN_SGPTC	(DCRN_CIC_BASE + 0x8)	/* CIC GPIO Tristate Ctrl Reg */
-#define DCRN_SGPI	(DCRN_CIC_BASE + 0x9)	/* CIC GPIO Input Reg */
-#endif
-
-#ifdef DCRN_CPMFR_BASE
-#define DCRN_CPMFR	(DCRN_CPMFR_BASE + 0x0)	/* CPM Force */
-#endif
-
-#ifndef CPM_AUD
-#define CPM_AUD		0x00000000
-#endif
-#ifndef CPM_BRG
-#define CPM_BRG		0x00000000
-#endif
-#ifndef CPM_CBS
-#define CPM_CBS		0x00000000
-#endif
-#ifndef CPM_CPU
-#define CPM_CPU		0x00000000
-#endif
-#ifndef CPM_DCP
-#define CPM_DCP		0x00000000
-#endif
-#ifndef CPM_DCRX
-#define CPM_DCRX	0x00000000
-#endif
-#ifndef CPM_DENC
-#define CPM_DENC	0x00000000
-#endif
-#ifndef CPM_DMA
-#define CPM_DMA		0x00000000
-#endif
-#ifndef CPM_DSCR
-#define CPM_DSCR	0x00000000
-#endif
-#ifndef CPM_EBC
-#define CPM_EBC		0x00000000
-#endif
-#ifndef CPM_EBIU
-#define CPM_EBIU	0x00000000
-#endif
-#ifndef CPM_EMAC_MM
-#define CPM_EMAC_MM	0x00000000
-#endif
-#ifndef CPM_EMAC_RM
-#define CPM_EMAC_RM	0x00000000
-#endif
-#ifndef CPM_EMAC_TM
-#define CPM_EMAC_TM	0x00000000
-#endif
-#ifndef CPM_GPIO0
-#define CPM_GPIO0	0x00000000
-#endif
-#ifndef CPM_GPT
-#define CPM_GPT		0x00000000
-#endif
-#ifndef CPM_I1284
-#define CPM_I1284	0x00000000
-#endif
-#ifndef CPM_IIC0
-#define CPM_IIC0	0x00000000
-#endif
-#ifndef CPM_IIC1
-#define CPM_IIC1	0x00000000
-#endif
-#ifndef CPM_MSI
-#define CPM_MSI		0x00000000
-#endif
-#ifndef CPM_PCI
-#define CPM_PCI		0x00000000
-#endif
-#ifndef CPM_PLB
-#define CPM_PLB		0x00000000
-#endif
-#ifndef CPM_SC0
-#define CPM_SC0		0x00000000
-#endif
-#ifndef CPM_SC1
-#define CPM_SC1		0x00000000
-#endif
-#ifndef CPM_SDRAM0
-#define CPM_SDRAM0	0x00000000
-#endif
-#ifndef CPM_SDRAM1
-#define CPM_SDRAM1	0x00000000
-#endif
-#ifndef CPM_TMRCLK
-#define CPM_TMRCLK	0x00000000
-#endif
-#ifndef CPM_UART0
-#define CPM_UART0	0x00000000
-#endif
-#ifndef CPM_UART1
-#define CPM_UART1	0x00000000
-#endif
-#ifndef CPM_UART2
-#define CPM_UART2	0x00000000
-#endif
-#ifndef CPM_UIC
-#define CPM_UIC		0x00000000
-#endif
-#ifndef CPM_VID2
-#define CPM_VID2	0x00000000
-#endif
-#ifndef CPM_XPT27
-#define CPM_XPT27	0x00000000
-#endif
-#ifndef CPM_XPT54
-#define CPM_XPT54	0x00000000
-#endif
-
-#ifdef DCRN_CPMSR_BASE
-#define DCRN_CPMSR	(DCRN_CPMSR_BASE + 0x0)	/* CPM Status */
-#define DCRN_CPMER	(DCRN_CPMSR_BASE + 0x1)	/* CPM Enable */
-#endif
-
-#ifdef DCRN_DCP0_BASE
-#define DCRN_DCP0_CFGADDR	(DCRN_DCP0_BASE + 0x0)	/* Decompression Controller Address */
-#define DCRN_DCP0_CFGDATA	(DCRN_DCP0_BASE + 0x1)	/* Decompression Controller Data */
-#endif
-
-#ifdef DCRN_DCRX_BASE
-#define DCRN_DCRXICR	(DCRN_DCRX_BASE + 0x0)	/* Internal Control Register */
-#define DCRN_DCRXISR	(DCRN_DCRX_BASE + 0x1)	/* Internal Status Register */
-#define DCRN_DCRXECR	(DCRN_DCRX_BASE + 0x2)	/* External Control Register */
-#define DCRN_DCRXESR	(DCRN_DCRX_BASE + 0x3)	/* External Status Register */
-#define DCRN_DCRXTAR	(DCRN_DCRX_BASE + 0x4)	/* Target Address Register */
-#define DCRN_DCRXTDR	(DCRN_DCRX_BASE + 0x5)	/* Target Data Register */
-#define DCRN_DCRXIGR	(DCRN_DCRX_BASE + 0x6)	/* Interrupt Generation Register */
-#define DCRN_DCRXBCR	(DCRN_DCRX_BASE + 0x7)	/* Line Buffer Control Register */
-#endif
-
-#ifdef DCRN_DMA0_BASE
-#define	DCRN_DMACR0	(DCRN_DMA0_BASE + 0x0)	/* DMA Channel Control Register 0 */
-#define	DCRN_DMACT0	(DCRN_DMA0_BASE + 0x1)	/* DMA Count Register 0 */
-#define	DCRN_DMADA0	(DCRN_DMA0_BASE + 0x2)	/* DMA Destination Address Register 0 */
-#define	DCRN_DMASA0	(DCRN_DMA0_BASE + 0x3)	/* DMA Source Address Register 0 */
-#ifdef DCRNCAP_DMA_CC
-#define	DCRN_DMACC0	(DCRN_DMA0_BASE + 0x4)	/* DMA Chained Count Register 0 */
-#endif
-
-#ifdef DCRNCAP_DMA_SG
-#define DCRN_ASG0	(DCRN_DMA0_BASE + 0x4)	/* DMA Scatter/Gather Descriptor Addr 0 */
-#endif
-#endif
-
-#ifdef DCRN_DMA1_BASE
-#define	DCRN_DMACR1	(DCRN_DMA1_BASE + 0x0)	/* DMA Channel Control Register 1 */
-#define	DCRN_DMACT1	(DCRN_DMA1_BASE + 0x1)	/* DMA Count Register 1 */
-#define	DCRN_DMADA1	(DCRN_DMA1_BASE + 0x2)	/* DMA Destination Address Register 1 */
-#define	DCRN_DMASA1	(DCRN_DMA1_BASE + 0x3)	/* DMA Source Address Register 1 */
-
-#ifdef DCRNCAP_DMA_CC
-#define	DCRN_DMACC1	(DCRN_DMA1_BASE + 0x4)	/* DMA Chained Count Register 1 */
-#endif
-#ifdef DCRNCAP_DMA_SG
-#define DCRN_ASG1	(DCRN_DMA1_BASE + 0x4)	/* DMA Scatter/Gather Descriptor Addr 1 */
-#endif
-#endif
-
-#ifdef DCRN_DMA2_BASE
-#define	DCRN_DMACR2	(DCRN_DMA2_BASE + 0x0)	/* DMA Channel Control Register 2 */
-#define	DCRN_DMACT2	(DCRN_DMA2_BASE + 0x1)	/* DMA Count Register 2 */
-#define	DCRN_DMADA2	(DCRN_DMA2_BASE + 0x2)	/* DMA Destination Address Register 2 */
-#define	DCRN_DMASA2	(DCRN_DMA2_BASE + 0x3)	/* DMA Source Address Register 2 */
-#ifdef DCRNCAP_DMA_CC
-#define	DCRN_DMACC2	(DCRN_DMA2_BASE + 0x4)	/* DMA Chained Count Register 2 */
-#endif
-#ifdef DCRNCAP_DMA_SG
-#define DCRN_ASG2	(DCRN_DMA2_BASE + 0x4)	/* DMA Scatter/Gather Descriptor Addr 2 */
-#endif
-#endif
-
-#ifdef DCRN_DMA3_BASE
-#define	DCRN_DMACR3	(DCRN_DMA3_BASE + 0x0)	/* DMA Channel Control Register 3 */
-#define	DCRN_DMACT3	(DCRN_DMA3_BASE + 0x1)	/* DMA Count Register 3 */
-#define	DCRN_DMADA3	(DCRN_DMA3_BASE + 0x2)	/* DMA Destination Address Register 3 */
-#define	DCRN_DMASA3	(DCRN_DMA3_BASE + 0x3)	/* DMA Source Address Register 3 */
-#ifdef DCRNCAP_DMA_CC
-#define	DCRN_DMACC3	(DCRN_DMA3_BASE + 0x4)	/* DMA Chained Count Register 3 */
-#endif
-#ifdef DCRNCAP_DMA_SG
-#define DCRN_ASG3	(DCRN_DMA3_BASE + 0x4)	/* DMA Scatter/Gather Descriptor Addr 3 */
-#endif
-#endif
-
-#ifdef DCRN_DMASR_BASE
-#define	DCRN_DMASR	(DCRN_DMASR_BASE + 0x0)	/* DMA Status Register */
-#ifdef DCRNCAP_DMA_SG
-#define DCRN_ASGC	(DCRN_DMASR_BASE + 0x3)	/* DMA Scatter/Gather Command */
-/* don't know if these two registers always exist if scatter/gather exists */
-#define DCRN_POL	(DCRN_DMASR_BASE + 0x6)	/* DMA Polarity Register */
-#define DCRN_SLP	(DCRN_DMASR_BASE + 0x5)	/* DMA Sleep Register */
-#endif
-#endif
-
-#ifdef DCRN_EBC_BASE
-#define DCRN_EBCCFGADR	(DCRN_EBC_BASE + 0x0)	/* Peripheral Controller Address */
-#define DCRN_EBCCFGDATA	(DCRN_EBC_BASE + 0x1)	/* Peripheral Controller Data */
-#endif
-
-#ifdef DCRN_EXIER_BASE
-#define	DCRN_EXIER	(DCRN_EXIER_BASE + 0x0)	/* External Interrupt Enable Register */
-#endif
-
-#ifdef DCRN_EBIMC_BASE
-#define DCRN_BRCRH0	(DCRN_EBIMC_BASE + 0x0) /* Bus Region Config High 0 */
-#define DCRN_BRCRH1	(DCRN_EBIMC_BASE + 0x1) /* Bus Region Config High 1 */
-#define DCRN_BRCRH2	(DCRN_EBIMC_BASE + 0x2) /* Bus Region Config High 2 */
-#define DCRN_BRCRH3	(DCRN_EBIMC_BASE + 0x3) /* Bus Region Config High 3 */
-#define DCRN_BRCRH4	(DCRN_EBIMC_BASE + 0x4) /* Bus Region Config High 4 */
-#define DCRN_BRCRH5	(DCRN_EBIMC_BASE + 0x5) /* Bus Region Config High 5 */
-#define DCRN_BRCRH6	(DCRN_EBIMC_BASE + 0x6) /* Bus Region Config High 6 */
-#define DCRN_BRCRH7	(DCRN_EBIMC_BASE + 0x7) /* Bus Region Config High 7 */
-#define DCRN_BRCR0	(DCRN_EBIMC_BASE + 0x10)/* BRC 0 */
-#define DCRN_BRCR1	(DCRN_EBIMC_BASE + 0x11)/* BRC 1 */
-#define DCRN_BRCR2	(DCRN_EBIMC_BASE + 0x12)/* BRC 2 */
-#define DCRN_BRCR3	(DCRN_EBIMC_BASE + 0x13)/* BRC 3 */
-#define DCRN_BRCR4	(DCRN_EBIMC_BASE + 0x14)/* BRC 4 */
-#define DCRN_BRCR5	(DCRN_EBIMC_BASE + 0x15)/* BRC 5 */
-#define DCRN_BRCR6	(DCRN_EBIMC_BASE + 0x16)/* BRC 6 */
-#define DCRN_BRCR7	(DCRN_EBIMC_BASE + 0x17)/* BRC 7 */
-#define DCRN_BEAR0	(DCRN_EBIMC_BASE + 0x20)/* Bus Error Address Register */
-#define DCRN_BESR0	(DCRN_EBIMC_BASE + 0x21)/* Bus Error Status Register */
-#define DCRN_BIUCR	(DCRN_EBIMC_BASE + 0x2A)/* Bus Interfac Unit Ctrl Reg */
-#endif
-
-#ifdef DCRN_EXISR_BASE
-#define	DCRN_EXISR	(DCRN_EXISR_BASE + 0x0)	/* External Interrupt Status Register */
-#endif
-#define EXIER_CIE	0x80000000	/* Critical Interrupt Enable */
-#define EXIER_SRIE	0x08000000	/* Serial Port Rx Int. Enable */
-#define EXIER_STIE	0x04000000	/* Serial Port Tx Int. Enable */
-#define EXIER_JRIE	0x02000000	/* JTAG Serial Port Rx Int. Enable */
-#define EXIER_JTIE	0x01000000	/* JTAG Serial Port Tx Int. Enable */
-#define EXIER_D0IE	0x00800000	/* DMA Channel 0 Interrupt Enable */
-#define EXIER_D1IE	0x00400000	/* DMA Channel 1 Interrupt Enable */
-#define EXIER_D2IE	0x00200000	/* DMA Channel 2 Interrupt Enable */
-#define EXIER_D3IE	0x00100000	/* DMA Channel 3 Interrupt Enable */
-#define EXIER_E0IE	0x00000010	/* External Interrupt 0 Enable */
-#define EXIER_E1IE	0x00000008	/* External Interrupt 1 Enable */
-#define EXIER_E2IE	0x00000004	/* External Interrupt 2 Enable */
-#define EXIER_E3IE	0x00000002	/* External Interrupt 3 Enable */
-#define EXIER_E4IE	0x00000001	/* External Interrupt 4 Enable */
-
-#ifdef DCRN_IOCR_BASE
-#define	DCRN_IOCR	(DCRN_IOCR_BASE + 0x0)	/* Input/Output Configuration Register */
-#endif
-#define IOCR_E0TE	0x80000000
-#define IOCR_E0LP	0x40000000
-#define IOCR_E1TE	0x20000000
-#define IOCR_E1LP	0x10000000
-#define IOCR_E2TE	0x08000000
-#define IOCR_E2LP	0x04000000
-#define IOCR_E3TE	0x02000000
-#define IOCR_E3LP	0x01000000
-#define IOCR_E4TE	0x00800000
-#define IOCR_E4LP	0x00400000
-#define IOCR_EDT	0x00080000
-#define IOCR_SOR	0x00040000
-#define IOCR_EDO	0x00008000
-#define IOCR_2XC	0x00004000
-#define IOCR_ATC	0x00002000
-#define IOCR_SPD	0x00001000
-#define IOCR_BEM	0x00000800
-#define IOCR_PTD	0x00000400
-#define IOCR_ARE	0x00000080
-#define IOCR_DRC	0x00000020
-#define IOCR_RDM(x)	(((x) & 0x3) << 3)
-#define IOCR_TCS	0x00000004
-#define IOCR_SCS	0x00000002
-#define IOCR_SPC	0x00000001
-
-#ifdef DCRN_MAL_BASE
-#define DCRN_MALCR		(DCRN_MAL_BASE + 0x0) /* MAL Configuration */
-#define DCRN_MALDBR		(DCRN_MAL_BASE + 0x3) /* Debug Register */
-#define DCRN_MALESR		(DCRN_MAL_BASE + 0x1) /* Error Status */
-#define DCRN_MALIER		(DCRN_MAL_BASE + 0x2) /* Interrupt Enable */
-#define DCRN_MALTXCARR		(DCRN_MAL_BASE + 0x5) /* TX Channed Active Reset Register */
-#define DCRN_MALTXCASR		(DCRN_MAL_BASE + 0x4) /* TX Channel Active Set Register */
-#define DCRN_MALTXDEIR		(DCRN_MAL_BASE + 0x7) /* Tx Descriptor Error Interrupt */
-#define DCRN_MALTXEOBISR	(DCRN_MAL_BASE + 0x6) /* Tx End of Buffer Interrupt Status  */
-#define DCRN_MALRXCARR		(DCRN_MAL_BASE + 0x11) /* RX Channed Active Reset Register */
-#define DCRN_MALRXCASR		(DCRN_MAL_BASE + 0x10) /* RX Channel Active Set Register */
-#define DCRN_MALRXDEIR		(DCRN_MAL_BASE + 0x13) /* Rx Descriptor Error Interrupt */
-#define DCRN_MALRXEOBISR	(DCRN_MAL_BASE + 0x12) /* Rx End of Buffer Interrupt Status  */
-#define DCRN_MALRXCTP0R		(DCRN_MAL_BASE + 0x40) /* Channel Rx 0 Channel Table Pointer */
-#define DCRN_MALTXCTP0R		(DCRN_MAL_BASE + 0x20) /* Channel Tx 0 Channel Table Pointer */
-#define DCRN_MALTXCTP1R		(DCRN_MAL_BASE + 0x21) /* Channel Tx 1 Channel Table Pointer */
-#define DCRN_MALRCBS0		(DCRN_MAL_BASE + 0x60) /* Channel Rx 0 Channel Buffer Size */
-#endif
-/* DCRN_MALCR */
-#define MALCR_MMSR		0x80000000/* MAL Software reset */
-#define MALCR_PLBP_1		0x00400000 /* MAL reqest priority: */
-#define MALCR_PLBP_2		0x00800000 /* lowsest is 00 */
-#define MALCR_PLBP_3		0x00C00000 /* highest */
-#define MALCR_GA		0x00200000 /* Guarded Active Bit */
-#define MALCR_OA		0x00100000 /* Ordered Active Bit */
-#define MALCR_PLBLE		0x00080000 /* PLB Lock Error Bit */
-#define MALCR_PLBLT_1		0x00040000 /* PLB Latency Timer */
-#define MALCR_PLBLT_2		0x00020000
-#define MALCR_PLBLT_3		0x00010000
-#define MALCR_PLBLT_4		0x00008000
-#define MALCR_PLBLT_DEFAULT	0x00078000 /* JSP: Is this a valid default?? */
-#define MALCR_PLBB		0x00004000 /* PLB Burst Deactivation Bit */
-#define MALCR_OPBBL		0x00000080 /* OPB Lock Bit */
-#define MALCR_EOPIE		0x00000004 /* End Of Packet Interrupt Enable */
-#define MALCR_LEA		0x00000002 /* Locked Error Active */
-#define MALCR_MSD		0x00000001 /* MAL Scroll Descriptor Bit */
-/* DCRN_MALESR */
-#define MALESR_EVB		0x80000000 /* Error Valid Bit */
-#define MALESR_CIDRX		0x40000000 /* Channel ID Receive */
-#define MALESR_DE		0x00100000 /* Descriptor Error */
-#define MALESR_OEN		0x00080000 /* OPB Non-Fullword Error */
-#define MALESR_OTE		0x00040000 /* OPB Timeout Error */
-#define MALESR_OSE		0x00020000 /* OPB Slave Error */
-#define MALESR_PEIN		0x00010000 /* PLB Bus Error Indication */
-#define MALESR_DEI		0x00000010 /* Descriptor Error Interrupt */
-#define MALESR_ONEI		0x00000008 /* OPB Non-Fullword Error Interrupt */
-#define MALESR_OTEI		0x00000004 /* OPB Timeout Error Interrupt */
-#define MALESR_OSEI		0x00000002 /* OPB Slace Error Interrupt */
-#define MALESR_PBEI		0x00000001 /* PLB Bus Error Interrupt */
-/* DCRN_MALIER */
-#define MALIER_DE		0x00000010 /* Descriptor Error Interrupt Enable */
-#define MALIER_NE		0x00000008 /* OPB Non-word Transfer Int Enable */
-#define MALIER_TE		0x00000004 /* OPB Time Out Error Interrupt Enable  */
-#define MALIER_OPBE		0x00000002 /* OPB Slave Error Interrupt Enable */
-#define MALIER_PLBE		0x00000001 /* PLB Error Interrupt Enable */
-/* DCRN_MALTXEOBISR */
-#define MALOBISR_CH0		0x80000000 /* EOB channel 1 bit */
-#define MALOBISR_CH2		0x40000000 /* EOB channel 2 bit */
-
-#ifdef DCRN_OCM0_BASE
-#define DCRN_OCMISARC	(DCRN_OCM0_BASE + 0x0)	/* OCM Instr Side Addr Range Compare */
-#define DCRN_OCMISCR	(DCRN_OCM0_BASE + 0x1)	/* OCM Instr Side Control */
-#define DCRN_OCMDSARC	(DCRN_OCM0_BASE + 0x2)	/* OCM Data Side Addr Range Compare */
-#define DCRN_OCMDSCR	(DCRN_OCM0_BASE + 0x3)	/* OCM Data Side Control */
-#endif
-
-#ifdef DCRN_PLB0_BASE
-#define DCRN_PLB0_BESR	(DCRN_PLB0_BASE + 0x0)
-#define DCRN_PLB0_BEAR	(DCRN_PLB0_BASE + 0x2)
-/* doesn't exist on stb03xxx? */
-#define DCRN_PLB0_ACR	(DCRN_PLB0_BASE + 0x3)
-#endif
-
-#ifdef DCRN_PLB1_BASE
-#define DCRN_PLB1_BESR	(DCRN_PLB1_BASE + 0x0)
-#define DCRN_PLB1_BEAR	(DCRN_PLB1_BASE + 0x1)
-/* doesn't exist on stb03xxx? */
-#define DCRN_PLB1_ACR	(DCRN_PLB1_BASE + 0x2)
-#endif
-
-#ifdef DCRN_PLLMR_BASE
-#define DCRN_PLLMR	(DCRN_PLLMR_BASE + 0x0)	/* PL1 Mode */
-#endif
-
-#ifdef DCRN_POB0_BASE
-#define DCRN_POB0_BESR0	(DCRN_POB0_BASE + 0x0)
-#define DCRN_POB0_BEAR	(DCRN_POB0_BASE + 0x2)
-#define DCRN_POB0_BESR1	(DCRN_POB0_BASE + 0x4)
-#endif
-
-#ifdef DCRN_SCCR_BASE
-#define DCRN_SCCR	(DCRN_SCCR_BASE + 0x0)
-#endif
-
-#ifdef DCRN_SDRAM0_BASE
-#define DCRN_SDRAM0_CFGADDR	(DCRN_SDRAM0_BASE + 0x0) /* Mem Ctrlr Address */
-#define DCRN_SDRAM0_CFGDATA	(DCRN_SDRAM0_BASE + 0x1) /* Mem Ctrlr Data */
-#endif
-
-#ifdef DCRN_UIC0_BASE
-#define DCRN_UIC0_SR	(DCRN_UIC0_BASE + 0x0)
-#define DCRN_UIC0_ER	(DCRN_UIC0_BASE + 0x2)
-#define DCRN_UIC0_CR	(DCRN_UIC0_BASE + 0x3)
-#define DCRN_UIC0_PR	(DCRN_UIC0_BASE + 0x4)
-#define DCRN_UIC0_TR	(DCRN_UIC0_BASE + 0x5)
-#define DCRN_UIC0_MSR	(DCRN_UIC0_BASE + 0x6)
-#define DCRN_UIC0_VR	(DCRN_UIC0_BASE + 0x7)
-#define DCRN_UIC0_VCR	(DCRN_UIC0_BASE + 0x8)
-#endif
-
-#ifdef DCRN_UIC1_BASE
-#define DCRN_UIC1_SR	(DCRN_UIC1_BASE + 0x0)
-#define DCRN_UIC1_SRS	(DCRN_UIC1_BASE + 0x1)
-#define DCRN_UIC1_ER	(DCRN_UIC1_BASE + 0x2)
-#define DCRN_UIC1_CR	(DCRN_UIC1_BASE + 0x3)
-#define DCRN_UIC1_PR	(DCRN_UIC1_BASE + 0x4)
-#define DCRN_UIC1_TR	(DCRN_UIC1_BASE + 0x5)
-#define DCRN_UIC1_MSR	(DCRN_UIC1_BASE + 0x6)
-#define DCRN_UIC1_VR	(DCRN_UIC1_BASE + 0x7)
-#define DCRN_UIC1_VCR	(DCRN_UIC1_BASE + 0x8)
-#endif
-
-#ifdef DCRN_SDRAM0_BASE
-#define DCRN_SDRAM0_CFGADDR	(DCRN_SDRAM0_BASE + 0x0) /* Memory Controller Address */
-#define DCRN_SDRAM0_CFGDATA	(DCRN_SDRAM0_BASE + 0x1) /* Memory Controller Data */
-#endif
-
-#ifdef DCRN_OCM0_BASE
-#define DCRN_OCMISARC	(DCRN_OCM0_BASE + 0x0) /* OCM Instr Side Addr Range Compare */
-#define DCRN_OCMISCR	(DCRN_OCM0_BASE + 0x1) /* OCM Instr Side Control */
-#define DCRN_OCMDSARC	(DCRN_OCM0_BASE + 0x2) /* OCM Data Side Addr Range Compare */
-#define DCRN_OCMDSCR	(DCRN_OCM0_BASE + 0x3) /* OCM Data Side Control */
-#endif
-
-#endif /* __ASM_IBM403_H__ */
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/ibm405.h b/include/asm-ppc/ibm405.h
deleted file mode 100644
index 4e5be9e2c15..00000000000
--- a/include/asm-ppc/ibm405.h
+++ /dev/null
@@ -1,299 +0,0 @@
-/*
- * Author: Armin Kuster <akuster@mvista.com>
- *
- * 2002 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#ifdef __KERNEL__
-#ifndef __ASM_IBM405_H__
-#define __ASM_IBM405_H__
-
-#ifdef DCRN_BE_BASE
-#define DCRN_BEAR	(DCRN_BE_BASE + 0x0)	/* Bus Error Address Register */
-#define DCRN_BESR	(DCRN_BE_BASE + 0x1)	/* Bus Error Syndrome Register */
-#endif
-/* DCRN_BESR */
-#define BESR_DSES	0x80000000	/* Data-Side Error Status */
-#define BESR_DMES	0x40000000	/* DMA Error Status */
-#define BESR_RWS	0x20000000	/* Read/Write Status */
-#define BESR_ETMASK	0x1C000000	/* Error Type */
-#define ET_PROT	0
-#define ET_PARITY	1
-#define ET_NCFG	2
-#define ET_BUSERR	4
-#define ET_BUSTO	6
-
-/* Clock and power management shifts for emacs */
-#define IBM_CPM_EMMII	0	/* Shift value for MII */
-#define IBM_CPM_EMRX	1	/* Shift value for recv */
-#define IBM_CPM_EMTX	2	/* Shift value for MAC */
-
-#ifdef DCRN_CHCR_BASE
-#define DCRN_CHCR0	(DCRN_CHCR_BASE + 0x0)	/* Chip Control Register 1 */
-#define DCRN_CHCR1	(DCRN_CHCR_BASE + 0x1)	/* Chip Control Register 2 */
-#endif
-#define CHR1_PCIPW	0x00008000	/* PCI Int enable/Peripheral Write enable */
-
-#ifdef DCRN_CHPSR_BASE
-#define DCRN_CHPSR	(DCRN_CHPSR_BASE + 0x0)	/* Chip Pin Strapping */
-#endif
-
-#ifdef DCRN_CPMFR_BASE
-#define DCRN_CPMFR	(DCRN_CPMFR_BASE + 0x0)	/* CPM Force */
-#endif
-
-#ifdef DCRN_CPMSR_BASE
-#define DCRN_CPMSR	(DCRN_CPMSR_BASE + 0x0)	/* CPM Status */
-#define DCRN_CPMER	(DCRN_CPMSR_BASE + 0x1)	/* CPM Enable */
-#endif
-
-#ifdef DCRN_DCP0_BASE
-/* Decompression Controller Address */
-#define DCRN_DCP0_CFGADDR	(DCRN_DCP0_BASE + 0x0)
-/* Decompression Controller Data */
-#define DCRN_DCP0_CFGDATA	(DCRN_DCP0_BASE + 0x1)
-#else
-#define DCRN_DCP0_CFGADDR	0x0
-#define DCRN_DCP0_CFGDATA	0x0
-#endif
-
-#ifdef DCRN_DMA0_BASE
-/* DMA Channel Control Register 0 */
-#define DCRN_DMACR0	(DCRN_DMA0_BASE + 0x0)
-#define DCRN_DMACT0	(DCRN_DMA0_BASE + 0x1)	/* DMA Count Register 0 */
-/* DMA Destination Address Register 0 */
-#define DCRN_DMADA0	(DCRN_DMA0_BASE + 0x2)
-/* DMA Source Address Register 0 */
-#define DCRN_DMASA0	(DCRN_DMA0_BASE + 0x3)
-#ifdef DCRNCAP_DMA_CC
-/* DMA Chained Count Register 0 */
-#define DCRN_DMACC0	(DCRN_DMA0_BASE + 0x4)
-#endif
-#ifdef DCRNCAP_DMA_SG
-/* DMA Scatter/Gather Descriptor Addr 0 */
-#define DCRN_ASG0	(DCRN_DMA0_BASE + 0x4)
-#endif
-#endif
-
-#ifdef DCRN_DMA1_BASE
-/* DMA Channel Control Register 1 */
-#define DCRN_DMACR1	(DCRN_DMA1_BASE + 0x0)
-#define DCRN_DMACT1	(DCRN_DMA1_BASE + 0x1)	/* DMA Count Register 1 */
-/* DMA Destination Address Register 1 */
-#define DCRN_DMADA1	(DCRN_DMA1_BASE + 0x2)
-/* DMA Source Address Register 1 */
-#define DCRN_DMASA1	(DCRN_DMA1_BASE + 0x3)	/* DMA Source Address Register 1 */
-#ifdef DCRNCAP_DMA_CC
-/* DMA Chained Count Register 1 */
-#define DCRN_DMACC1	(DCRN_DMA1_BASE + 0x4)
-#endif
-#ifdef DCRNCAP_DMA_SG
-/* DMA Scatter/Gather Descriptor Addr 1 */
-#define DCRN_ASG1	(DCRN_DMA1_BASE + 0x4)
-#endif
-#endif
-
-#ifdef DCRN_DMA2_BASE
-#define DCRN_DMACR2	(DCRN_DMA2_BASE + 0x0)	/* DMA Channel Control Register 2 */
-#define DCRN_DMACT2	(DCRN_DMA2_BASE + 0x1)	/* DMA Count Register 2 */
-#define DCRN_DMADA2	(DCRN_DMA2_BASE + 0x2)	/* DMA Destination Address Register 2 */
-#define DCRN_DMASA2	(DCRN_DMA2_BASE + 0x3)	/* DMA Source Address Register 2 */
-#ifdef DCRNCAP_DMA_CC
-#define DCRN_DMACC2	(DCRN_DMA2_BASE + 0x4)	/* DMA Chained Count Register 2 */
-#endif
-#ifdef DCRNCAP_DMA_SG
-#define DCRN_ASG2	(DCRN_DMA2_BASE + 0x4)	/* DMA Scatter/Gather Descriptor Addr 2 */
-#endif
-#endif
-
-#ifdef DCRN_DMA3_BASE
-#define DCRN_DMACR3	(DCRN_DMA3_BASE + 0x0)	/* DMA Channel Control Register 3 */
-#define DCRN_DMACT3	(DCRN_DMA3_BASE + 0x1)	/* DMA Count Register 3 */
-#define DCRN_DMADA3	(DCRN_DMA3_BASE + 0x2)	/* DMA Destination Address Register 3 */
-#define DCRN_DMASA3	(DCRN_DMA3_BASE + 0x3)	/* DMA Source Address Register 3 */
-#ifdef DCRNCAP_DMA_CC
-#define DCRN_DMACC3	(DCRN_DMA3_BASE + 0x4)	/* DMA Chained Count Register 3 */
-#endif
-#ifdef DCRNCAP_DMA_SG
-#define DCRN_ASG3	(DCRN_DMA3_BASE + 0x4)	/* DMA Scatter/Gather Descriptor Addr 3 */
-#endif
-#endif
-
-#ifdef DCRN_DMASR_BASE
-#define DCRN_DMASR	(DCRN_DMASR_BASE + 0x0)	/* DMA Status Register */
-#ifdef DCRNCAP_DMA_SG
-#define DCRN_ASGC	(DCRN_DMASR_BASE + 0x3)	/* DMA Scatter/Gather Command */
-/* don't know if these two registers always exist if scatter/gather exists */
-#define DCRN_POL	(DCRN_DMASR_BASE + 0x6)	/* DMA Polarity Register */
-#define DCRN_SLP	(DCRN_DMASR_BASE + 0x5)	/* DMA Sleep Register */
-#endif
-#endif
-
-#ifdef DCRN_EBC_BASE
-#define DCRN_EBCCFGADR	(DCRN_EBC_BASE + 0x0)	/* Peripheral Controller Address */
-#define DCRN_EBCCFGDATA	(DCRN_EBC_BASE + 0x1)	/* Peripheral Controller Data */
-#endif
-
-#ifdef DCRN_EXIER_BASE
-#define DCRN_EXIER	(DCRN_EXIER_BASE + 0x0)	/* External Interrupt Enable Register */
-#endif
-
-#ifdef DCRN_EXISR_BASE
-#define DCRN_EXISR	(DCRN_EXISR_BASE + 0x0)	/* External Interrupt Status Register */
-#endif
-
-#define EXIER_CIE	0x80000000	/* Critical Interrupt Enable */
-#define EXIER_SRIE	0x08000000	/* Serial Port Rx Int. Enable */
-#define EXIER_STIE	0x04000000	/* Serial Port Tx Int. Enable */
-#define EXIER_JRIE	0x02000000	/* JTAG Serial Port Rx Int. Enable */
-#define EXIER_JTIE	0x01000000	/* JTAG Serial Port Tx Int. Enable */
-#define EXIER_D0IE	0x00800000	/* DMA Channel 0 Interrupt Enable */
-#define EXIER_D1IE	0x00400000	/* DMA Channel 1 Interrupt Enable */
-#define EXIER_D2IE	0x00200000	/* DMA Channel 2 Interrupt Enable */
-#define EXIER_D3IE	0x00100000	/* DMA Channel 3 Interrupt Enable */
-#define EXIER_E0IE	0x00000010	/* External Interrupt 0 Enable */
-#define EXIER_E1IE	0x00000008	/* External Interrupt 1 Enable */
-#define EXIER_E2IE	0x00000004	/* External Interrupt 2 Enable */
-#define EXIER_E3IE	0x00000002	/* External Interrupt 3 Enable */
-#define EXIER_E4IE	0x00000001	/* External Interrupt 4 Enable */
-
-#ifdef DCRN_IOCR_BASE
-#define DCRN_IOCR	(DCRN_IOCR_BASE + 0x0)	/* Input/Output Configuration Register */
-#endif
-#define IOCR_E0TE	0x80000000
-#define IOCR_E0LP	0x40000000
-#define IOCR_E1TE	0x20000000
-#define IOCR_E1LP	0x10000000
-#define IOCR_E2TE	0x08000000
-#define IOCR_E2LP	0x04000000
-#define IOCR_E3TE	0x02000000
-#define IOCR_E3LP	0x01000000
-#define IOCR_E4TE	0x00800000
-#define IOCR_E4LP	0x00400000
-#define IOCR_EDT	0x00080000
-#define IOCR_SOR	0x00040000
-#define IOCR_EDO	0x00008000
-#define IOCR_2XC	0x00004000
-#define IOCR_ATC	0x00002000
-#define IOCR_SPD	0x00001000
-#define IOCR_BEM	0x00000800
-#define IOCR_PTD	0x00000400
-#define IOCR_ARE	0x00000080
-#define IOCR_DRC	0x00000020
-#define IOCR_RDM(x)	(((x) & 0x3) << 3)
-#define IOCR_TCS	0x00000004
-#define IOCR_SCS	0x00000002
-#define IOCR_SPC	0x00000001
-
-#define DCRN_MALCR(base)	(base + 0x0)	/* MAL Configuration */
-#define DCRN_MALDBR(base)	((base) + 0x3)	/* Debug Register */
-#define DCRN_MALESR(base)	((base) + 0x1)	/* Error Status */
-#define DCRN_MALIER(base)	((base) + 0x2)	/* Interrupt Enable */
-#define DCRN_MALTXCARR(base)	((base) + 0x5)	/* TX Channed Active Reset Register */
-#define DCRN_MALTXCASR(base)	((base) + 0x4)	/* TX Channel Active Set Register */
-#define DCRN_MALTXDEIR(base)	((base) + 0x7)	/* Tx Descriptor Error Interrupt */
-#define DCRN_MALTXEOBISR(base)	((base) + 0x6)	/* Tx End of Buffer Interrupt Status */
-#define DCRN_MALRXCARR(base)	((base) + 0x11)	/* RX Channed Active Reset Register */
-#define DCRN_MALRXCASR(base)	((base) + 0x10)	/* RX Channel Active Set Register */
-#define DCRN_MALRXDEIR(base)	((base) + 0x13)	/* Rx Descriptor Error Interrupt */
-#define DCRN_MALRXEOBISR(base)	((base) + 0x12)	/* Rx End of Buffer Interrupt Status */
-#define DCRN_MALRXCTP0R(base)	((base) + 0x40)	/* Channel Rx 0 Channel Table Pointer */
-#define DCRN_MALRXCTP1R(base)	((base) + 0x41)	/* Channel Rx 1 Channel Table Pointer */
-#define DCRN_MALTXCTP0R(base)	((base) + 0x20)	/* Channel Tx 0 Channel Table Pointer */
-#define DCRN_MALTXCTP1R(base)	((base) + 0x21)	/* Channel Tx 1 Channel Table Pointer */
-#define DCRN_MALTXCTP2R(base)	((base) + 0x22)	/* Channel Tx 2 Channel Table Pointer */
-#define DCRN_MALTXCTP3R(base)	((base) + 0x23)	/* Channel Tx 3 Channel Table Pointer */
-#define DCRN_MALRCBS0(base)	((base) + 0x60)	/* Channel Rx 0 Channel Buffer Size */
-#define DCRN_MALRCBS1(base)	((base) + 0x61)	/* Channel Rx 1 Channel Buffer Size */
-
- /* DCRN_MALCR */
-#define MALCR_MMSR		0x80000000	/* MAL Software reset */
-#define MALCR_PLBP_1		0x00400000	/* MAL reqest priority: */
-#define MALCR_PLBP_2		0x00800000	/* lowsest is 00 */
-#define MALCR_PLBP_3		0x00C00000	/* highest */
-#define MALCR_GA		0x00200000	/* Guarded Active Bit */
-#define MALCR_OA		0x00100000	/* Ordered Active Bit */
-#define MALCR_PLBLE		0x00080000	/* PLB Lock Error Bit */
-#define MALCR_PLBLT_1		0x00040000	/* PLB Latency Timer */
-#define MALCR_PLBLT_2 		0x00020000
-#define MALCR_PLBLT_3		0x00010000
-#define MALCR_PLBLT_4		0x00008000
-#define MALCR_PLBLT_DEFAULT	0x00078000	/* JSP: Is this a valid default?? */
-#define MALCR_PLBB		0x00004000	/* PLB Burst Deactivation Bit */
-#define MALCR_OPBBL		0x00000080	/* OPB Lock Bit */
-#define MALCR_EOPIE		0x00000004	/* End Of Packet Interrupt Enable */
-#define MALCR_LEA		0x00000002	/* Locked Error Active */
-#define MALCR_MSD		0x00000001	/* MAL Scroll Descriptor Bit */
-/* DCRN_MALESR */
-#define MALESR_EVB		0x80000000	/* Error Valid Bit */
-#define MALESR_CIDRX		0x40000000	/* Channel ID Receive */
-#define MALESR_DE		0x00100000	/* Descriptor Error */
-#define MALESR_OEN		0x00080000	/* OPB Non-Fullword Error */
-#define MALESR_OTE		0x00040000	/* OPB Timeout Error */
-#define MALESR_OSE		0x00020000	/* OPB Slave Error */
-#define MALESR_PEIN		0x00010000	/* PLB Bus Error Indication */
-#define MALESR_DEI		0x00000010	/* Descriptor Error Interrupt */
-#define MALESR_ONEI		0x00000008	/* OPB Non-Fullword Error Interrupt */
-#define MALESR_OTEI		0x00000004	/* OPB Timeout Error Interrupt */
-#define MALESR_OSEI		0x00000002	/* OPB Slace Error Interrupt */
-#define MALESR_PBEI		0x00000001	/* PLB Bus Error Interrupt */
-/* DCRN_MALIER */
-#define MALIER_DE		0x00000010	/* Descriptor Error Interrupt Enable */
-#define MALIER_NE		0x00000008	/* OPB Non-word Transfer Int Enable */
-#define MALIER_TE		0x00000004	/* OPB Time Out Error Interrupt Enable */
-#define MALIER_OPBE		0x00000002	/* OPB Slave Error Interrupt Enable */
-#define MALIER_PLBE		0x00000001	/* PLB Error Interrupt Enable */
-/* DCRN_MALTXEOBISR */
-#define MALOBISR_CH0		0x80000000	/* EOB channel 1 bit */
-#define MALOBISR_CH2		0x40000000	/* EOB channel 2 bit */
-
-#ifdef DCRN_PLB0_BASE
-#define DCRN_PLB0_BESR	(DCRN_PLB0_BASE + 0x0)
-#define DCRN_PLB0_BEAR	(DCRN_PLB0_BASE + 0x2)
-/* doesn't exist on stb03xxx? */
-#define DCRN_PLB0_ACR	(DCRN_PLB0_BASE + 0x3)
-#endif
-
-#ifdef DCRN_PLB1_BASE
-#define DCRN_PLB1_BESR	(DCRN_PLB1_BASE + 0x0)
-#define DCRN_PLB1_BEAR	(DCRN_PLB1_BASE + 0x1)
-/* doesn't exist on stb03xxx? */
-#define DCRN_PLB1_ACR	(DCRN_PLB1_BASE + 0x2)
-#endif
-
-#ifdef DCRN_PLLMR_BASE
-#define DCRN_PLLMR	(DCRN_PLLMR_BASE + 0x0)	/* PL1 Mode */
-#endif
-
-#ifdef DCRN_POB0_BASE
-#define DCRN_POB0_BESR0	(DCRN_POB0_BASE + 0x0)
-#define DCRN_POB0_BEAR	(DCRN_POB0_BASE + 0x2)
-#define DCRN_POB0_BESR1	(DCRN_POB0_BASE + 0x4)
-#endif
-
-#define DCRN_UIC_SR(base)	(base + 0x0)
-#define DCRN_UIC_ER(base)	(base + 0x2)
-#define DCRN_UIC_CR(base)	(base + 0x3)
-#define DCRN_UIC_PR(base)	(base + 0x4)
-#define DCRN_UIC_TR(base)	(base + 0x5)
-#define DCRN_UIC_MSR(base)	(base + 0x6)
-#define DCRN_UIC_VR(base)	(base + 0x7)
-#define DCRN_UIC_VCR(base)	(base + 0x8)
-
-#ifdef DCRN_SDRAM0_BASE
-#define DCRN_SDRAM0_CFGADDR	(DCRN_SDRAM0_BASE + 0x0)	/* Memory Controller Address */
-#define DCRN_SDRAM0_CFGDATA	(DCRN_SDRAM0_BASE + 0x1)	/* Memory Controller Data */
-#endif
-
-#ifdef DCRN_OCM0_BASE
-#define DCRN_OCMISARC	(DCRN_OCM0_BASE + 0x0)	/* OCM Instr Side Addr Range Compare */
-#define DCRN_OCMISCR	(DCRN_OCM0_BASE + 0x1)	/* OCM Instr Side Control */
-#define DCRN_OCMDSARC	(DCRN_OCM0_BASE + 0x2)	/* OCM Data Side Addr Range Compare */
-#define DCRN_OCMDSCR	(DCRN_OCM0_BASE + 0x3)	/* OCM Data Side Control */
-#endif
-
-#endif				/* __ASM_IBM405_H__ */
-#endif				/* __KERNEL__ */
diff --git a/include/asm-ppc/ibm44x.h b/include/asm-ppc/ibm44x.h
deleted file mode 100644
index 7818b54b6e3..00000000000
--- a/include/asm-ppc/ibm44x.h
+++ /dev/null
@@ -1,674 +0,0 @@
-/*
- * include/asm-ppc/ibm44x.h
- *
- * PPC44x definitions
- *
- * Matt Porter <mporter@kernel.crashing.org>
- *
- * Copyright 2002-2005 MontaVista Software Inc.
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-
-#ifdef __KERNEL__
-#ifndef __ASM_IBM44x_H__
-#define __ASM_IBM44x_H__
-
-
-#ifndef NR_BOARD_IRQS
-#define NR_BOARD_IRQS 0
-#endif
-
-#define _IO_BASE	isa_io_base
-#define _ISA_MEM_BASE	isa_mem_base
-#define PCI_DRAM_OFFSET	pci_dram_offset
-
-/* TLB entry offset/size used for pinning kernel lowmem */
-#define PPC44x_PIN_SHIFT	28
-#define PPC_PIN_SIZE		(1 << PPC44x_PIN_SHIFT)
-
-/* Lowest TLB slot consumed by the default pinned TLBs */
-#define PPC44x_LOW_SLOT		63
-
-/*
- * Least significant 32-bits and extended real page number (ERPN) of
- * UART0 physical address location for early serial text debug
- */
-#if defined(CONFIG_440SP)
-#define UART0_PHYS_ERPN		1
-#define UART0_PHYS_IO_BASE	0xf0000200
-#elif defined(CONFIG_440SPE)
-#define UART0_PHYS_ERPN		4
-#define UART0_PHYS_IO_BASE	0xf0000200
-#elif defined(CONFIG_440EP)
-#define UART0_PHYS_IO_BASE	0xe0000000
-#else
-#define UART0_PHYS_ERPN		1
-#define UART0_PHYS_IO_BASE	0x40000200
-#endif
-
-/*
- * XXX This 36-bit trap stuff will move somewhere in syslib/
- * when we rework/abstract the PPC44x PCI-X handling -mdp
- */
-
-/*
- * Standard 4GB "page" definitions
- */
-#if defined(CONFIG_440SP)
-#define	PPC44x_IO_PAGE		0x0000000100000000ULL
-#define	PPC44x_PCICFG_PAGE	0x0000000900000000ULL
-#define	PPC44x_PCIIO_PAGE	PPC44x_PCICFG_PAGE
-#define	PPC44x_PCIMEM_PAGE	0x0000000a00000000ULL
-#elif defined(CONFIG_440SPE)
-#define	PPC44x_IO_PAGE		0x0000000400000000ULL
-#define	PPC44x_PCICFG_PAGE	0x0000000c00000000ULL
-#define	PPC44x_PCIIO_PAGE	PPC44x_PCICFG_PAGE
-#define	PPC44x_PCIMEM_PAGE	0x0000000d00000000ULL
-#elif defined(CONFIG_440EP)
-#define PPC44x_IO_PAGE		0x0000000000000000ULL
-#define PPC44x_PCICFG_PAGE	0x0000000000000000ULL
-#define PPC44x_PCIIO_PAGE	PPC44x_PCICFG_PAGE
-#define PPC44x_PCIMEM_PAGE	0x0000000000000000ULL
-#else
-#define	PPC44x_IO_PAGE		0x0000000100000000ULL
-#define	PPC44x_PCICFG_PAGE	0x0000000200000000ULL
-#define	PPC44x_PCIIO_PAGE	PPC44x_PCICFG_PAGE
-#define	PPC44x_PCIMEM_PAGE	0x0000000300000000ULL
-#endif
-
-/*
- * 36-bit trap ranges
- */
-#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
-#define PPC44x_IO_LO		0xf0000000UL
-#define PPC44x_IO_HI		0xf0000fffUL
-#define PPC44x_PCI0CFG_LO	0x0ec00000UL
-#define PPC44x_PCI0CFG_HI	0x0ec00007UL
-#define PPC44x_PCI1CFG_LO	0x1ec00000UL
-#define PPC44x_PCI1CFG_HI	0x1ec00007UL
-#define PPC44x_PCI2CFG_LO	0x2ec00000UL
-#define PPC44x_PCI2CFG_HI	0x2ec00007UL
-#define PPC44x_PCIMEM_LO	0x80000000UL
-#define PPC44x_PCIMEM_HI	0xdfffffffUL
-#elif defined(CONFIG_440EP)
-#define PPC44x_IO_LO		0xef500000UL
-#define PPC44x_IO_HI		0xefffffffUL
-#define PPC44x_PCI0CFG_LO	0xeec00000UL
-#define PPC44x_PCI0CFG_HI	0xeecfffffUL
-#define PPC44x_PCIMEM_LO	0xa0000000UL
-#define PPC44x_PCIMEM_HI	0xdfffffffUL
-#else
-#define PPC44x_IO_LO		0x40000000UL
-#define PPC44x_IO_HI		0x40000fffUL
-#define PPC44x_PCI0CFG_LO	0x0ec00000UL
-#define PPC44x_PCI0CFG_HI	0x0ec00007UL
-#define PPC44x_PCIMEM_LO	0x80002000UL
-#define PPC44x_PCIMEM_HI	0xffffffffUL
-#endif
-
-/*
- * The "residual" board information structure the boot loader passes
- * into the kernel.
- */
-#ifndef __ASSEMBLY__
-
-/*
- * DCRN definitions
- */
-
-
-/* CPRs (440GX and 440SP/440SPe) */
-#define DCRN_CPR_CONFIG_ADDR	0xc
-#define DCRN_CPR_CONFIG_DATA	0xd
-
-#define DCRN_CPR_CLKUPD		0x0020
-#define DCRN_CPR_PLLC		0x0040
-#define DCRN_CPR_PLLD		0x0060
-#define DCRN_CPR_PRIMAD		0x0080
-#define DCRN_CPR_PRIMBD		0x00a0
-#define DCRN_CPR_OPBD		0x00c0
-#define DCRN_CPR_PERD		0x00e0
-#define DCRN_CPR_MALD		0x0100
-
-/* CPRs read/write helper macros */
-#define CPR_READ(offset) ({\
-	mtdcr(DCRN_CPR_CONFIG_ADDR, offset); \
-	mfdcr(DCRN_CPR_CONFIG_DATA);})
-#define CPR_WRITE(offset, data) ({\
-	mtdcr(DCRN_CPR_CONFIG_ADDR, offset); \
-	mtdcr(DCRN_CPR_CONFIG_DATA, data);})
-
-/* SDRs (440GX and 440SP/440SPe) */
-#define DCRN_SDR_CONFIG_ADDR 	0xe
-#define DCRN_SDR_CONFIG_DATA	0xf
-#define DCRN_SDR_PFC0		0x4100
-#define DCRN_SDR_PFC1		0x4101
-#define DCRN_SDR_PFC1_EPS	0x1c00000
-#define DCRN_SDR_PFC1_EPS_SHIFT	22
-#define DCRN_SDR_PFC1_RMII	0x02000000
-#define DCRN_SDR_MFR		0x4300
-#define DCRN_SDR_MFR_TAH0 	0x80000000  	/* TAHOE0 Enable */
-#define DCRN_SDR_MFR_TAH1 	0x40000000  	/* TAHOE1 Enable */
-#define DCRN_SDR_MFR_PCM  	0x10000000  	/* PPC440GP irq compat mode */
-#define DCRN_SDR_MFR_ECS  	0x08000000  	/* EMAC int clk */
-#define DCRN_SDR_MFR_T0TXFL	0x00080000
-#define DCRN_SDR_MFR_T0TXFH	0x00040000
-#define DCRN_SDR_MFR_T1TXFL	0x00020000
-#define DCRN_SDR_MFR_T1TXFH	0x00010000
-#define DCRN_SDR_MFR_E0TXFL	0x00008000
-#define DCRN_SDR_MFR_E0TXFH	0x00004000
-#define DCRN_SDR_MFR_E0RXFL	0x00002000
-#define DCRN_SDR_MFR_E0RXFH	0x00001000
-#define DCRN_SDR_MFR_E1TXFL	0x00000800
-#define DCRN_SDR_MFR_E1TXFH	0x00000400
-#define DCRN_SDR_MFR_E1RXFL	0x00000200
-#define DCRN_SDR_MFR_E1RXFH	0x00000100
-#define DCRN_SDR_MFR_E2TXFL	0x00000080
-#define DCRN_SDR_MFR_E2TXFH	0x00000040
-#define DCRN_SDR_MFR_E2RXFL	0x00000020
-#define DCRN_SDR_MFR_E2RXFH	0x00000010
-#define DCRN_SDR_MFR_E3TXFL	0x00000008
-#define DCRN_SDR_MFR_E3TXFH	0x00000004
-#define DCRN_SDR_MFR_E3RXFL	0x00000002
-#define DCRN_SDR_MFR_E3RXFH	0x00000001
-#define DCRN_SDR_UART0		0x0120
-#define DCRN_SDR_UART1		0x0121
-
-#ifdef CONFIG_440EP
-#define DCRN_SDR_UART2		0x0122
-#define DCRN_SDR_UART3		0x0123
-#define DCRN_SDR_CUST0		0x4000
-#endif
-
-/* SDR read/write helper macros */
-#define SDR_READ(offset) ({\
-	mtdcr(DCRN_SDR_CONFIG_ADDR, offset); \
-	mfdcr(DCRN_SDR_CONFIG_DATA);})
-#define SDR_WRITE(offset, data) ({\
-	mtdcr(DCRN_SDR_CONFIG_ADDR, offset); \
-	mtdcr(DCRN_SDR_CONFIG_DATA,data);})
-
-/* DMA (excluding 440SP/440SPe) */
-#define DCRN_DMA0_BASE		0x100
-#define DCRN_DMA1_BASE		0x108
-#define DCRN_DMA2_BASE		0x110
-#define DCRN_DMA3_BASE		0x118
-#define DCRN_DMASR_BASE		0x120
-#define DCRNCAP_DMA_SG		1	/* have DMA scatter/gather capability */
-#define DCRN_MAL_BASE		0x180
-
-#ifdef CONFIG_440EP
-#define DCRN_DMA2P40_BASE	0x300
-#define DCRN_DMA2P41_BASE	0x308
-#define DCRN_DMA2P42_BASE	0x310
-#define DCRN_DMA2P43_BASE	0x318
-#define DCRN_DMA2P4SR_BASE	0x320
-#endif
-
-/* UIC */
-#define DCRN_UIC0_BASE	0xc0
-#define DCRN_UIC1_BASE	0xd0
-#define UIC0		DCRN_UIC0_BASE
-#define UIC1		DCRN_UIC1_BASE
-
-#ifdef CONFIG_440SPE
-#define DCRN_UIC2_BASE	0xe0
-#define DCRN_UIC3_BASE	0xf0
-#define UIC2		DCRN_UIC2_BASE
-#define UIC3		DCRN_UIC3_BASE
-#else
-#define DCRN_UIC2_BASE	0x210
-#define DCRN_UICB_BASE	0x200
-#define UIC2		DCRN_UIC2_BASE
-#define UICB		DCRN_UICB_BASE
-#endif
-
-#define DCRN_UIC_SR(base)       (base + 0x0)
-#define DCRN_UIC_ER(base)       (base + 0x2)
-#define DCRN_UIC_CR(base)       (base + 0x3)
-#define DCRN_UIC_PR(base)       (base + 0x4)
-#define DCRN_UIC_TR(base)       (base + 0x5)
-#define DCRN_UIC_MSR(base)      (base + 0x6)
-#define DCRN_UIC_VR(base)       (base + 0x7)
-#define DCRN_UIC_VCR(base)      (base + 0x8)
-
-#define UIC0_UIC1NC      	0x00000002
-
-#ifdef CONFIG_440SPE
-#define UIC0_UIC1NC      0x00000002
-#define UIC0_UIC2NC      0x00200000
-#define UIC0_UIC3NC      0x00008000
-#endif
-
-#define UICB_UIC0NC		0x40000000
-#define UICB_UIC1NC		0x10000000
-#define UICB_UIC2NC		0x04000000
-
-/* 440 MAL DCRs */
-#define DCRN_MALCR(base)		(base + 0x0)	/* Configuration */
-#define DCRN_MALESR(base)		(base + 0x1)	/* Error Status */
-#define DCRN_MALIER(base)		(base + 0x2)	/* Interrupt Enable */
-#define DCRN_MALTXCASR(base)		(base + 0x4)	/* Tx Channel Active Set */
-#define DCRN_MALTXCARR(base)		(base + 0x5)	/* Tx Channel Active Reset */
-#define DCRN_MALTXEOBISR(base)		(base + 0x6)	/* Tx End of Buffer Interrupt Status */
-#define DCRN_MALTXDEIR(base)		(base + 0x7)	/* Tx Descriptor Error Interrupt */
-#define DCRN_MALRXCASR(base)		(base + 0x10)	/* Rx Channel Active Set */
-#define DCRN_MALRXCARR(base)		(base + 0x11)	/* Rx Channel Active Reset */
-#define DCRN_MALRXEOBISR(base)		(base + 0x12)	/* Rx End of Buffer Interrupt Status */
-#define DCRN_MALRXDEIR(base)		(base + 0x13)	/* Rx Descriptor Error Interrupt */
-#define DCRN_MALTXCTP0R(base)		(base + 0x20)	/* Channel Tx 0 Channel Table Pointer */
-#define DCRN_MALTXCTP1R(base)		(base + 0x21)	/* Channel Tx 1 Channel Table Pointer */
-#define DCRN_MALTXCTP2R(base)		(base + 0x22)	/* Channel Tx 2 Channel Table Pointer */
-#define DCRN_MALTXCTP3R(base)		(base + 0x23)	/* Channel Tx 3 Channel Table Pointer */
-#define DCRN_MALRXCTP0R(base)		(base + 0x40)	/* Channel Rx 0 Channel Table Pointer */
-#define DCRN_MALRXCTP1R(base)		(base + 0x41)	/* Channel Rx 1 Channel Table Pointer */
-#define DCRN_MALRCBS0(base)		(base + 0x60)	/* Channel Rx 0 Channel Buffer Size */
-#define DCRN_MALRCBS1(base)		(base + 0x61)	/* Channel Rx 1 Channel Buffer Size */
-
-/* Compatibility DCRN's */
-#define DCRN_MALRXCTP2R(base)	((base) + 0x42)	/* Channel Rx 2 Channel Table Pointer */
-#define DCRN_MALRXCTP3R(base)	((base) + 0x43)	/* Channel Rx 3 Channel Table Pointer */
-#define DCRN_MALTXCTP4R(base)	((base) + 0x24)	/* Channel Tx 4 Channel Table Pointer */
-#define DCRN_MALTXCTP5R(base)	((base) + 0x25)	/* Channel Tx 5 Channel Table Pointer */
-#define DCRN_MALTXCTP6R(base)	((base) + 0x26)	/* Channel Tx 6 Channel Table Pointer */
-#define DCRN_MALTXCTP7R(base)	((base) + 0x27)	/* Channel Tx 7 Channel Table Pointer */
-#define DCRN_MALRCBS2(base)	((base) + 0x62)	/* Channel Rx 2 Channel Buffer Size */
-#define DCRN_MALRCBS3(base)	((base) + 0x63)	/* Channel Rx 3 Channel Buffer Size */
-
-#define MALCR_MMSR		0x80000000	/* MAL Software reset */
-#define MALCR_PLBP_1		0x00400000	/* MAL reqest priority: */
-#define MALCR_PLBP_2		0x00800000	/* lowsest is 00 */
-#define MALCR_PLBP_3		0x00C00000	/* highest */
-#define MALCR_GA		0x00200000	/* Guarded Active Bit */
-#define MALCR_OA		0x00100000	/* Ordered Active Bit */
-#define MALCR_PLBLE		0x00080000	/* PLB Lock Error Bit */
-#define MALCR_PLBLT_1		0x00040000	/* PLB Latency Timer */
-#define MALCR_PLBLT_2 		0x00020000
-#define MALCR_PLBLT_3		0x00010000
-#define MALCR_PLBLT_4		0x00008000
-#ifdef CONFIG_440GP
-#define MALCR_PLBLT_DEFAULT	0x00330000	/* PLB Latency Timer default */
-#else
-#define MALCR_PLBLT_DEFAULT	0x00ff0000	/* PLB Latency Timer default */
-#endif
-#define MALCR_PLBB		0x00004000	/* PLB Burst Deactivation Bit */
-#define MALCR_OPBBL		0x00000080	/* OPB Lock Bit */
-#define MALCR_EOPIE		0x00000004	/* End Of Packet Interrupt Enable */
-#define MALCR_LEA		0x00000002	/* Locked Error Active */
-#define MALCR_MSD		0x00000001	/* MAL Scroll Descriptor Bit */
-/* DCRN_MALESR */
-#define MALESR_EVB		0x80000000	/* Error Valid Bit */
-#define MALESR_CIDRX		0x40000000	/* Channel ID Receive */
-#define MALESR_DE		0x00100000	/* Descriptor Error */
-#define MALESR_OEN		0x00080000	/* OPB Non-Fullword Error */
-#define MALESR_OTE		0x00040000	/* OPB Timeout Error */
-#define MALESR_OSE		0x00020000	/* OPB Slave Error */
-#define MALESR_PEIN		0x00010000	/* PLB Bus Error Indication */
-#define MALESR_DEI		0x00000010	/* Descriptor Error Interrupt */
-#define MALESR_ONEI		0x00000008	/* OPB Non-Fullword Error Interrupt */
-#define MALESR_OTEI		0x00000004	/* OPB Timeout Error Interrupt */
-#define MALESR_OSEI		0x00000002	/* OPB Slace Error Interrupt */
-#define MALESR_PBEI		0x00000001	/* PLB Bus Error Interrupt */
-/* DCRN_MALIER */
-#define MALIER_DE		0x00000010	/* Descriptor Error Interrupt Enable */
-#define MALIER_NE		0x00000008	/* OPB Non-word Transfer Int Enable */
-#define MALIER_TE		0x00000004	/* OPB Time Out Error Interrupt Enable */
-#define MALIER_OPBE		0x00000002	/* OPB Slave Error Interrupt Enable */
-#define MALIER_PLBE		0x00000001	/* PLB Error Interrupt Enable */
-/* DCRN_MALTXEOBISR */
-#define MALOBISR_CH0		0x80000000	/* EOB channel 1 bit */
-#define MALOBISR_CH2		0x40000000	/* EOB channel 2 bit */
-
-#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
-/* 440SP/440SPe PLB Arbiter DCRs */
-#define DCRN_PLB_REVID	       0x080		/* PLB Revision ID */
-#define DCRN_PLB_CCR	       0x088		/* PLB Crossbar Control */
-
-#define DCRN_PLB0_ACR	       0x081		/* PLB Arbiter Control */
-#define DCRN_PLB0_BESRL	       0x082		/* PLB Error Status */
-#define DCRN_PLB0_BESRH	       0x083		/* PLB Error Status */
-#define DCRN_PLB0_BEARL	       0x084		/* PLB Error Address Low */
-#define DCRN_PLB0_BEARH	       0x085		/* PLB Error Address High */
-
-#define DCRN_PLB1_ACR		0x089		/* PLB Arbiter Control */
-#define DCRN_PLB1_BESRL		0x08a		/* PLB Error Status */
-#define DCRN_PLB1_BESRH		0x08b		/* PLB Error Status */
-#define DCRN_PLB1_BEARL		0x08c		/* PLB Error Address Low */
-#define DCRN_PLB1_BEARH		0x08d		/* PLB Error Address High */
-#else
-/* 440GP/GX PLB Arbiter DCRs */
-#define DCRN_PLB0_REVID		0x082		/* PLB Arbiter Revision ID */
-#define DCRN_PLB0_ACR		0x083		/* PLB Arbiter Control */
-#define DCRN_PLB0_BESR		0x084		/* PLB Error Status */
-#define DCRN_PLB0_BEARL		0x086		/* PLB Error Address Low */
-#define DCRN_PLB0_BEAR		DCRN_PLB0_BEARL	/* 40x compatibility */
-#define DCRN_PLB0_BEARH		0x087		/* PLB Error Address High */
-#endif
-
-/* 440GP/GX PLB to OPB bridge DCRs */
-#define DCRN_POB0_BESR0		0x090
-#define DCRN_POB0_BESR1		0x094
-#define DCRN_POB0_BEARL		0x092
-#define DCRN_POB0_BEARH		0x093
-
-/* 440GP/GX OPB to PLB bridge DCRs */
-#define DCRN_OPB0_BSTAT		0x0a9
-#define DCRN_OPB0_BEARL		0x0aa
-#define DCRN_OPB0_BEARH		0x0ab
-
-/* 440GP Clock, PM, chip control */
-#define DCRN_CPC0_SR		0x0b0
-#define DCRN_CPC0_ER		0x0b1
-#define DCRN_CPC0_FR		0x0b2
-#define DCRN_CPC0_SYS0		0x0e0
-#define DCRN_CPC0_SYS1		0x0e1
-#define DCRN_CPC0_CUST0		0x0e2
-#define DCRN_CPC0_CUST1		0x0e3
-#define DCRN_CPC0_STRP0		0x0e4
-#define DCRN_CPC0_STRP1		0x0e5
-#define DCRN_CPC0_STRP2		0x0e6
-#define DCRN_CPC0_STRP3		0x0e7
-#define DCRN_CPC0_GPIO		0x0e8
-#define DCRN_CPC0_PLB		0x0e9
-#define DCRN_CPC0_CR1		0x0ea
-#define DCRN_CPC0_CR0		0x0eb
-#define DCRN_CPC0_MIRQ0		0x0ec
-#define DCRN_CPC0_MIRQ1		0x0ed
-#define DCRN_CPC0_JTAGID	0x0ef
-
-/* 440GP DMA controller DCRs */
-#define DCRN_DMACR0	(DCRN_DMA0_BASE + 0x0)	/* DMA Channel Control 0 */
-#define DCRN_DMACT0	(DCRN_DMA0_BASE + 0x1)  /* DMA Count 0 */
-#define DCRN_DMASAH0	(DCRN_DMA0_BASE + 0x2)	/* DMA Src Addr High 0 */
-#define DCRN_DMASA0	(DCRN_DMA0_BASE + 0x3)	/* DMA Src Addr Low 0 */
-#define DCRN_DMADAH0	(DCRN_DMA0_BASE + 0x4)	/* DMA Dest Addr High 0 */
-#define DCRN_DMADA0	(DCRN_DMA0_BASE + 0x5)	/* DMA Dest Addr Low 0 */
-#define DCRN_ASGH0	(DCRN_DMA0_BASE + 0x6)	/* DMA SG Desc Addr High 0 */
-#define DCRN_ASG0	(DCRN_DMA0_BASE + 0x7)	/* DMA SG Desc Addr Low 0 */
-
-#define DCRN_DMACR1	(DCRN_DMA1_BASE + 0x0)	/* DMA Channel Control 1 */
-#define DCRN_DMACT1	(DCRN_DMA1_BASE + 0x1)  /* DMA Count 1 */
-#define DCRN_DMASAH1	(DCRN_DMA1_BASE + 0x2)	/* DMA Src Addr High 1 */
-#define DCRN_DMASA1	(DCRN_DMA1_BASE + 0x3)	/* DMA Src Addr Low 1 */
-#define DCRN_DMADAH1	(DCRN_DMA1_BASE + 0x4)	/* DMA Dest Addr High 1 */
-#define DCRN_DMADA1	(DCRN_DMA1_BASE + 0x5)	/* DMA Dest Addr Low 1 */
-#define DCRN_ASGH1	(DCRN_DMA1_BASE + 0x6)	/* DMA SG Desc Addr High 1 */
-#define DCRN_ASG1	(DCRN_DMA1_BASE + 0x7)	/* DMA SG Desc Addr Low 1 */
-
-#define DCRN_DMACR2	(DCRN_DMA2_BASE + 0x0)	/* DMA Channel Control 2 */
-#define DCRN_DMACT2	(DCRN_DMA2_BASE + 0x1)  /* DMA Count 2 */
-#define DCRN_DMASAH2	(DCRN_DMA2_BASE + 0x2)	/* DMA Src Addr High 2 */
-#define DCRN_DMASA2	(DCRN_DMA2_BASE + 0x3)	/* DMA Src Addr Low 2 */
-#define DCRN_DMADAH2	(DCRN_DMA2_BASE + 0x4)	/* DMA Dest Addr High 2 */
-#define DCRN_DMADA2	(DCRN_DMA2_BASE + 0x5)	/* DMA Dest Addr Low 2 */
-#define DCRN_ASGH2	(DCRN_DMA2_BASE + 0x6)	/* DMA SG Desc Addr High 2 */
-#define DCRN_ASG2	(DCRN_DMA2_BASE + 0x7)	/* DMA SG Desc Addr Low 2 */
-
-#define DCRN_DMACR3	(DCRN_DMA3_BASE + 0x0)	/* DMA Channel Control 3 */
-#define DCRN_DMACT3	(DCRN_DMA3_BASE + 0x1)  /* DMA Count 3 */
-#define DCRN_DMASAH3	(DCRN_DMA3_BASE + 0x2)	/* DMA Src Addr High 3 */
-#define DCRN_DMASA3	(DCRN_DMA3_BASE + 0x3)	/* DMA Src Addr Low 3 */
-#define DCRN_DMADAH3	(DCRN_DMA3_BASE + 0x4)	/* DMA Dest Addr High 3 */
-#define DCRN_DMADA3	(DCRN_DMA3_BASE + 0x5)	/* DMA Dest Addr Low 3 */
-#define DCRN_ASGH3	(DCRN_DMA3_BASE + 0x6)	/* DMA SG Desc Addr High 3 */
-#define DCRN_ASG3	(DCRN_DMA3_BASE + 0x7)	/* DMA SG Desc Addr Low 3 */
-
-#define DCRN_DMASR	(DCRN_DMASR_BASE + 0x0)	/* DMA Status Register */
-#define DCRN_ASGC	(DCRN_DMASR_BASE + 0x3)	/* DMA Scatter/Gather Command */
-#define DCRN_SLP	(DCRN_DMASR_BASE + 0x5)	/* DMA Sleep Register */
-#define DCRN_POL	(DCRN_DMASR_BASE + 0x6)	/* DMA Polarity Register */
-
-/* 440GP/440GX SDRAM controller DCRs */
-#define DCRN_SDRAM0_CFGADDR		0x010
-#define DCRN_SDRAM0_CFGDATA		0x011
-
-#define SDRAM0_B0CR	0x40
-#define SDRAM0_B1CR	0x44
-#define SDRAM0_B2CR	0x48
-#define SDRAM0_B3CR	0x4c
-
-#define SDRAM_CONFIG_BANK_ENABLE	0x00000001
-#define SDRAM_CONFIG_SIZE_MASK		0x000e0000
-#define SDRAM_CONFIG_BANK_SIZE(reg)	((reg & SDRAM_CONFIG_SIZE_MASK) >> 17)
-#define SDRAM_CONFIG_SIZE_8M		0x00000001
-#define SDRAM_CONFIG_SIZE_16M		0x00000002
-#define SDRAM_CONFIG_SIZE_32M		0x00000003
-#define SDRAM_CONFIG_SIZE_64M		0x00000004
-#define SDRAM_CONFIG_SIZE_128M		0x00000005
-#define SDRAM_CONFIG_SIZE_256M		0x00000006
-#define SDRAM_CONFIG_SIZE_512M		0x00000007
-#define PPC44x_MEM_SIZE_8M		0x00800000
-#define PPC44x_MEM_SIZE_16M		0x01000000
-#define PPC44x_MEM_SIZE_32M		0x02000000
-#define PPC44x_MEM_SIZE_64M		0x04000000
-#define PPC44x_MEM_SIZE_128M		0x08000000
-#define PPC44x_MEM_SIZE_256M		0x10000000
-#define PPC44x_MEM_SIZE_512M		0x20000000
-#define PPC44x_MEM_SIZE_1G		0x40000000
-#define PPC44x_MEM_SIZE_2G		0x80000000
-
-/* 440SP/440SPe memory controller DCRs */
-#define DCRN_MQ0_BS0BAS			0x40
-#if defined(CONFIG_440SP)
-#define MQ0_NUM_BANKS			2
-#elif defined(CONFIG_440SPE)
-#define MQ0_NUM_BANKS			4
-#endif
-
-#define MQ0_CONFIG_SIZE_MASK		0x0000fff0
-#define MQ0_CONFIG_SIZE_8M		0x0000ffc0
-#define MQ0_CONFIG_SIZE_16M		0x0000ff80
-#define MQ0_CONFIG_SIZE_32M		0x0000ff00
-#define MQ0_CONFIG_SIZE_64M		0x0000fe00
-#define MQ0_CONFIG_SIZE_128M		0x0000fc00
-#define MQ0_CONFIG_SIZE_256M		0x0000f800
-#define MQ0_CONFIG_SIZE_512M		0x0000f000
-#define MQ0_CONFIG_SIZE_1G		0x0000e000
-#define MQ0_CONFIG_SIZE_2G		0x0000c000
-#define MQ0_CONFIG_SIZE_4G		0x00008000
-
-/* Internal SRAM Controller 440GX/440SP/440SPe */
-#define DCRN_SRAM0_BASE		0x000
-
-#define DCRN_SRAM0_SB0CR	(DCRN_SRAM0_BASE + 0x020)
-#define DCRN_SRAM0_SB1CR	(DCRN_SRAM0_BASE + 0x021)
-#define DCRN_SRAM0_SB2CR	(DCRN_SRAM0_BASE + 0x022)
-#define DCRN_SRAM0_SB3CR	(DCRN_SRAM0_BASE + 0x023)
-#define  SRAM_SBCR_BAS0		0x80000000
-#define  SRAM_SBCR_BAS1		0x80010000
-#define  SRAM_SBCR_BAS2		0x80020000
-#define  SRAM_SBCR_BAS3		0x80030000
-#define  SRAM_SBCR_BU_MASK	0x00000180
-#define  SRAM_SBCR_BS_64KB	0x00000800
-#define  SRAM_SBCR_BU_RO	0x00000080
-#define  SRAM_SBCR_BU_RW	0x00000180
-#define DCRN_SRAM0_BEAR		(DCRN_SRAM0_BASE + 0x024)
-#define DCRN_SRAM0_BESR0	(DCRN_SRAM0_BASE + 0x025)
-#define DCRN_SRAM0_BESR1	(DCRN_SRAM0_BASE + 0x026)
-#define DCRN_SRAM0_PMEG		(DCRN_SRAM0_BASE + 0x027)
-#define DCRN_SRAM0_CID		(DCRN_SRAM0_BASE + 0x028)
-#define DCRN_SRAM0_REVID	(DCRN_SRAM0_BASE + 0x029)
-#define DCRN_SRAM0_DPC		(DCRN_SRAM0_BASE + 0x02a)
-#define  SRAM_DPC_ENABLE	0x80000000
-
-/* L2 Cache Controller 440GX/440SP/440SPe */
-#define DCRN_L2C0_CFG		0x030
-#define  L2C_CFG_L2M		0x80000000
-#define  L2C_CFG_ICU		0x40000000
-#define  L2C_CFG_DCU		0x20000000
-#define  L2C_CFG_DCW_MASK	0x1e000000
-#define  L2C_CFG_TPC		0x01000000
-#define  L2C_CFG_CPC		0x00800000
-#define  L2C_CFG_FRAN		0x00200000
-#define  L2C_CFG_SS_MASK	0x00180000
-#define  L2C_CFG_SS_256		0x00000000
-#define  L2C_CFG_CPIM		0x00040000
-#define  L2C_CFG_TPIM		0x00020000
-#define  L2C_CFG_LIM		0x00010000
-#define  L2C_CFG_PMUX_MASK	0x00007000
-#define  L2C_CFG_PMUX_SNP	0x00000000
-#define  L2C_CFG_PMUX_IF	0x00001000
-#define  L2C_CFG_PMUX_DF	0x00002000
-#define  L2C_CFG_PMUX_DS	0x00003000
-#define  L2C_CFG_PMIM		0x00000800
-#define  L2C_CFG_TPEI		0x00000400
-#define  L2C_CFG_CPEI		0x00000200
-#define  L2C_CFG_NAM		0x00000100
-#define  L2C_CFG_SMCM		0x00000080
-#define  L2C_CFG_NBRM		0x00000040
-#define DCRN_L2C0_CMD		0x031
-#define  L2C_CMD_CLR		0x80000000
-#define  L2C_CMD_DIAG		0x40000000
-#define  L2C_CMD_INV		0x20000000
-#define  L2C_CMD_CCP		0x10000000
-#define  L2C_CMD_CTE		0x08000000
-#define  L2C_CMD_STRC		0x04000000
-#define  L2C_CMD_STPC		0x02000000
-#define  L2C_CMD_RPMC		0x01000000
-#define  L2C_CMD_HCC		0x00800000
-#define DCRN_L2C0_ADDR		0x032
-#define DCRN_L2C0_DATA		0x033
-#define DCRN_L2C0_SR		0x034
-#define  L2C_SR_CC		0x80000000
-#define  L2C_SR_CPE		0x40000000
-#define  L2C_SR_TPE		0x20000000
-#define  L2C_SR_LRU		0x10000000
-#define  L2C_SR_PCS		0x08000000
-#define DCRN_L2C0_REVID		0x035
-#define DCRN_L2C0_SNP0		0x036
-#define DCRN_L2C0_SNP1		0x037
-#define  L2C_SNP_BA_MASK	0xffff0000
-#define  L2C_SNP_SSR_MASK	0x0000f000
-#define  L2C_SNP_SSR_32G	0x0000f000
-#define  L2C_SNP_ESR		0x00000800
-
-/*
- * PCI-X definitions
- */
-#define PCIX0_CFGA		0x0ec00000UL
-#define PCIX1_CFGA		0x1ec00000UL
-#define PCIX2_CFGA		0x2ec00000UL
-#define PCIX0_CFGD		0x0ec00004UL
-#define PCIX1_CFGD		0x1ec00004UL
-#define PCIX2_CFGD		0x2ec00004UL
-
-#define PCIX0_IO_BASE		0x0000000908000000ULL
-#define PCIX1_IO_BASE		0x0000000908000000ULL
-#define PCIX2_IO_BASE		0x0000000908000000ULL
-#define PCIX_IO_SIZE		0x00010000
-
-#ifdef CONFIG_440SP
-#define PCIX0_REG_BASE		0x000000090ec80000ULL
-#else
-#define PCIX0_REG_BASE		0x000000020ec80000ULL
-#endif
-#define PCIX_REG_OFFSET		0x10000000
-#define PCIX_REG_SIZE		0x200
-
-#define PCIX0_VENDID		0x000
-#define PCIX0_DEVID		0x002
-#define PCIX0_COMMAND		0x004
-#define PCIX0_STATUS		0x006
-#define PCIX0_REVID		0x008
-#define PCIX0_CLS		0x009
-#define PCIX0_CACHELS		0x00c
-#define PCIX0_LATTIM		0x00d
-#define PCIX0_HDTYPE		0x00e
-#define PCIX0_BIST		0x00f
-#define PCIX0_BAR0L		0x010
-#define PCIX0_BAR0H		0x014
-#define PCIX0_BAR1		0x018
-#define PCIX0_BAR2L		0x01c
-#define PCIX0_BAR2H		0x020
-#define PCIX0_BAR3		0x024
-#define PCIX0_CISPTR		0x028
-#define PCIX0_SBSYSVID		0x02c
-#define PCIX0_SBSYSID		0x02e
-#define PCIX0_EROMBA		0x030
-#define PCIX0_CAP		0x034
-#define PCIX0_RES0		0x035
-#define PCIX0_RES1		0x036
-#define PCIX0_RES2		0x038
-#define PCIX0_INTLN		0x03c
-#define PCIX0_INTPN		0x03d
-#define PCIX0_MINGNT		0x03e
-#define PCIX0_MAXLTNCY		0x03f
-#define PCIX0_BRDGOPT1		0x040
-#define PCIX0_BRDGOPT2		0x044
-#define PCIX0_ERREN		0x050
-#define PCIX0_ERRSTS		0x054
-#define PCIX0_PLBBESR		0x058
-#define PCIX0_PLBBEARL		0x05c
-#define PCIX0_PLBBEARH		0x060
-#define PCIX0_POM0LAL		0x068
-#define PCIX0_POM0LAH		0x06c
-#define PCIX0_POM0SA		0x070
-#define PCIX0_POM0PCIAL		0x074
-#define PCIX0_POM0PCIAH		0x078
-#define PCIX0_POM1LAL		0x07c
-#define PCIX0_POM1LAH		0x080
-#define PCIX0_POM1SA		0x084
-#define PCIX0_POM1PCIAL		0x088
-#define PCIX0_POM1PCIAH		0x08c
-#define PCIX0_POM2SA		0x090
-#define PCIX0_PIM0SAL		0x098
-#define PCIX0_PIM0SA		PCIX0_PIM0SAL
-#define PCIX0_PIM0LAL		0x09c
-#define PCIX0_PIM0LAH		0x0a0
-#define PCIX0_PIM1SA		0x0a4
-#define PCIX0_PIM1LAL		0x0a8
-#define PCIX0_PIM1LAH		0x0ac
-#define PCIX0_PIM2SAL		0x0b0
-#define PCIX0_PIM2SA		PCIX0_PIM2SAL
-#define PCIX0_PIM2LAL		0x0b4
-#define PCIX0_PIM2LAH		0x0b8
-#define PCIX0_OMCAPID		0x0c0
-#define PCIX0_OMNIPTR		0x0c1
-#define PCIX0_OMMC		0x0c2
-#define PCIX0_OMMA		0x0c4
-#define PCIX0_OMMUA		0x0c8
-#define PCIX0_OMMDATA		0x0cc
-#define PCIX0_OMMEOI		0x0ce
-#define PCIX0_PMCAPID		0x0d0
-#define PCIX0_PMNIPTR		0x0d1
-#define PCIX0_PMC		0x0d2
-#define PCIX0_PMCSR		0x0d4
-#define PCIX0_PMCSRBSE		0x0d6
-#define PCIX0_PMDATA		0x0d7
-#define PCIX0_PMSCRR		0x0d8
-#define PCIX0_CAPID		0x0dc
-#define PCIX0_NIPTR		0x0dd
-#define PCIX0_CMD		0x0de
-#define PCIX0_STS		0x0e0
-#define PCIX0_IDR		0x0e4
-#define PCIX0_CID		0x0e8
-#define PCIX0_RID		0x0ec
-#define PCIX0_PIM0SAH		0x0f8
-#define PCIX0_PIM2SAH		0x0fc
-#define PCIX0_MSGIL		0x100
-#define PCIX0_MSGIH		0x104
-#define PCIX0_MSGOL		0x108
-#define PCIX0_MSGOH		0x10c
-#define PCIX0_IM		0x1f8
-
-#define IIC_OWN			0x55
-#define IIC_CLOCK		50
-
-#undef NR_UICS
-#if defined(CONFIG_440GX)
-#define NR_UICS 3
-#elif defined(CONFIG_440SPE)
-#define NR_UICS 4
-#else
-#define NR_UICS 2
-#endif
-
-#include <asm/ibm4xx.h>
-
-#endif /* __ASSEMBLY__ */
-#endif /* __ASM_IBM44x_H__ */
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/ibm4xx.h b/include/asm-ppc/ibm4xx.h
deleted file mode 100644
index ed6891af05d..00000000000
--- a/include/asm-ppc/ibm4xx.h
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- *
- *    Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
- *
- *    Module name: ibm4xx.h
- *
- *    Description:
- *	A generic include file which pulls in appropriate include files
- *      for specific board types based on configuration settings.
- *
- */
-
-#ifdef __KERNEL__
-#ifndef __ASM_IBM4XX_H__
-#define __ASM_IBM4XX_H__
-
-#include <asm/types.h>
-#include <asm/dcr.h>
-
-#ifdef CONFIG_40x
-
-#if defined(CONFIG_BUBINGA)
-#include <platforms/4xx/bubinga.h>
-#endif
-
-#if defined(CONFIG_CPCI405)
-#include <platforms/4xx/cpci405.h>
-#endif
-
-#if defined(CONFIG_EP405)
-#include <platforms/4xx/ep405.h>
-#endif
-
-#if defined(CONFIG_REDWOOD_5)
-#include <platforms/4xx/redwood5.h>
-#endif
-
-#if defined(CONFIG_REDWOOD_6)
-#include <platforms/4xx/redwood6.h>
-#endif
-
-#if defined(CONFIG_SYCAMORE)
-#include <platforms/4xx/sycamore.h>
-#endif
-
-#if defined(CONFIG_WALNUT)
-#include <platforms/4xx/walnut.h>
-#endif
-
-#if defined(CONFIG_XILINX_VIRTEX)
-#include <platforms/4xx/virtex.h>
-#endif
-
-#ifndef __ASSEMBLY__
-
-#ifdef CONFIG_40x
-/*
- * The "residual" board information structure the boot loader passes
- * into the kernel.
- */
-extern bd_t __res;
-#endif
-
-void ppc4xx_setup_arch(void);
-void ppc4xx_map_io(void);
-void ppc4xx_init_IRQ(void);
-void ppc4xx_init(unsigned long r3, unsigned long r4, unsigned long r5,
-		 unsigned long r6, unsigned long r7);
-#endif
-
-#ifndef PPC4xx_MACHINE_NAME
-#define PPC4xx_MACHINE_NAME	"Unidentified 4xx class"
-#endif
-
-
-/* IO_BASE is for PCI I/O.
- * ISA not supported, just here to resolve copilation.
- */
-
-#ifndef _IO_BASE
-#define _IO_BASE	0xe8000000	/* The PCI address window */
-#define _ISA_MEM_BASE	0
-#define PCI_DRAM_OFFSET	0
-#endif
-
-#elif defined(CONFIG_44x)
-
-#if defined(CONFIG_BAMBOO)
-#include <platforms/4xx/bamboo.h>
-#endif
-
-#if defined(CONFIG_EBONY)
-#include <platforms/4xx/ebony.h>
-#endif
-
-#if defined(CONFIG_LUAN)
-#include <platforms/4xx/luan.h>
-#endif
-
-#if defined(CONFIG_YUCCA)
-#include <platforms/4xx/yucca.h>
-#endif
-
-#if defined(CONFIG_OCOTEA)
-#include <platforms/4xx/ocotea.h>
-#endif
-
-#if defined(CONFIG_TAISHAN)
-#include <platforms/4xx/taishan.h>
-#endif
-
-#ifndef __ASSEMBLY__
-#ifdef CONFIG_40x
-/*
- * The "residual" board information structure the boot loader passes
- * into the kernel.
- */
-extern bd_t __res;
-#endif
-#endif
-#endif /* CONFIG_40x */
-
-#endif /* __ASM_IBM4XX_H__ */
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/ibm_ocp.h b/include/asm-ppc/ibm_ocp.h
deleted file mode 100644
index ddce616f765..00000000000
--- a/include/asm-ppc/ibm_ocp.h
+++ /dev/null
@@ -1,204 +0,0 @@
-/*
- * ibm_ocp.h
- *
- *      (c) Benjamin Herrenschmidt (benh@kernel.crashing.org)
- *          Mipsys - France
- *
- *          Derived from work (c) Armin Kuster akuster@pacbell.net
- *
- *          Additional support and port to 2.6 LDM/sysfs by
- *          Matt Porter <mporter@kernel.crashing.org>
- *          Copyright 2003-2004 MontaVista Software, Inc.
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- *
- */
-#ifdef __KERNEL__
-#ifndef __IBM_OCP_H__
-#define __IBM_OCP_H__
-
-#include <asm/types.h>
-
-/*
- * IBM 4xx OCP system information
- */
-struct ocp_sys_info_data {
-	int	opb_bus_freq;	/* OPB Bus Frequency (Hz) */
-	int	ebc_bus_freq;	/* EBC Bus Frequency (Hz) */
-};
-
-extern struct ocp_sys_info_data ocp_sys_info;
-
-/*
- * EMAC additional data and sysfs support
- *
- * Note about mdio_idx: When you have a zmii, it's usually
- * not necessary, it covers the case of the 405EP which has
- * the MDIO lines on EMAC0 only
- *
- * Note about phy_map: Per EMAC map of PHY ids which should
- * be probed by emac_probe. Different EMACs can have
- * overlapping maps.
- *
- * Note, this map uses inverse logic for bits:
- *  0 - id should be probed
- *  1 - id should be ignored
- *
- * Default value of 0x00000000 - will result in usual
- * auto-detection logic.
- *
- */
-
-struct ocp_func_emac_data {
-	int	rgmii_idx;	/* RGMII device index or -1 */
-	int	rgmii_mux;	/* RGMII input of this EMAC */
-	int	zmii_idx;	/* ZMII device index or -1 */
-	int	zmii_mux;	/* ZMII input of this EMAC */
-	int	mal_idx;	/* MAL device index */
-	int	mal_rx_chan;	/* MAL rx channel number */
-	int	mal_tx_chan;	/* MAL tx channel number */
-	int	wol_irq;	/* WOL interrupt */
-	int	mdio_idx;	/* EMAC idx of MDIO master or -1 */
-	int	tah_idx;	/* TAH device index or -1 */
-	int	phy_mode;	/* PHY type or configurable mode */
-	u8	mac_addr[6];	/* EMAC mac address */
-	u32	phy_map;	/* EMAC phy map */
-	u32	phy_feat_exc;	/* Excluded PHY features */
-};
-
-/* Sysfs support */
-#define OCP_SYSFS_EMAC_DATA()						\
-OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, rgmii_idx)	\
-OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, rgmii_mux)	\
-OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, zmii_idx)	\
-OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, zmii_mux)	\
-OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mal_idx)	\
-OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mal_rx_chan)	\
-OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mal_tx_chan)	\
-OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, wol_irq)	\
-OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mdio_idx)	\
-OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, tah_idx)	\
-OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, phy_mode)	\
-OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "0x%08x\n", emac, phy_map)	\
-OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "0x%08x\n", emac, phy_feat_exc)\
-									\
-void ocp_show_emac_data(struct device *dev)				\
-{									\
-	device_create_file(dev, &dev_attr_emac_rgmii_idx);		\
-	device_create_file(dev, &dev_attr_emac_rgmii_mux);		\
-	device_create_file(dev, &dev_attr_emac_zmii_idx);		\
-	device_create_file(dev, &dev_attr_emac_zmii_mux);		\
-	device_create_file(dev, &dev_attr_emac_mal_idx);		\
-	device_create_file(dev, &dev_attr_emac_mal_rx_chan);		\
-	device_create_file(dev, &dev_attr_emac_mal_tx_chan);		\
-	device_create_file(dev, &dev_attr_emac_wol_irq);		\
-	device_create_file(dev, &dev_attr_emac_mdio_idx);		\
-	device_create_file(dev, &dev_attr_emac_tah_idx);		\
-	device_create_file(dev, &dev_attr_emac_phy_mode);		\
-	device_create_file(dev, &dev_attr_emac_phy_map);		\
-	device_create_file(dev, &dev_attr_emac_phy_feat_exc);		\
-}
-
-/*
- * PHY mode settings (EMAC <-> ZMII/RGMII bridge <-> PHY)
- */
-#define PHY_MODE_NA	0
-#define PHY_MODE_MII	1
-#define PHY_MODE_RMII	2
-#define PHY_MODE_SMII	3
-#define PHY_MODE_RGMII	4
-#define PHY_MODE_TBI	5
-#define PHY_MODE_GMII	6
-#define PHY_MODE_RTBI	7
-#define PHY_MODE_SGMII	8
-
-#ifdef CONFIG_40x
-/*
- * Helper function to copy MAC addresses from the bd_t to OCP EMAC
- * additions.
- *
- * The range of EMAC indices (inclusive) to be copied are the arguments.
- */
-static inline void ibm_ocp_set_emac(int start, int end)
-{
-	int i;
-	struct ocp_def *def;
-
-	/* Copy MAC addresses to EMAC additions */
-	for (i=start; i<=end; i++) {
-		def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, i);
-		if (i == 0)
-			memcpy(((struct ocp_func_emac_data *)def->additions)->mac_addr,
-			       __res.bi_enetaddr, 6);
-#if defined(CONFIG_405EP) || defined(CONFIG_44x)
-		else if (i == 1)
-			memcpy(((struct ocp_func_emac_data *)def->additions)->mac_addr,
-			       __res.bi_enet1addr, 6);
-#endif
-#if defined(CONFIG_440GX)
-		else if (i == 2)
-			memcpy(((struct ocp_func_emac_data *)def->additions)->mac_addr,
-			       __res.bi_enet2addr, 6);
-		else if (i == 3)
-			memcpy(((struct ocp_func_emac_data *)def->additions)->mac_addr,
-			       __res.bi_enet3addr, 6);
-#endif
-	}
-}
-#endif
-
-/*
- * MAL additional data and sysfs support
- */
-struct ocp_func_mal_data {
-	int	num_tx_chans;	/* Number of TX channels */
-	int	num_rx_chans;	/* Number of RX channels */
-	int 	txeob_irq;	/* TX End Of Buffer IRQ  */
-	int 	rxeob_irq;	/* RX End Of Buffer IRQ  */
-	int	txde_irq;	/* TX Descriptor Error IRQ */
-	int	rxde_irq;	/* RX Descriptor Error IRQ */
-	int	serr_irq;	/* MAL System Error IRQ    */
-	int	dcr_base;	/* MALx_CFG DCR number   */
-};
-
-#define OCP_SYSFS_MAL_DATA()						\
-OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, num_tx_chans)	\
-OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, num_rx_chans)	\
-OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, txeob_irq)	\
-OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, rxeob_irq)	\
-OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, txde_irq)	\
-OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, rxde_irq)	\
-OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, serr_irq)	\
-OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, dcr_base)	\
-									\
-void ocp_show_mal_data(struct device *dev)				\
-{									\
-	device_create_file(dev, &dev_attr_mal_num_tx_chans);		\
-	device_create_file(dev, &dev_attr_mal_num_rx_chans);		\
-	device_create_file(dev, &dev_attr_mal_txeob_irq);		\
-	device_create_file(dev, &dev_attr_mal_rxeob_irq);		\
-	device_create_file(dev, &dev_attr_mal_txde_irq);		\
-	device_create_file(dev, &dev_attr_mal_rxde_irq);		\
-	device_create_file(dev, &dev_attr_mal_serr_irq);		\
-	device_create_file(dev, &dev_attr_mal_dcr_base);		\
-}
-
-/*
- * IIC additional data and sysfs support
- */
-struct ocp_func_iic_data {
-	int	fast_mode;	/* IIC fast mode enabled */
-};
-
-#define OCP_SYSFS_IIC_DATA()						\
-OCP_SYSFS_ADDTL(struct ocp_func_iic_data, "%d\n", iic, fast_mode)	\
-									\
-void ocp_show_iic_data(struct device *dev)				\
-{									\
-	device_create_file(dev, &dev_attr_iic_fast_mode);		\
-}
-#endif /* __IBM_OCP_H__ */
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/ibm_ocp_pci.h b/include/asm-ppc/ibm_ocp_pci.h
deleted file mode 100644
index a81ab614435..00000000000
--- a/include/asm-ppc/ibm_ocp_pci.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * Author: Armin Kuster <akuster@mvista.com>
- *
- * 2001-2002 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#ifdef __KERNEL__
-#ifndef __ASM_IBM_OCP_PCI_H__
-#define __ASM_IBM_OCP_PCI_H__
-
-/* PCI 32 */
-
-struct pmm_regs {
-	u32 la;
-	u32 ma;
-	u32 pcila;
-	u32 pciha;
-};
-
-typedef struct pcil0_regs {
-	struct pmm_regs pmm[3];
-	u32 ptm1ms;
-	u32 ptm1la;
-	u32 ptm2ms;
-	u32 ptm2la;
-} pci0_t;
-
-#endif				/* __ASM_IBM_OCP_PCI_H__ */
-#endif				/* __KERNEL__ */
diff --git a/include/asm-ppc/immap_cpm2.h b/include/asm-ppc/immap_cpm2.h
deleted file mode 100644
index 3c23d9cb47a..00000000000
--- a/include/asm-ppc/immap_cpm2.h
+++ /dev/null
@@ -1,648 +0,0 @@
-/*
- * CPM2 Internal Memory Map
- * Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
- *
- * The Internal Memory Map for devices with CPM2 on them.  This
- * is the superset of all CPM2 devices (8260, 8266, 8280, 8272,
- * 8560). 
- */
-#ifdef __KERNEL__
-#ifndef __IMMAP_CPM2__
-#define __IMMAP_CPM2__
-
-/* System configuration registers.
-*/
-typedef	struct sys_82xx_conf {
-	u32	sc_siumcr;
-	u32	sc_sypcr;
-	u8	res1[6];
-	u16	sc_swsr;
-	u8	res2[20];
-	u32	sc_bcr;
-	u8	sc_ppc_acr;
-	u8	res3[3];
-	u32	sc_ppc_alrh;
-	u32	sc_ppc_alrl;
-	u8	sc_lcl_acr;
-	u8	res4[3];
-	u32	sc_lcl_alrh;
-	u32	sc_lcl_alrl;
-	u32	sc_tescr1;
-	u32	sc_tescr2;
-	u32	sc_ltescr1;
-	u32	sc_ltescr2;
-	u32	sc_pdtea;
-	u8	sc_pdtem;
-	u8	res5[3];
-	u32	sc_ldtea;
-	u8	sc_ldtem;
-	u8	res6[163];
-} sysconf_82xx_cpm2_t;
-
-typedef	struct sys_85xx_conf {
-	u32	sc_cear;
-	u16	sc_ceer;
-	u16	sc_cemr;
-	u8	res1[70];
-	u32	sc_smaer;
-	u8	res2[4];
-	u32	sc_smevr;
-	u32	sc_smctr;
-	u32	sc_lmaer;
-	u8	res3[4];
-	u32	sc_lmevr;
-	u32	sc_lmctr;
-	u8	res4[144];
-} sysconf_85xx_cpm2_t;
-
-typedef union sys_conf {
-	sysconf_82xx_cpm2_t	siu_82xx;
-	sysconf_85xx_cpm2_t	siu_85xx;
-} sysconf_cpm2_t;
-
-
-
-/* Memory controller registers.
-*/
-typedef struct	mem_ctlr {
-	u32	memc_br0;
-	u32	memc_or0;
-	u32	memc_br1;
-	u32	memc_or1;
-	u32	memc_br2;
-	u32	memc_or2;
-	u32	memc_br3;
-	u32	memc_or3;
-	u32	memc_br4;
-	u32	memc_or4;
-	u32	memc_br5;
-	u32	memc_or5;
-	u32	memc_br6;
-	u32	memc_or6;
-	u32	memc_br7;
-	u32	memc_or7;
-	u32	memc_br8;
-	u32	memc_or8;
-	u32	memc_br9;
-	u32	memc_or9;
-	u32	memc_br10;
-	u32	memc_or10;
-	u32	memc_br11;
-	u32	memc_or11;
-	u8	res1[8];
-	u32	memc_mar;
-	u8	res2[4];
-	u32	memc_mamr;
-	u32	memc_mbmr;
-	u32	memc_mcmr;
-	u8	res3[8];
-	u16	memc_mptpr;
-	u8	res4[2];
-	u32	memc_mdr;
-	u8	res5[4];
-	u32	memc_psdmr;
-	u32	memc_lsdmr;
-	u8	memc_purt;
-	u8	res6[3];
-	u8	memc_psrt;
-	u8	res7[3];
-	u8	memc_lurt;
-	u8	res8[3];
-	u8	memc_lsrt;
-	u8	res9[3];
-	u32	memc_immr;
-	u32	memc_pcibr0;
-	u32	memc_pcibr1;
-	u8	res10[16];
-	u32	memc_pcimsk0;
-	u32	memc_pcimsk1;
-	u8	res11[52];
-} memctl_cpm2_t;
-
-/* System Integration Timers.
-*/
-typedef struct	sys_int_timers {
-	u8	res1[32];
-	u16	sit_tmcntsc;
-	u8	res2[2];
-	u32	sit_tmcnt;
-	u8	res3[4];
-	u32	sit_tmcntal;
-	u8	res4[16];
-	u16	sit_piscr;
-	u8	res5[2];
-	u32	sit_pitc;
-	u32	sit_pitr;
-	u8      res6[94];
-	u8	res7[390];
-} sit_cpm2_t;
-
-#define PISCR_PIRQ_MASK		((u16)0xff00)
-#define PISCR_PS		((u16)0x0080)
-#define PISCR_PIE		((u16)0x0004)
-#define PISCR_PTF		((u16)0x0002)
-#define PISCR_PTE		((u16)0x0001)
-
-/* PCI Controller.
-*/
-typedef struct pci_ctlr {
-	u32	pci_omisr;
-	u32	pci_omimr;
-	u8	res1[8];
-	u32	pci_ifqpr;
-	u32	pci_ofqpr;
-	u8	res2[8];
-	u32	pci_imr0;
-	u32	pci_imr1;
-	u32	pci_omr0;
-	u32	pci_omr1;
-	u32	pci_odr;
-	u8	res3[4];
-	u32	pci_idr;
-	u8	res4[20];
-	u32	pci_imisr;
-	u32	pci_imimr;
-	u8	res5[24];
-	u32	pci_ifhpr;
-	u8	res6[4];
-	u32	pci_iftpr;
-	u8	res7[4];
-	u32	pci_iphpr;
-	u8	res8[4];
-	u32	pci_iptpr;
-	u8	res9[4];
-	u32	pci_ofhpr;
-	u8	res10[4];
-	u32	pci_oftpr;
-	u8	res11[4];
-	u32	pci_ophpr;
-	u8	res12[4];
-	u32	pci_optpr;
-	u8	res13[8];
-	u32	pci_mucr;
-	u8	res14[8];
-	u32	pci_qbar;
-	u8	res15[12];
-	u32	pci_dmamr0;
-	u32	pci_dmasr0;
-	u32	pci_dmacdar0;
-	u8	res16[4];
-	u32	pci_dmasar0;
-	u8	res17[4];
-	u32	pci_dmadar0;
-	u8	res18[4];
-	u32	pci_dmabcr0;
-	u32	pci_dmandar0;
-	u8	res19[86];
-	u32	pci_dmamr1;
-	u32	pci_dmasr1;
-	u32	pci_dmacdar1;
-	u8	res20[4];
-	u32	pci_dmasar1;
-	u8	res21[4];
-	u32	pci_dmadar1;
-	u8	res22[4];
-	u32	pci_dmabcr1;
-	u32	pci_dmandar1;
-	u8	res23[88];
-	u32	pci_dmamr2;
-	u32	pci_dmasr2;
-	u32	pci_dmacdar2;
-	u8	res24[4];
-	u32	pci_dmasar2;
-	u8	res25[4];
-	u32	pci_dmadar2;
-	u8	res26[4];
-	u32	pci_dmabcr2;
-	u32	pci_dmandar2;
-	u8	res27[88];
-	u32	pci_dmamr3;
-	u32	pci_dmasr3;
-	u32	pci_dmacdar3;
-	u8	res28[4];
-	u32	pci_dmasar3;
-	u8	res29[4];
-	u32	pci_dmadar3;
-	u8	res30[4];
-	u32	pci_dmabcr3;
-	u32	pci_dmandar3;
-	u8	res31[344];
-	u32	pci_potar0;
-	u8	res32[4];
-	u32	pci_pobar0;
-	u8	res33[4];
-	u32	pci_pocmr0;
-	u8	res34[4];
-	u32	pci_potar1;
-	u8	res35[4];
-	u32	pci_pobar1;
-	u8	res36[4];
-	u32	pci_pocmr1;
-	u8	res37[4];
-	u32	pci_potar2;
-	u8	res38[4];
-	u32	pci_pobar2;
-	u8	res39[4];
-	u32	pci_pocmr2;
-	u8	res40[50];
-	u32	pci_ptcr;
-	u32	pci_gpcr;
-	u32	pci_gcr;
-	u32	pci_esr;
-	u32	pci_emr;
-	u32	pci_ecr;
-	u32	pci_eacr;
-	u8	res41[4];
-	u32	pci_edcr;
-	u8	res42[4];
-	u32	pci_eccr;
-	u8	res43[44];
-	u32	pci_pitar1;
-	u8	res44[4];
-	u32	pci_pibar1;
-	u8	res45[4];
-	u32	pci_picmr1;
-	u8	res46[4];
-	u32	pci_pitar0;
-	u8	res47[4];
-	u32	pci_pibar0;
-	u8	res48[4];
-	u32	pci_picmr0;
-	u8	res49[4];
-	u32	pci_cfg_addr;
-	u32	pci_cfg_data;
-	u32	pci_int_ack;
-	u8	res50[756];
-} pci_cpm2_t;
-
-/* Interrupt Controller.
-*/
-typedef struct interrupt_controller {
-	u16	ic_sicr;
-	u8	res1[2];
-	u32	ic_sivec;
-	u32	ic_sipnrh;
-	u32	ic_sipnrl;
-	u32	ic_siprr;
-	u32	ic_scprrh;
-	u32	ic_scprrl;
-	u32	ic_simrh;
-	u32	ic_simrl;
-	u32	ic_siexr;
-	u8	res2[88];
-} intctl_cpm2_t;
-
-/* Clocks and Reset.
-*/
-typedef struct clk_and_reset {
-	u32	car_sccr;
-	u8	res1[4];
-	u32	car_scmr;
-	u8	res2[4];
-	u32	car_rsr;
-	u32	car_rmr;
-	u8	res[104];
-} car_cpm2_t;
-
-/* Input/Output Port control/status registers.
- * Names consistent with processor manual, although they are different
- * from the original 8xx names.......
- */
-typedef struct io_port {
-	u32	iop_pdira;
-	u32	iop_ppara;
-	u32	iop_psora;
-	u32	iop_podra;
-	u32	iop_pdata;
-	u8	res1[12];
-	u32	iop_pdirb;
-	u32	iop_pparb;
-	u32	iop_psorb;
-	u32	iop_podrb;
-	u32	iop_pdatb;
-	u8	res2[12];
-	u32	iop_pdirc;
-	u32	iop_pparc;
-	u32	iop_psorc;
-	u32	iop_podrc;
-	u32	iop_pdatc;
-	u8	res3[12];
-	u32	iop_pdird;
-	u32	iop_ppard;
-	u32	iop_psord;
-	u32	iop_podrd;
-	u32	iop_pdatd;
-	u8	res4[12];
-} iop_cpm2_t;
-
-/* Communication Processor Module Timers
-*/
-typedef struct cpm_timers {
-	u8	cpmt_tgcr1;
-	u8	res1[3];
-	u8	cpmt_tgcr2;
-	u8	res2[11];
-	u16	cpmt_tmr1;
-	u16	cpmt_tmr2;
-	u16	cpmt_trr1;
-	u16	cpmt_trr2;
-	u16	cpmt_tcr1;
-	u16	cpmt_tcr2;
-	u16	cpmt_tcn1;
-	u16	cpmt_tcn2;
-	u16	cpmt_tmr3;
-	u16	cpmt_tmr4;
-	u16	cpmt_trr3;
-	u16	cpmt_trr4;
-	u16	cpmt_tcr3;
-	u16	cpmt_tcr4;
-	u16	cpmt_tcn3;
-	u16	cpmt_tcn4;
-	u16	cpmt_ter1;
-	u16	cpmt_ter2;
-	u16	cpmt_ter3;
-	u16	cpmt_ter4;
-	u8	res3[584];
-} cpmtimer_cpm2_t;
-
-/* DMA control/status registers.
-*/
-typedef struct sdma_csr {
-	u8	res0[24];
-	u8	sdma_sdsr;
-	u8	res1[3];
-	u8	sdma_sdmr;
-	u8	res2[3];
-	u8	sdma_idsr1;
-	u8	res3[3];
-	u8	sdma_idmr1;
-	u8	res4[3];
-	u8	sdma_idsr2;
-	u8	res5[3];
-	u8	sdma_idmr2;
-	u8	res6[3];
-	u8	sdma_idsr3;
-	u8	res7[3];
-	u8	sdma_idmr3;
-	u8	res8[3];
-	u8	sdma_idsr4;
-	u8	res9[3];
-	u8	sdma_idmr4;
-	u8	res10[707];
-} sdma_cpm2_t;
-
-/* Fast controllers
-*/
-typedef struct fcc {
-	u32	fcc_gfmr;
-	u32	fcc_fpsmr;
-	u16	fcc_ftodr;
-	u8	res1[2];
-	u16	fcc_fdsr;
-	u8	res2[2];
-	u16	fcc_fcce;
-	u8	res3[2];
-	u16	fcc_fccm;
-	u8	res4[2];
-	u8	fcc_fccs;
-	u8	res5[3];
-	u8	fcc_ftirr_phy[4];
-} fcc_t;
-
-/* Fast controllers continued
- */
-typedef struct fcc_c {
-	u32	fcc_firper;
-	u32	fcc_firer;
-	u32	fcc_firsr_hi;
-	u32	fcc_firsr_lo;
-	u8	fcc_gfemr;
-	u8	res1[15];
-} fcc_c_t;
-
-/* TC Layer
- */
-typedef struct tclayer {
-	u16	tc_tcmode;
-	u16	tc_cdsmr;
-	u16	tc_tcer;
-	u16	tc_rcc;
-	u16	tc_tcmr;
-	u16	tc_fcc;
-	u16	tc_ccc;
-	u16	tc_icc;
-	u16	tc_tcc;
-	u16	tc_ecc;
-	u8	res1[12];
-} tclayer_t;
-
-
-/* I2C
-*/
-typedef struct i2c {
-	u8	i2c_i2mod;
-	u8	res1[3];
-	u8	i2c_i2add;
-	u8	res2[3];
-	u8	i2c_i2brg;
-	u8	res3[3];
-	u8	i2c_i2com;
-	u8	res4[3];
-	u8	i2c_i2cer;
-	u8	res5[3];
-	u8	i2c_i2cmr;
-	u8	res6[331];
-} i2c_cpm2_t;
-
-typedef struct scc {		/* Serial communication channels */
-	u32	scc_gsmrl;
-	u32	scc_gsmrh;
-	u16	scc_psmr;
-	u8	res1[2];
-	u16	scc_todr;
-	u16	scc_dsr;
-	u16	scc_scce;
-	u8	res2[2];
-	u16	scc_sccm;
-	u8	res3;
-	u8	scc_sccs;
-	u8	res4[8];
-} scc_t;
-
-typedef struct smc {		/* Serial management channels */
-	u8	res1[2];
-	u16	smc_smcmr;
-	u8	res2[2];
-	u8	smc_smce;
-	u8	res3[3];
-	u8	smc_smcm;
-	u8	res4[5];
-} smc_t;
-
-/* Serial Peripheral Interface.
-*/
-typedef struct spi_ctrl {
-	u16	spi_spmode;
-	u8	res1[4];
-	u8	spi_spie;
-	u8	res2[3];
-	u8	spi_spim;
-	u8	res3[2];
-	u8	spi_spcom;
-	u8	res4[82];
-} spictl_cpm2_t;
-
-/* CPM Mux.
-*/
-typedef struct cpmux {
-	u8	cmx_si1cr;
-	u8	res1;
-	u8	cmx_si2cr;
-	u8	res2;
-	u32	cmx_fcr;
-	u32	cmx_scr;
-	u8	cmx_smr;
-	u8	res3;
-	u16	cmx_uar;
-	u8	res4[16];
-} cpmux_t;
-
-/* SIRAM control
-*/
-typedef struct siram {
-	u16	si_amr;
-	u16	si_bmr;
-	u16	si_cmr;
-	u16	si_dmr;
-	u8	si_gmr;
-	u8	res1;
-	u8	si_cmdr;
-	u8	res2;
-	u8	si_str;
-	u8	res3;
-	u16	si_rsr;
-} siramctl_t;
-
-typedef struct mcc {
-	u16	mcc_mcce;
-	u8	res1[2];
-	u16	mcc_mccm;
-	u8	res2[2];
-	u8	mcc_mccf;
-	u8	res3[7];
-} mcc_t;
-
-typedef struct comm_proc {
-	u32	cp_cpcr;
-	u32	cp_rccr;
-	u8	res1[14];
-	u16	cp_rter;
-	u8	res2[2];
-	u16	cp_rtmr;
-	u16	cp_rtscr;
-	u8	res3[2];
-	u32	cp_rtsr;
-	u8	res4[12];
-} cpm_cpm2_t;
-
-/* USB Controller.
-*/
-typedef struct usb_ctlr {
-	u8	usb_usmod;
-	u8	usb_usadr;
-	u8	usb_uscom;
-	u8	res1[1];
-	u16	usb_usep1;
-	u16	usb_usep2;
-	u16	usb_usep3;
-	u16	usb_usep4;
-	u8	res2[4];
-	u16	usb_usber;
-	u8	res3[2];
-	u16	usb_usbmr;
-	u8	usb_usbs;
-	u8	res4[7];
-} usb_cpm2_t;
-
-/* ...and the whole thing wrapped up....
-*/
-
-typedef struct immap {
-	/* Some references are into the unique and known dpram spaces,
-	 * others are from the generic base.
-	 */
-#define im_dprambase	im_dpram1
-	u8		im_dpram1[16*1024];
-	u8		res1[16*1024];
-	u8		im_dpram2[4*1024];
-	u8		res2[8*1024];
-	u8		im_dpram3[4*1024];
-	u8		res3[16*1024];
-
-	sysconf_cpm2_t	im_siu_conf;	/* SIU Configuration */
-	memctl_cpm2_t	im_memctl;	/* Memory Controller */
-	sit_cpm2_t	im_sit;		/* System Integration Timers */
-	pci_cpm2_t	im_pci;		/* PCI Controller */
-	intctl_cpm2_t	im_intctl;	/* Interrupt Controller */
-	car_cpm2_t	im_clkrst;	/* Clocks and reset */
-	iop_cpm2_t	im_ioport;	/* IO Port control/status */
-	cpmtimer_cpm2_t	im_cpmtimer;	/* CPM timers */
-	sdma_cpm2_t	im_sdma;	/* SDMA control/status */
-
-	fcc_t		im_fcc[3];	/* Three FCCs */
-	u8		res4z[32];
-	fcc_c_t		im_fcc_c[3];	/* Continued FCCs */
-
-	u8		res4[32];
-
-	tclayer_t	im_tclayer[8];	/* Eight TCLayers */
-	u16		tc_tcgsr;
-	u16		tc_tcger;
-	
-	/* First set of baud rate generators.
-	*/
-	u8		res[236];
-	u32		im_brgc5;
-	u32		im_brgc6;
-	u32		im_brgc7;
-	u32		im_brgc8;
-
-	u8		res5[608];
-
-	i2c_cpm2_t	im_i2c;		/* I2C control/status */
-	cpm_cpm2_t	im_cpm;		/* Communication processor */
-
-	/* Second set of baud rate generators.
-	*/
-	u32		im_brgc1;
-	u32		im_brgc2;
-	u32		im_brgc3;
-	u32		im_brgc4;
-
-	scc_t		im_scc[4];	/* Four SCCs */
-	smc_t		im_smc[2];	/* Couple of SMCs */
-	spictl_cpm2_t	im_spi;		/* A SPI */
-	cpmux_t		im_cpmux;	/* CPM clock route mux */
-	siramctl_t	im_siramctl1;	/* First SI RAM Control */
-	mcc_t		im_mcc1;	/* First MCC */
-	siramctl_t	im_siramctl2;	/* Second SI RAM Control */
-	mcc_t		im_mcc2;	/* Second MCC */
-	usb_cpm2_t	im_usb;		/* USB Controller */
-
-	u8		res6[1153];
-
-	u16		im_si1txram[256];
-	u8		res7[512];
-	u16		im_si1rxram[256];
-	u8		res8[512];
-	u16		im_si2txram[256];
-	u8		res9[512];
-	u16		im_si2rxram[256];
-	u8		res10[512];
-	u8		res11[4096];
-} cpm2_map_t;
-
-extern cpm2_map_t	*cpm2_immr;
-
-#endif /* __IMMAP_CPM2__ */
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/io.h b/include/asm-ppc/io.h
deleted file mode 100644
index a0d409a5d80..00000000000
--- a/include/asm-ppc/io.h
+++ /dev/null
@@ -1,502 +0,0 @@
-#ifdef __KERNEL__
-#ifndef _PPC_IO_H
-#define _PPC_IO_H
-
-#include <linux/string.h>
-#include <linux/types.h>
-
-#include <asm/page.h>
-#include <asm/byteorder.h>
-#include <asm/synch.h>
-#include <asm/mmu.h>
-
-#define SIO_CONFIG_RA	0x398
-#define SIO_CONFIG_RD	0x399
-
-#define SLOW_DOWN_IO
-
-#define PMAC_ISA_MEM_BASE 	0
-#define PMAC_PCI_DRAM_OFFSET 	0
-#define CHRP_ISA_IO_BASE 	0xf8000000
-#define CHRP_ISA_MEM_BASE 	0xf7000000
-#define CHRP_PCI_DRAM_OFFSET 	0
-#define PREP_ISA_IO_BASE 	0x80000000
-#define PREP_ISA_MEM_BASE 	0xc0000000
-#define PREP_PCI_DRAM_OFFSET 	0x80000000
-
-#if defined(CONFIG_4xx)
-#include <asm/ibm4xx.h>
-#elif defined(CONFIG_8xx)
-#include <asm/mpc8xx.h>
-#elif defined(CONFIG_8260)
-#include <asm/mpc8260.h>
-#elif !defined(CONFIG_PCI)
-#define _IO_BASE	0
-#define _ISA_MEM_BASE	0
-#define PCI_DRAM_OFFSET 0
-#else /* Everyone else */
-#define _IO_BASE	isa_io_base
-#define _ISA_MEM_BASE	isa_mem_base
-#define PCI_DRAM_OFFSET	pci_dram_offset
-#endif /* Platform-dependent I/O */
-
-#define ___IO_BASE ((void __iomem *)_IO_BASE)
-extern unsigned long isa_io_base;
-extern unsigned long isa_mem_base;
-extern unsigned long pci_dram_offset;
-
-/*
- * 8, 16 and 32 bit, big and little endian I/O operations, with barrier.
- *
- * Read operations have additional twi & isync to make sure the read
- * is actually performed (i.e. the data has come back) before we start
- * executing any following instructions.
- */
-extern inline int in_8(const volatile unsigned char __iomem *addr)
-{
-	int ret;
-
-	__asm__ __volatile__(
-		"sync; lbz%U1%X1 %0,%1;\n"
-		"twi 0,%0,0;\n"
-		"isync" : "=r" (ret) : "m" (*addr));
-	return ret;
-}
-
-extern inline void out_8(volatile unsigned char __iomem *addr, int val)
-{
-	__asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
-}
-
-extern inline int in_le16(const volatile unsigned short __iomem *addr)
-{
-	int ret;
-
-	__asm__ __volatile__("sync; lhbrx %0,0,%1;\n"
-			     "twi 0,%0,0;\n"
-			     "isync" : "=r" (ret) :
-			      "r" (addr), "m" (*addr));
-	return ret;
-}
-
-extern inline int in_be16(const volatile unsigned short __iomem *addr)
-{
-	int ret;
-
-	__asm__ __volatile__("sync; lhz%U1%X1 %0,%1;\n"
-			     "twi 0,%0,0;\n"
-			     "isync" : "=r" (ret) : "m" (*addr));
-	return ret;
-}
-
-extern inline void out_le16(volatile unsigned short __iomem *addr, int val)
-{
-	__asm__ __volatile__("sync; sthbrx %1,0,%2" : "=m" (*addr) :
-			      "r" (val), "r" (addr));
-}
-
-extern inline void out_be16(volatile unsigned short __iomem *addr, int val)
-{
-	__asm__ __volatile__("sync; sth%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
-}
-
-extern inline unsigned in_le32(const volatile unsigned __iomem *addr)
-{
-	unsigned ret;
-
-	__asm__ __volatile__("sync; lwbrx %0,0,%1;\n"
-			     "twi 0,%0,0;\n"
-			     "isync" : "=r" (ret) :
-			     "r" (addr), "m" (*addr));
-	return ret;
-}
-
-extern inline unsigned in_be32(const volatile unsigned __iomem *addr)
-{
-	unsigned ret;
-
-	__asm__ __volatile__("sync; lwz%U1%X1 %0,%1;\n"
-			     "twi 0,%0,0;\n"
-			     "isync" : "=r" (ret) : "m" (*addr));
-	return ret;
-}
-
-extern inline void out_le32(volatile unsigned __iomem *addr, int val)
-{
-	__asm__ __volatile__("sync; stwbrx %1,0,%2" : "=m" (*addr) :
-			     "r" (val), "r" (addr));
-}
-
-extern inline void out_be32(volatile unsigned __iomem *addr, int val)
-{
-	__asm__ __volatile__("sync; stw%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
-}
-#if defined (CONFIG_8260_PCI9)
-#define readb(addr) in_8((volatile u8 *)(addr))
-#define writeb(b,addr) out_8((volatile u8 *)(addr), (b))
-#else
-static inline __u8 readb(const volatile void __iomem *addr)
-{
-	return in_8(addr);
-}
-static inline void writeb(__u8 b, volatile void __iomem *addr)
-{
-	out_8(addr, b);
-}
-#endif
-
-#if defined (CONFIG_8260_PCI9)
-/* Use macros if PCI9 workaround enabled */
-#define readw(addr) in_le16((volatile u16 *)(addr))
-#define readl(addr) in_le32((volatile u32 *)(addr))
-#define writew(b,addr) out_le16((volatile u16 *)(addr),(b))
-#define writel(b,addr) out_le32((volatile u32 *)(addr),(b))
-#else
-static inline __u16 readw(const volatile void __iomem *addr)
-{
-	return in_le16(addr);
-}
-static inline __u32 readl(const volatile void __iomem *addr)
-{
-	return in_le32(addr);
-}
-static inline void writew(__u16 b, volatile void __iomem *addr)
-{
-	out_le16(addr, b);
-}
-static inline void writel(__u32 b, volatile void __iomem *addr)
-{
-	out_le32(addr, b);
-}
-#endif /* CONFIG_8260_PCI9 */
-
-#define readb_relaxed(addr) readb(addr)
-#define readw_relaxed(addr) readw(addr)
-#define readl_relaxed(addr) readl(addr)
-
-static inline __u8 __raw_readb(const volatile void __iomem *addr)
-{
-	return *(__force volatile __u8 *)(addr);
-}
-static inline __u16 __raw_readw(const volatile void __iomem *addr)
-{
-	return *(__force volatile __u16 *)(addr);
-}
-static inline __u32 __raw_readl(const volatile void __iomem *addr)
-{
-	return *(__force volatile __u32 *)(addr);
-}
-static inline void __raw_writeb(__u8 b, volatile void __iomem *addr)
-{
-	*(__force volatile __u8 *)(addr) = b;
-}
-static inline void __raw_writew(__u16 b, volatile void __iomem *addr)
-{
-	*(__force volatile __u16 *)(addr) = b;
-}
-static inline void __raw_writel(__u32 b, volatile void __iomem *addr)
-{
-	*(__force volatile __u32 *)(addr) = b;
-}
-
-#define mmiowb()
-
-/*
- * The insw/outsw/insl/outsl macros don't do byte-swapping.
- * They are only used in practice for transferring buffers which
- * are arrays of bytes, and byte-swapping is not appropriate in
- * that case.  - paulus
- */
-#define insb(port, buf, ns)	_insb((port)+___IO_BASE, (buf), (ns))
-#define outsb(port, buf, ns)	_outsb((port)+___IO_BASE, (buf), (ns))
-#define insw(port, buf, ns)	_insw_ns((port)+___IO_BASE, (buf), (ns))
-#define outsw(port, buf, ns)	_outsw_ns((port)+___IO_BASE, (buf), (ns))
-#define insl(port, buf, nl)	_insl_ns((port)+___IO_BASE, (buf), (nl))
-#define outsl(port, buf, nl)	_outsl_ns((port)+___IO_BASE, (buf), (nl))
-
-#define readsb(a, b, n)		_insb((a), (b), (n))
-#define readsw(a, b, n)		_insw_ns((a), (b), (n))
-#define readsl(a, b, n)		_insl_ns((a), (b), (n))
-#define writesb(a, b, n)	_outsb((a),(b),(n))
-#define writesw(a, b, n)	_outsw_ns((a),(b),(n))
-#define writesl(a, b, n)	_outsl_ns((a),(b),(n))
-
-
-/*
- * On powermacs and 8xx we will get a machine check exception 
- * if we try to read data from a non-existent I/O port. Because
- * the machine check is an asynchronous exception, it isn't
- * well-defined which instruction SRR0 will point to when the
- * exception occurs.
- * With the sequence below (twi; isync; nop), we have found that
- * the machine check occurs on one of the three instructions on
- * all PPC implementations tested so far.  The twi and isync are
- * needed on the 601 (in fact twi; sync works too), the isync and
- * nop are needed on 604[e|r], and any of twi, sync or isync will
- * work on 603[e], 750, 74xx.
- * The twi creates an explicit data dependency on the returned
- * value which seems to be needed to make the 601 wait for the
- * load to finish.
- */
-
-#define __do_in_asm(name, op)				\
-extern __inline__ unsigned int name(unsigned int port)	\
-{							\
-	unsigned int x;					\
-	__asm__ __volatile__(				\
-		"sync\n"				\
-		"0:"	op "	%0,0,%1\n"		\
-		"1:	twi	0,%0,0\n"		\
-		"2:	isync\n"			\
-		"3:	nop\n"				\
-		"4:\n"					\
-		".section .fixup,\"ax\"\n"		\
-		"5:	li	%0,-1\n"		\
-		"	b	4b\n"			\
-		".previous\n"				\
-		".section __ex_table,\"a\"\n"		\
-		"	.align	2\n"			\
-		"	.long	0b,5b\n"		\
-		"	.long	1b,5b\n"		\
-		"	.long	2b,5b\n"		\
-		"	.long	3b,5b\n"		\
-		".previous"				\
-		: "=&r" (x)				\
-		: "r" (port + ___IO_BASE));		\
-	return x;					\
-}
-
-#define __do_out_asm(name, op)				\
-extern __inline__ void name(unsigned int val, unsigned int port) \
-{							\
-	__asm__ __volatile__(				\
-		"sync\n"				\
-		"0:" op " %0,0,%1\n"			\
-		"1:	sync\n"				\
-		"2:\n"					\
-		".section __ex_table,\"a\"\n"		\
-		"	.align	2\n"			\
-		"	.long	0b,2b\n"		\
-		"	.long	1b,2b\n"		\
-		".previous"				\
-		: : "r" (val), "r" (port + ___IO_BASE));	\
-}
-
-__do_out_asm(outb, "stbx")
-#if defined (CONFIG_8260_PCI9)
-/* in asm cannot be defined if PCI9 workaround is used */
-#define inb(port)		in_8((port)+___IO_BASE)
-#define inw(port)		in_le16((port)+___IO_BASE)
-#define inl(port)		in_le32((port)+___IO_BASE)
-__do_out_asm(outw, "sthbrx")
-__do_out_asm(outl, "stwbrx")
-#else
-__do_in_asm(inb, "lbzx")
-__do_in_asm(inw, "lhbrx")
-__do_in_asm(inl, "lwbrx")
-__do_out_asm(outw, "sthbrx")
-__do_out_asm(outl, "stwbrx")
-
-#endif
-
-#define inb_p(port)		inb((port))
-#define outb_p(val, port)	outb((val), (port))
-#define inw_p(port)		inw((port))
-#define outw_p(val, port)	outw((val), (port))
-#define inl_p(port)		inl((port))
-#define outl_p(val, port)	outl((val), (port))
-
-extern void _insb(const volatile u8 __iomem *addr, void *buf, long count);
-extern void _outsb(volatile u8 __iomem *addr,const void *buf,long count);
-extern void _insw_ns(const volatile u16 __iomem *addr, void *buf, long count);
-extern void _outsw_ns(volatile u16 __iomem *addr, const void *buf, long count);
-extern void _insl_ns(const volatile u32 __iomem *addr, void *buf, long count);
-extern void _outsl_ns(volatile u32 __iomem *addr, const void *buf, long count);
-
-
-#define IO_SPACE_LIMIT ~0
-
-#if defined (CONFIG_8260_PCI9)
-#define memset_io(a,b,c)       memset((void *)(a),(b),(c))
-#define memcpy_fromio(a,b,c)   memcpy((a),(void *)(b),(c))
-#define memcpy_toio(a,b,c)     memcpy((void *)(a),(b),(c))
-#else
-static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count)
-{
-	memset((void __force *)addr, val, count);
-}
-static inline void memcpy_fromio(void *dst,const volatile void __iomem *src, int count)
-{
-	memcpy(dst, (void __force *) src, count);
-}
-static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count)
-{
-	memcpy((void __force *) dst, src, count);
-}
-#endif
-
-/*
- * Map in an area of physical address space, for accessing
- * I/O devices etc.
- */
-extern void __iomem *__ioremap(phys_addr_t address, unsigned long size,
-		       unsigned long flags);
-extern void __iomem *ioremap(phys_addr_t address, unsigned long size);
-#ifdef CONFIG_44x
-extern void __iomem *ioremap64(unsigned long long address, unsigned long size);
-#endif
-#define ioremap_nocache(addr, size)	ioremap((addr), (size))
-extern void iounmap(volatile void __iomem *addr);
-extern unsigned long iopa(unsigned long addr);
-extern void io_block_mapping(unsigned long virt, phys_addr_t phys,
-			     unsigned int size, int flags);
-
-/*
- * The PCI bus is inherently Little-Endian.  The PowerPC is being
- * run Big-Endian.  Thus all values which cross the [PCI] barrier
- * must be endian-adjusted.  Also, the local DRAM has a different
- * address from the PCI point of view, thus buffer addresses also
- * have to be modified [mapped] appropriately.
- */
-extern inline unsigned long virt_to_bus(volatile void * address)
-{
-        if (address == (void *)0)
-		return 0;
-        return (unsigned long)address - KERNELBASE + PCI_DRAM_OFFSET;
-}
-
-extern inline void * bus_to_virt(unsigned long address)
-{
-        if (address == 0)
-		return NULL;
-        return (void *)(address - PCI_DRAM_OFFSET + KERNELBASE);
-}
-
-/*
- * Change virtual addresses to physical addresses and vv, for
- * addresses in the area where the kernel has the RAM mapped.
- */
-extern inline unsigned long virt_to_phys(volatile void * address)
-{
-	return (unsigned long) address - KERNELBASE;
-}
-
-extern inline void * phys_to_virt(unsigned long address)
-{
-	return (void *) (address + KERNELBASE);
-}
-
-/*
- * Change "struct page" to physical address.
- */
-#define page_to_phys(page)	(page_to_pfn(page) << PAGE_SHIFT)
-#define page_to_bus(page)	(page_to_phys(page) + PCI_DRAM_OFFSET)
-
-/* Enforce in-order execution of data I/O.
- * No distinction between read/write on PPC; use eieio for all three.
- */
-#define iobarrier_rw() eieio()
-#define iobarrier_r()  eieio()
-#define iobarrier_w()  eieio()
-
-/*
- * Here comes the ppc implementation of the IOMAP 
- * interfaces.
- */
-static inline unsigned int ioread8(void __iomem *addr)
-{
-	return readb(addr);
-}
-
-static inline unsigned int ioread16(void __iomem *addr)
-{
-	return readw(addr);
-}
-
-static inline unsigned int ioread32(void __iomem *addr)
-{
-	return readl(addr);
-}
-
-static inline void iowrite8(u8 val, void __iomem *addr)
-{
-	writeb(val, addr);
-}
-
-static inline void iowrite16(u16 val, void __iomem *addr)
-{
-	writew(val, addr);
-}
-
-static inline void iowrite32(u32 val, void __iomem *addr)
-{
-	writel(val, addr);
-}
-
-static inline void ioread8_rep(void __iomem *addr, void *dst, unsigned long count)
-{
-	_insb(addr, dst, count);
-}
-
-static inline void ioread16_rep(void __iomem *addr, void *dst, unsigned long count)
-{
-	_insw_ns(addr, dst, count);
-}
-
-static inline void ioread32_rep(void __iomem *addr, void *dst, unsigned long count)
-{
-	_insl_ns(addr, dst, count);
-}
-
-static inline void iowrite8_rep(void __iomem *addr, const void *src, unsigned long count)
-{
-	_outsb(addr, src, count);
-}
-
-static inline void iowrite16_rep(void __iomem *addr, const void *src, unsigned long count)
-{
-	_outsw_ns(addr, src, count);
-}
-
-static inline void iowrite32_rep(void __iomem *addr, const void *src, unsigned long count)
-{
-	_outsl_ns(addr, src, count);
-}
-
-/* Create a virtual mapping cookie for an IO port range */
-extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
-extern void ioport_unmap(void __iomem *);
-
-/* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
-struct pci_dev;
-extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
-extern void pci_iounmap(struct pci_dev *dev, void __iomem *);
-
-#endif /* _PPC_IO_H */
-
-#ifdef CONFIG_8260_PCI9
-#include <asm/mpc8260_pci9.h>
-#endif
-
-/*
- * Convert a physical pointer to a virtual kernel pointer for /dev/mem
- * access
- */
-#define xlate_dev_mem_ptr(p)	__va(p)
-
-/*
- * Convert a virtual cached pointer to an uncached pointer
- */
-#define xlate_dev_kmem_ptr(p)	p
-
-/* access ports */
-#define setbits32(_addr, _v) out_be32((_addr), in_be32(_addr) |  (_v))
-#define clrbits32(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v))
-
-#define setbits16(_addr, _v) out_be16((_addr), in_be16(_addr) |  (_v))
-#define clrbits16(_addr, _v) out_be16((_addr), in_be16(_addr) & ~(_v))
-
-#define setbits8(_addr, _v) out_8((_addr), in_8(_addr) |  (_v))
-#define clrbits8(_addr, _v) out_8((_addr), in_8(_addr) & ~(_v))
-
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/irq_regs.h b/include/asm-ppc/irq_regs.h
deleted file mode 100644
index 3dd9c0b7027..00000000000
--- a/include/asm-ppc/irq_regs.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/irq_regs.h>
diff --git a/include/asm-ppc/kdebug.h b/include/asm-ppc/kdebug.h
deleted file mode 100644
index 6ece1b03766..00000000000
--- a/include/asm-ppc/kdebug.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/kdebug.h>
diff --git a/include/asm-ppc/kgdb.h b/include/asm-ppc/kgdb.h
deleted file mode 100644
index b617dac8296..00000000000
--- a/include/asm-ppc/kgdb.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * kgdb.h: Defines and declarations for serial line source level
- *         remote debugging of the Linux kernel using gdb.
- *
- * PPC Mods (C) 1998 Michael Tesch (tesch@cs.wisc.edu)
- *
- * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
- */
-#ifdef __KERNEL__
-#ifndef _PPC_KGDB_H
-#define _PPC_KGDB_H
-
-#ifndef __ASSEMBLY__
-
-/* Things specific to the gen550 backend. */
-struct uart_port;
-
-extern void gen550_progress(char *, unsigned short);
-extern void gen550_kgdb_map_scc(void);
-extern void gen550_init(int, struct uart_port *);
-
-/* Things specific to the pmac backend. */
-extern void zs_kgdb_hook(int tty_num);
-
-/* To init the kgdb engine. (called by serial hook)*/
-extern void set_debug_traps(void);
-
-/* To enter the debugger explicitly. */
-extern void breakpoint(void);
-
-/* For taking exceptions
- * these are defined in traps.c
- */
-extern int (*debugger)(struct pt_regs *regs);
-extern int (*debugger_bpt)(struct pt_regs *regs);
-extern int (*debugger_sstep)(struct pt_regs *regs);
-extern int (*debugger_iabr_match)(struct pt_regs *regs);
-extern int (*debugger_dabr_match)(struct pt_regs *regs);
-extern void (*debugger_fault_handler)(struct pt_regs *regs);
-
-/* What we bring to the party */
-int kgdb_bpt(struct pt_regs *regs);
-int kgdb_sstep(struct pt_regs *regs);
-void kgdb(struct pt_regs *regs);
-int kgdb_iabr_match(struct pt_regs *regs);
-int kgdb_dabr_match(struct pt_regs *regs);
-
-/*
- * external low-level support routines (ie macserial.c)
- */
-extern void kgdb_interruptible(int); /* control interrupts from serial */
-extern void putDebugChar(char);   /* write a single character      */
-extern char getDebugChar(void);   /* read and return a single char */
-
-#endif /* !(__ASSEMBLY__) */
-#endif /* !(_PPC_KGDB_H) */
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/m8260_pci.h b/include/asm-ppc/m8260_pci.h
deleted file mode 100644
index bf9e05dd54b..00000000000
--- a/include/asm-ppc/m8260_pci.h
+++ /dev/null
@@ -1,187 +0,0 @@
-/*
- * include/asm-ppc/m8260_pci.h
- *
- * Definitions for the MPC8250/MPC8265/MPC8266 integrated PCI host bridge.
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-
-#ifdef __KERNEL__
-#ifndef __M8260_PCI_H
-#define __M8260_PCI_H
-
-#include <linux/pci_ids.h>
-
-/*
- * Define the vendor/device ID for the MPC8265.
- */
-#define	PCI_DEVICE_ID_MPC8265	((0x18C0 << 16) | PCI_VENDOR_ID_MOTOROLA)
-#define	PCI_DEVICE_ID_MPC8272	((0x18C1 << 16) | PCI_VENDOR_ID_MOTOROLA)
-
-#define M8265_PCIBR0	0x101ac
-#define M8265_PCIBR1	0x101b0
-#define M8265_PCIMSK0	0x101c4
-#define M8265_PCIMSK1	0x101c8
-
-/* Bit definitions for PCIBR registers */
-
-#define PCIBR_ENABLE        0x00000001
-
-/* Bit definitions for PCIMSK registers */
-
-#define PCIMSK_32KiB         0xFFFF8000  /* Size of window, smallest */
-#define PCIMSK_64KiB         0xFFFF0000
-#define PCIMSK_128KiB        0xFFFE0000
-#define PCIMSK_256KiB        0xFFFC0000
-#define PCIMSK_512KiB        0xFFF80000
-#define PCIMSK_1MiB          0xFFF00000
-#define PCIMSK_2MiB          0xFFE00000
-#define PCIMSK_4MiB          0xFFC00000
-#define PCIMSK_8MiB          0xFF800000
-#define PCIMSK_16MiB         0xFF000000
-#define PCIMSK_32MiB         0xFE000000
-#define PCIMSK_64MiB         0xFC000000
-#define PCIMSK_128MiB        0xF8000000
-#define PCIMSK_256MiB        0xF0000000
-#define PCIMSK_512MiB        0xE0000000
-#define PCIMSK_1GiB          0xC0000000  /* Size of window, largest */
-
-
-#define M826X_SCCR_PCI_MODE_EN 0x100
-
-
-/*
- * Outbound ATU registers (3 sets). These registers control how 60x bus (local) 
- * addresses are translated to PCI addresses when the MPC826x is a PCI bus 
- * master (initiator).
- */
-
-#define POTAR_REG0          0x10800     /* PCI Outbound Translation Addr registers */
-#define POTAR_REG1          0x10818
-#define POTAR_REG2          0x10830
-
-#define POBAR_REG0          0x10808     /* PCI Outbound Base Addr registers */
-#define POBAR_REG1          0x10820
-#define POBAR_REG2          0x10838
-
-#define POCMR_REG0          0x10810     /* PCI Outbound Comparison Mask registers */
-#define POCMR_REG1          0x10828
-#define POCMR_REG2          0x10840
-
-/* Bit definitions for POMCR registers */
-
-#define POCMR_MASK_4KiB      0x000FFFFF
-#define POCMR_MASK_8KiB      0x000FFFFE
-#define POCMR_MASK_16KiB     0x000FFFFC
-#define POCMR_MASK_32KiB     0x000FFFF8
-#define POCMR_MASK_64KiB     0x000FFFF0
-#define POCMR_MASK_128KiB    0x000FFFE0
-#define POCMR_MASK_256KiB    0x000FFFC0
-#define POCMR_MASK_512KiB    0x000FFF80
-#define POCMR_MASK_1MiB      0x000FFF00
-#define POCMR_MASK_2MiB      0x000FFE00
-#define POCMR_MASK_4MiB      0x000FFC00
-#define POCMR_MASK_8MiB      0x000FF800
-#define POCMR_MASK_16MiB     0x000FF000
-#define POCMR_MASK_32MiB     0x000FE000
-#define POCMR_MASK_64MiB     0x000FC000
-#define POCMR_MASK_128MiB    0x000F8000
-#define POCMR_MASK_256MiB    0x000F0000
-#define POCMR_MASK_512MiB    0x000E0000
-#define POCMR_MASK_1GiB      0x000C0000
-
-#define POCMR_ENABLE        0x80000000
-#define POCMR_PCI_IO        0x40000000
-#define POCMR_PREFETCH_EN   0x20000000
-
-/* Soft PCI reset */
-
-#define PCI_GCR_REG         0x10880
-
-/* Bit definitions for PCI_GCR registers */
-
-#define PCIGCR_PCI_BUS_EN   0x1
-
-#define PCI_EMR_REG	    0x10888
-/*
- * Inbound ATU registers (2 sets). These registers control how PCI addresses 
- * are translated to 60x bus (local) addresses when the MPC826x is a PCI bus target.
- */
-
-#define PITAR_REG1          0x108D0
-#define PIBAR_REG1          0x108D8
-#define PICMR_REG1          0x108E0
-#define PITAR_REG0          0x108E8
-#define PIBAR_REG0          0x108F0
-#define PICMR_REG0          0x108F8
-
-/* Bit definitions for PCI Inbound Comparison Mask registers */
-
-#define PICMR_MASK_4KiB       0x000FFFFF
-#define PICMR_MASK_8KiB       0x000FFFFE
-#define PICMR_MASK_16KiB      0x000FFFFC
-#define PICMR_MASK_32KiB      0x000FFFF8
-#define PICMR_MASK_64KiB      0x000FFFF0
-#define PICMR_MASK_128KiB     0x000FFFE0
-#define PICMR_MASK_256KiB     0x000FFFC0
-#define PICMR_MASK_512KiB     0x000FFF80
-#define PICMR_MASK_1MiB       0x000FFF00
-#define PICMR_MASK_2MiB       0x000FFE00
-#define PICMR_MASK_4MiB       0x000FFC00
-#define PICMR_MASK_8MiB       0x000FF800
-#define PICMR_MASK_16MiB      0x000FF000
-#define PICMR_MASK_32MiB      0x000FE000
-#define PICMR_MASK_64MiB      0x000FC000
-#define PICMR_MASK_128MiB     0x000F8000
-#define PICMR_MASK_256MiB     0x000F0000
-#define PICMR_MASK_512MiB     0x000E0000
-#define PICMR_MASK_1GiB       0x000C0000
-
-#define PICMR_ENABLE         0x80000000
-#define PICMR_NO_SNOOP_EN    0x40000000
-#define PICMR_PREFETCH_EN    0x20000000
-
-/* PCI error Registers */
-
-#define	PCI_ERROR_STATUS_REG		0x10884
-#define	PCI_ERROR_MASK_REG		0x10888
-#define	PCI_ERROR_CONTROL_REG		0x1088C
-#define PCI_ERROR_ADRS_CAPTURE_REG      0x10890
-#define PCI_ERROR_DATA_CAPTURE_REG      0x10898
-#define PCI_ERROR_CTRL_CAPTURE_REG      0x108A0
-
-/* PCI error Register bit defines */
-
-#define	PCI_ERROR_PCI_ADDR_PAR			0x00000001
-#define	PCI_ERROR_PCI_DATA_PAR_WR		0x00000002
-#define	PCI_ERROR_PCI_DATA_PAR_RD		0x00000004
-#define	PCI_ERROR_PCI_NO_RSP			0x00000008
-#define	PCI_ERROR_PCI_TAR_ABT			0x00000010
-#define	PCI_ERROR_PCI_SERR			0x00000020
-#define	PCI_ERROR_PCI_PERR_RD			0x00000040
-#define	PCI_ERROR_PCI_PERR_WR			0x00000080
-#define	PCI_ERROR_I2O_OFQO			0x00000100
-#define	PCI_ERROR_I2O_IPQO			0x00000200
-#define	PCI_ERROR_IRA				0x00000400
-#define	PCI_ERROR_NMI				0x00000800
-#define	PCI_ERROR_I2O_DBMC			0x00001000
-
-/*
- * Register pair used to generate configuration cycles on the PCI bus
- * and access the MPC826x's own PCI configuration registers.
- */
-
-#define PCI_CFG_ADDR_REG     0x10900
-#define PCI_CFG_DATA_REG     0x10904
-
-/* Bus parking decides where the bus control sits when idle */
-/* If modifying memory controllers for PCI park on the core */
-
-#define PPC_ACR_BUS_PARK_CORE 0x6
-#define PPC_ACR_BUS_PARK_PCI  0x3
-
-#endif /* __M8260_PCI_H */
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/machdep.h b/include/asm-ppc/machdep.h
deleted file mode 100644
index a20b499b018..00000000000
--- a/include/asm-ppc/machdep.h
+++ /dev/null
@@ -1,178 +0,0 @@
-#ifdef __KERNEL__
-#ifndef _PPC_MACHDEP_H
-#define _PPC_MACHDEP_H
-
-#include <linux/init.h>
-#include <linux/kexec.h>
-
-#include <asm/setup.h>
-#include <asm/page.h>
-
-struct pt_regs;
-struct pci_bus;	
-struct pci_dev;
-struct seq_file;
-struct file;
-
-/*
- * This is for compatibility with ARCH=powerpc.
- */
-#define machine_is(x)	__MACHINE_IS_##x
-#define __MACHINE_IS_powermac	0
-#define __MACHINE_IS_chrp	0
-#ifdef CONFIG_PPC_PREP
-#define __MACHINE_IS_prep	1
-#else
-#define __MACHINE_IS_prep	0
-#endif
-
-/* We export this macro for external modules like Alsa to know if
- * ppc_md.feature_call is implemented or not
- */
-#define CONFIG_PPC_HAS_FEATURE_CALLS
-
-struct machdep_calls {
-	void		(*setup_arch)(void);
-	/* Optional, may be NULL. */
-	int		(*show_cpuinfo)(struct seq_file *m);
-	int		(*show_percpuinfo)(struct seq_file *m, int i);
-	/* Optional, may be NULL. */
-	unsigned int	(*irq_canonicalize)(unsigned int irq);
-	void		(*init_IRQ)(void);
-	int		(*get_irq)(void);
-	
-	/* A general init function, called by ppc_init in init/main.c.
-	   May be NULL. DEPRECATED ! */
-	void		(*init)(void);
-	/* For compatibility with merged platforms */
-	void		(*init_early)(void);
-
-	void		(*restart)(char *cmd);
-	void		(*power_off)(void);
-	void		(*halt)(void);
-
-	void		(*idle_loop)(void);
-	void		(*power_save)(void);
-
-	long		(*time_init)(void); /* Optional, may be NULL */
-	int		(*set_rtc_time)(unsigned long nowtime);
-	unsigned long	(*get_rtc_time)(void);
-	unsigned char 	(*rtc_read_val)(int addr);
-	void		(*rtc_write_val)(int addr, unsigned char val);
-	void		(*calibrate_decr)(void);
-
-	void		(*heartbeat)(void);
-	unsigned long	heartbeat_reset;
-	unsigned long	heartbeat_count;
-
-	unsigned long	(*find_end_of_memory)(void);
-	void		(*setup_io_mappings)(void);
-
-	void		(*early_serial_map)(void);
-  	void		(*progress)(char *, unsigned short);
-	void		(*kgdb_map_scc)(void);
-
-	unsigned char 	(*nvram_read_val)(int addr);
-	void		(*nvram_write_val)(int addr, unsigned char val);
-	void		(*nvram_sync)(void);
-
-	/*
-	 * optional PCI "hooks"
-	 */
-
-	/* Called after scanning the bus, before allocating resources */
-	void (*pcibios_fixup)(void);
-
-	/* Called after PPC generic resource fixup to perform
-	   machine specific fixups */
-	void (*pcibios_fixup_resources)(struct pci_dev *);
-
-	/* Called for each PCI bus in the system when it's probed */
-	void (*pcibios_fixup_bus)(struct pci_bus *);
-
-	/* Called when pci_enable_device() is called (initial=0) or
-	 * when a device with no assigned resource is found (initial=1).
-	 * Returns 0 to allow assignment/enabling of the device. */
-	int  (*pcibios_enable_device_hook)(struct pci_dev *, int initial);
-
-	/* For interrupt routing */
-	unsigned char (*pci_swizzle)(struct pci_dev *, unsigned char *);
-	int (*pci_map_irq)(struct pci_dev *, unsigned char, unsigned char);
-
-	/* Called in indirect_* to avoid touching devices */
-	int (*pci_exclude_device)(unsigned char, unsigned char);
-
-	/* Called at then very end of pcibios_init() */
-	void (*pcibios_after_init)(void);
-
-	/* Get access protection for /dev/mem */
-	pgprot_t	(*phys_mem_access_prot)(struct file *file,
-						unsigned long pfn,
-						unsigned long size,
-						pgprot_t vma_prot);
-
-	/* Motherboard/chipset features. This is a kind of general purpose
-	 * hook used to control some machine specific features (like reset
-	 * lines, chip power control, etc...).
-	 */
-	long (*feature_call)(unsigned int feature, ...);
-
-#ifdef CONFIG_SMP
-	/* functions for dealing with other cpus */
-	struct smp_ops_t *smp_ops;
-#endif /* CONFIG_SMP */
-
-#ifdef CONFIG_KEXEC
-	/* Called to shutdown machine specific hardware not already controlled
-	 * by other drivers.
-	 * XXX Should we move this one out of kexec scope?
-	 */
-	void (*machine_shutdown)(void);
-
-	/* Called to do the minimal shutdown needed to run a kexec'd kernel
-	 * to run successfully.
-	 * XXX Should we move this one out of kexec scope?
-	 */
-	void (*machine_crash_shutdown)(void);
-
-	/* Called to do what every setup is needed on image and the
-	 * reboot code buffer. Returns 0 on success.
-	 * Provide your own (maybe dummy) implementation if your platform
-	 * claims to support kexec.
-	 */
-	int (*machine_kexec_prepare)(struct kimage *image);
-
-	/* Called to handle any machine specific cleanup on image */
-	void (*machine_kexec_cleanup)(struct kimage *image);
-
-	/* Called to perform the _real_ kexec.
-	 * Do NOT allocate memory or fail here. We are past the point of
-	 * no return.
-	 */
-	void (*machine_kexec)(struct kimage *image);
-#endif /* CONFIG_KEXEC */
-};
-
-extern struct machdep_calls ppc_md;
-extern char cmd_line[COMMAND_LINE_SIZE];
-
-extern void setup_pci_ptrs(void);
-
-#ifdef CONFIG_SMP
-struct smp_ops_t {
-	void  (*message_pass)(int target, int msg);
-	int   (*probe)(void);
-	void  (*kick_cpu)(int nr);
-	void  (*setup_cpu)(int nr);
-	void  (*space_timers)(int nr);
-	void  (*take_timebase)(void);
-	void  (*give_timebase)(void);
-};
-
-/* Poor default implementations */
-extern void __devinit smp_generic_give_timebase(void);
-extern void __devinit smp_generic_take_timebase(void);
-#endif /* CONFIG_SMP */
-
-#endif /* _PPC_MACHDEP_H */
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/md.h b/include/asm-ppc/md.h
deleted file mode 100644
index 9a9b6b42b4b..00000000000
--- a/include/asm-ppc/md.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * md.h: High speed xor_block operation for RAID4/5
- *
- */
-
-#ifdef __KERNEL__
-#ifndef __ASM_MD_H
-#define __ASM_MD_H
-
-/* #define HAVE_ARCH_XORBLOCK */
-
-#define MD_XORBLOCK_ALIGNMENT	sizeof(long)
-
-#endif /* __ASM_MD_H */
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/mk48t59.h b/include/asm-ppc/mk48t59.h
deleted file mode 100644
index 6a0ed6fc2d5..00000000000
--- a/include/asm-ppc/mk48t59.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * Registers for the mk48t59 real-time-clock
- */
-
-#ifndef _PPC_MK48T59_H
-#define _PPC_MK48T59_H
-
-/* RTC Offsets */
-
-#define MK48T59_RTC_SECONDS		0x1FF9
-#define MK48T59_RTC_MINUTES		0x1FFA
-#define MK48T59_RTC_HOURS		0x1FFB
-#define MK48T59_RTC_DAY_OF_WEEK		0x1FFC
-#define MK48T59_RTC_DAY_OF_MONTH	0x1FFD
-#define MK48T59_RTC_MONTH		0x1FFE
-#define MK48T59_RTC_YEAR		0x1FFF
-
-#define MK48T59_RTC_CONTROLA		0x1FF8
-#define MK48T59_RTC_CA_WRITE		0x80
-#define MK48T59_RTC_CA_READ		0x40
-#define MK48T59_RTC_CA_CALIB_SIGN	0x20
-#define MK48T59_RTC_CA_CALIB_MASK	0x1f
-
-#define MK48T59_RTC_CONTROLB		0x1FF9
-#define MK48T59_RTC_CB_STOP		0x80
-
-#endif /* _PPC_MK48T59_H */
diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h
deleted file mode 100644
index d76ef098ed3..00000000000
--- a/include/asm-ppc/mmu.h
+++ /dev/null
@@ -1,444 +0,0 @@
-/*
- * PowerPC memory management structures
- */
-
-#ifdef __KERNEL__
-#ifndef _PPC_MMU_H_
-#define _PPC_MMU_H_
-
-
-#ifndef __ASSEMBLY__
-
-/*
- * Define physical address type.  Machines using split size
- * virtual/physical addressing like 32-bit virtual / 36-bit
- * physical need a larger than native word size type. -Matt
- */
-#ifndef CONFIG_PHYS_64BIT
-#define PHYS_FMT	"%.8lx"
-#else
-extern phys_addr_t fixup_bigphys_addr(phys_addr_t, phys_addr_t);
-#define PHYS_FMT	"%16Lx"
-#endif
-
-typedef struct {
-	unsigned long id;
-	unsigned long vdso_base;
-} mm_context_t;
-
-/* Hardware Page Table Entry */
-typedef struct _PTE {
-	unsigned long v:1;	/* Entry is valid */
-	unsigned long vsid:24;	/* Virtual segment identifier */
-	unsigned long h:1;	/* Hash algorithm indicator */
-	unsigned long api:6;	/* Abbreviated page index */
-	unsigned long rpn:20;	/* Real (physical) page number */
-	unsigned long    :3;	/* Unused */
-	unsigned long r:1;	/* Referenced */
-	unsigned long c:1;	/* Changed */
-	unsigned long w:1;	/* Write-thru cache mode */
-	unsigned long i:1;	/* Cache inhibited */
-	unsigned long m:1;	/* Memory coherence */
-	unsigned long g:1;	/* Guarded */
-	unsigned long  :1;	/* Unused */
-	unsigned long pp:2;	/* Page protection */
-} PTE;
-
-/* Values for PP (assumes Ks=0, Kp=1) */
-#define PP_RWXX	0	/* Supervisor read/write, User none */
-#define PP_RWRX 1	/* Supervisor read/write, User read */
-#define PP_RWRW 2	/* Supervisor read/write, User read/write */
-#define PP_RXRX 3	/* Supervisor read,       User read */
-
-/* Segment Register */
-typedef struct _SEGREG {
-	unsigned long t:1;	/* Normal or I/O  type */
-	unsigned long ks:1;	/* Supervisor 'key' (normally 0) */
-	unsigned long kp:1;	/* User 'key' (normally 1) */
-	unsigned long n:1;	/* No-execute */
-	unsigned long :4;	/* Unused */
-	unsigned long vsid:24;	/* Virtual Segment Identifier */
-} SEGREG;
-
-/* Block Address Translation (BAT) Registers */
-typedef struct _P601_BATU {	/* Upper part of BAT for 601 processor */
-	unsigned long bepi:15;	/* Effective page index (virtual address) */
-	unsigned long :8;	/* unused */
-	unsigned long w:1;
-	unsigned long i:1;	/* Cache inhibit */
-	unsigned long m:1;	/* Memory coherence */
-	unsigned long ks:1;	/* Supervisor key (normally 0) */
-	unsigned long kp:1;	/* User key (normally 1) */
-	unsigned long pp:2;	/* Page access protections */
-} P601_BATU;
-
-typedef struct _BATU {		/* Upper part of BAT (all except 601) */
-	unsigned long bepi:15;	/* Effective page index (virtual address) */
-	unsigned long :4;	/* Unused */
-	unsigned long bl:11;	/* Block size mask */
-	unsigned long vs:1;	/* Supervisor valid */
-	unsigned long vp:1;	/* User valid */
-} BATU;
-
-typedef struct _P601_BATL {	/* Lower part of BAT for 601 processor */
-	unsigned long brpn:15;	/* Real page index (physical address) */
-	unsigned long :10;	/* Unused */
-	unsigned long v:1;	/* Valid bit */
-	unsigned long bl:6;	/* Block size mask */
-} P601_BATL;
-
-typedef struct _BATL {		/* Lower part of BAT (all except 601) */
-	unsigned long brpn:15;	/* Real page index (physical address) */
-	unsigned long :10;	/* Unused */
-	unsigned long w:1;	/* Write-thru cache */
-	unsigned long i:1;	/* Cache inhibit */
-	unsigned long m:1;	/* Memory coherence */
-	unsigned long g:1;	/* Guarded (MBZ in IBAT) */
-	unsigned long :1;	/* Unused */
-	unsigned long pp:2;	/* Page access protections */
-} BATL;
-
-typedef struct _BAT {
-	BATU batu;		/* Upper register */
-	BATL batl;		/* Lower register */
-} BAT;
-
-typedef struct _P601_BAT {
-	P601_BATU batu;		/* Upper register */
-	P601_BATL batl;		/* Lower register */
-} P601_BAT;
-
-#endif /* __ASSEMBLY__ */
-
-/* Block size masks */
-#define BL_128K	0x000
-#define BL_256K 0x001
-#define BL_512K 0x003
-#define BL_1M   0x007
-#define BL_2M   0x00F
-#define BL_4M   0x01F
-#define BL_8M   0x03F
-#define BL_16M  0x07F
-#define BL_32M  0x0FF
-#define BL_64M  0x1FF
-#define BL_128M 0x3FF
-#define BL_256M 0x7FF
-
-/* BAT Access Protection */
-#define BPP_XX	0x00		/* No access */
-#define BPP_RX	0x01		/* Read only */
-#define BPP_RW	0x02		/* Read/write */
-
-/* Control/status registers for the MPC8xx.
- * A write operation to these registers causes serialized access.
- * During software tablewalk, the registers used perform mask/shift-add
- * operations when written/read.  A TLB entry is created when the Mx_RPN
- * is written, and the contents of several registers are used to
- * create the entry.
- */
-#define SPRN_MI_CTR	784	/* Instruction TLB control register */
-#define MI_GPM		0x80000000	/* Set domain manager mode */
-#define MI_PPM		0x40000000	/* Set subpage protection */
-#define MI_CIDEF	0x20000000	/* Set cache inhibit when MMU dis */
-#define MI_RSV4I	0x08000000	/* Reserve 4 TLB entries */
-#define MI_PPCS		0x02000000	/* Use MI_RPN prob/priv state */
-#define MI_IDXMASK	0x00001f00	/* TLB index to be loaded */
-#define MI_RESETVAL	0x00000000	/* Value of register at reset */
-
-/* These are the Ks and Kp from the PowerPC books.  For proper operation,
- * Ks = 0, Kp = 1.
- */
-#define SPRN_MI_AP	786
-#define MI_Ks		0x80000000	/* Should not be set */
-#define MI_Kp		0x40000000	/* Should always be set */
-
-/* The effective page number register.  When read, contains the information
- * about the last instruction TLB miss.  When MI_RPN is written, bits in
- * this register are used to create the TLB entry.
- */
-#define SPRN_MI_EPN	787
-#define MI_EPNMASK	0xfffff000	/* Effective page number for entry */
-#define MI_EVALID	0x00000200	/* Entry is valid */
-#define MI_ASIDMASK	0x0000000f	/* ASID match value */
-					/* Reset value is undefined */
-
-/* A "level 1" or "segment" or whatever you want to call it register.
- * For the instruction TLB, it contains bits that get loaded into the
- * TLB entry when the MI_RPN is written.
- */
-#define SPRN_MI_TWC	789
-#define MI_APG		0x000001e0	/* Access protection group (0) */
-#define MI_GUARDED	0x00000010	/* Guarded storage */
-#define MI_PSMASK	0x0000000c	/* Mask of page size bits */
-#define MI_PS8MEG	0x0000000c	/* 8M page size */
-#define MI_PS512K	0x00000004	/* 512K page size */
-#define MI_PS4K_16K	0x00000000	/* 4K or 16K page size */
-#define MI_SVALID	0x00000001	/* Segment entry is valid */
-					/* Reset value is undefined */
-
-/* Real page number.  Defined by the pte.  Writing this register
- * causes a TLB entry to be created for the instruction TLB, using
- * additional information from the MI_EPN, and MI_TWC registers.
- */
-#define SPRN_MI_RPN	790
-
-/* Define an RPN value for mapping kernel memory to large virtual
- * pages for boot initialization.  This has real page number of 0,
- * large page size, shared page, cache enabled, and valid.
- * Also mark all subpages valid and write access.
- */
-#define MI_BOOTINIT	0x000001fd
-
-#define SPRN_MD_CTR	792	/* Data TLB control register */
-#define MD_GPM		0x80000000	/* Set domain manager mode */
-#define MD_PPM		0x40000000	/* Set subpage protection */
-#define MD_CIDEF	0x20000000	/* Set cache inhibit when MMU dis */
-#define MD_WTDEF	0x10000000	/* Set writethrough when MMU dis */
-#define MD_RSV4I	0x08000000	/* Reserve 4 TLB entries */
-#define MD_TWAM		0x04000000	/* Use 4K page hardware assist */
-#define MD_PPCS		0x02000000	/* Use MI_RPN prob/priv state */
-#define MD_IDXMASK	0x00001f00	/* TLB index to be loaded */
-#define MD_RESETVAL	0x04000000	/* Value of register at reset */
-
-#define SPRN_M_CASID	793	/* Address space ID (context) to match */
-#define MC_ASIDMASK	0x0000000f	/* Bits used for ASID value */
-
-
-/* These are the Ks and Kp from the PowerPC books.  For proper operation,
- * Ks = 0, Kp = 1.
- */
-#define SPRN_MD_AP	794
-#define MD_Ks		0x80000000	/* Should not be set */
-#define MD_Kp		0x40000000	/* Should always be set */
-
-/* The effective page number register.  When read, contains the information
- * about the last instruction TLB miss.  When MD_RPN is written, bits in
- * this register are used to create the TLB entry.
- */
-#define SPRN_MD_EPN	795
-#define MD_EPNMASK	0xfffff000	/* Effective page number for entry */
-#define MD_EVALID	0x00000200	/* Entry is valid */
-#define MD_ASIDMASK	0x0000000f	/* ASID match value */
-					/* Reset value is undefined */
-
-/* The pointer to the base address of the first level page table.
- * During a software tablewalk, reading this register provides the address
- * of the entry associated with MD_EPN.
- */
-#define SPRN_M_TWB	796
-#define	M_L1TB		0xfffff000	/* Level 1 table base address */
-#define M_L1INDX	0x00000ffc	/* Level 1 index, when read */
-					/* Reset value is undefined */
-
-/* A "level 1" or "segment" or whatever you want to call it register.
- * For the data TLB, it contains bits that get loaded into the TLB entry
- * when the MD_RPN is written.  It is also provides the hardware assist
- * for finding the PTE address during software tablewalk.
- */
-#define SPRN_MD_TWC	797
-#define MD_L2TB		0xfffff000	/* Level 2 table base address */
-#define MD_L2INDX	0xfffffe00	/* Level 2 index (*pte), when read */
-#define MD_APG		0x000001e0	/* Access protection group (0) */
-#define MD_GUARDED	0x00000010	/* Guarded storage */
-#define MD_PSMASK	0x0000000c	/* Mask of page size bits */
-#define MD_PS8MEG	0x0000000c	/* 8M page size */
-#define MD_PS512K	0x00000004	/* 512K page size */
-#define MD_PS4K_16K	0x00000000	/* 4K or 16K page size */
-#define MD_WT		0x00000002	/* Use writethrough page attribute */
-#define MD_SVALID	0x00000001	/* Segment entry is valid */
-					/* Reset value is undefined */
-
-
-/* Real page number.  Defined by the pte.  Writing this register
- * causes a TLB entry to be created for the data TLB, using
- * additional information from the MD_EPN, and MD_TWC registers.
- */
-#define SPRN_MD_RPN	798
-
-/* This is a temporary storage register that could be used to save
- * a processor working register during a tablewalk.
- */
-#define SPRN_M_TW	799
-
-/*
- * At present, all PowerPC 400-class processors share a similar TLB
- * architecture. The instruction and data sides share a unified,
- * 64-entry, fully-associative TLB which is maintained totally under
- * software control. In addition, the instruction side has a
- * hardware-managed, 4-entry, fully- associative TLB which serves as a
- * first level to the shared TLB. These two TLBs are known as the UTLB
- * and ITLB, respectively.
- */
-
-#define        PPC4XX_TLB_SIZE 64
-
-/*
- * TLB entries are defined by a "high" tag portion and a "low" data
- * portion.  On all architectures, the data portion is 32-bits.
- *
- * TLB entries are managed entirely under software control by reading,
- * writing, and searchoing using the 4xx-specific tlbre, tlbwr, and tlbsx
- * instructions.
- */
-
-#define	TLB_LO          1
-#define	TLB_HI          0
-
-#define	TLB_DATA        TLB_LO
-#define	TLB_TAG         TLB_HI
-
-/* Tag portion */
-
-#define TLB_EPN_MASK    0xFFFFFC00      /* Effective Page Number */
-#define TLB_PAGESZ_MASK 0x00000380
-#define TLB_PAGESZ(x)   (((x) & 0x7) << 7)
-#define   PAGESZ_1K		0
-#define   PAGESZ_4K             1
-#define   PAGESZ_16K            2
-#define   PAGESZ_64K            3
-#define   PAGESZ_256K           4
-#define   PAGESZ_1M             5
-#define   PAGESZ_4M             6
-#define   PAGESZ_16M            7
-#define TLB_VALID       0x00000040      /* Entry is valid */
-
-/* Data portion */
-
-#define TLB_RPN_MASK    0xFFFFFC00      /* Real Page Number */
-#define TLB_PERM_MASK   0x00000300
-#define TLB_EX          0x00000200      /* Instruction execution allowed */
-#define TLB_WR          0x00000100      /* Writes permitted */
-#define TLB_ZSEL_MASK   0x000000F0
-#define TLB_ZSEL(x)     (((x) & 0xF) << 4)
-#define TLB_ATTR_MASK   0x0000000F
-#define TLB_W           0x00000008      /* Caching is write-through */
-#define TLB_I           0x00000004      /* Caching is inhibited */
-#define TLB_M           0x00000002      /* Memory is coherent */
-#define TLB_G           0x00000001      /* Memory is guarded from prefetch */
-
-/*
- * PPC440 support
- */
-#define PPC44x_MMUCR_TID	0x000000ff
-#define PPC44x_MMUCR_STS	0x00010000
-
-#define	PPC44x_TLB_PAGEID	0
-#define	PPC44x_TLB_XLAT		1
-#define	PPC44x_TLB_ATTRIB	2
-
-/* Page identification fields */
-#define PPC44x_TLB_EPN_MASK	0xfffffc00      /* Effective Page Number */
-#define	PPC44x_TLB_VALID	0x00000200      /* Valid flag */
-#define PPC44x_TLB_TS		0x00000100	/* Translation address space */
-#define PPC44x_TLB_1K		0x00000000	/* Page sizes */
-#define PPC44x_TLB_4K		0x00000010
-#define PPC44x_TLB_16K		0x00000020
-#define PPC44x_TLB_64K		0x00000030
-#define PPC44x_TLB_256K		0x00000040
-#define PPC44x_TLB_1M		0x00000050
-#define PPC44x_TLB_16M		0x00000070
-#define	PPC44x_TLB_256M		0x00000090
-
-/* Translation fields */
-#define PPC44x_TLB_RPN_MASK	0xfffffc00      /* Real Page Number */
-#define	PPC44x_TLB_ERPN_MASK	0x0000000f
-
-/* Storage attribute and access control fields */
-#define PPC44x_TLB_ATTR_MASK	0x0000ff80
-#define PPC44x_TLB_U0		0x00008000      /* User 0 */
-#define PPC44x_TLB_U1		0x00004000      /* User 1 */
-#define PPC44x_TLB_U2		0x00002000      /* User 2 */
-#define PPC44x_TLB_U3		0x00001000      /* User 3 */
-#define PPC44x_TLB_W		0x00000800      /* Caching is write-through */
-#define PPC44x_TLB_I		0x00000400      /* Caching is inhibited */
-#define PPC44x_TLB_M		0x00000200      /* Memory is coherent */
-#define PPC44x_TLB_G		0x00000100      /* Memory is guarded */
-#define PPC44x_TLB_E		0x00000080      /* Memory is guarded */
-
-#define PPC44x_TLB_PERM_MASK	0x0000003f
-#define PPC44x_TLB_UX		0x00000020      /* User execution */
-#define PPC44x_TLB_UW		0x00000010      /* User write */
-#define PPC44x_TLB_UR		0x00000008      /* User read */
-#define PPC44x_TLB_SX		0x00000004      /* Super execution */
-#define PPC44x_TLB_SW		0x00000002      /* Super write */
-#define PPC44x_TLB_SR		0x00000001      /* Super read */
-
-/* Book-E defined page sizes */
-#define BOOKE_PAGESZ_1K		0
-#define BOOKE_PAGESZ_4K		1
-#define BOOKE_PAGESZ_16K	2
-#define BOOKE_PAGESZ_64K	3
-#define BOOKE_PAGESZ_256K	4
-#define BOOKE_PAGESZ_1M		5
-#define BOOKE_PAGESZ_4M		6
-#define BOOKE_PAGESZ_16M	7
-#define BOOKE_PAGESZ_64M	8
-#define BOOKE_PAGESZ_256M	9
-#define BOOKE_PAGESZ_1GB	10
-#define BOOKE_PAGESZ_4GB	11
-#define BOOKE_PAGESZ_16GB	12
-#define BOOKE_PAGESZ_64GB	13
-#define BOOKE_PAGESZ_256GB	14
-#define BOOKE_PAGESZ_1TB	15
-
-#ifndef CONFIG_SERIAL_TEXT_DEBUG
-#define PPC44x_EARLY_TLBS	1
-#else
-#define PPC44x_EARLY_TLBS	2
-#endif
-
-/*
- * Freescale Book-E MMU support
- */
-
-#define MAS0_TLBSEL(x)	((x << 28) & 0x30000000)
-#define MAS0_ESEL(x)	((x << 16) & 0x0FFF0000)
-#define MAS0_NV(x)	((x) & 0x00000FFF)
-
-#define MAS1_VALID 	0x80000000
-#define MAS1_IPROT	0x40000000
-#define MAS1_TID(x)	((x << 16) & 0x3FFF0000)
-#define MAS1_TS		0x00001000
-#define MAS1_TSIZE(x)	((x << 8) & 0x00000F00)
-
-#define MAS2_EPN	0xFFFFF000
-#define MAS2_X0		0x00000040
-#define MAS2_X1		0x00000020
-#define MAS2_W		0x00000010
-#define MAS2_I		0x00000008
-#define MAS2_M		0x00000004
-#define MAS2_G		0x00000002
-#define MAS2_E		0x00000001
-
-#define MAS3_RPN	0xFFFFF000
-#define MAS3_U0		0x00000200
-#define MAS3_U1		0x00000100
-#define MAS3_U2		0x00000080
-#define MAS3_U3		0x00000040
-#define MAS3_UX		0x00000020
-#define MAS3_SX		0x00000010
-#define MAS3_UW		0x00000008
-#define MAS3_SW		0x00000004
-#define MAS3_UR		0x00000002
-#define MAS3_SR		0x00000001
-
-#define MAS4_TLBSELD(x) MAS0_TLBSEL(x)
-#define MAS4_TIDDSEL	0x000F0000
-#define MAS4_TSIZED(x)	MAS1_TSIZE(x)
-#define MAS4_X0D	0x00000040
-#define MAS4_X1D	0x00000020
-#define MAS4_WD		0x00000010
-#define MAS4_ID		0x00000008
-#define MAS4_MD		0x00000004
-#define MAS4_GD		0x00000002
-#define MAS4_ED		0x00000001
-
-#define MAS6_SPID0	0x3FFF0000
-#define MAS6_SPID1	0x00007FFE
-#define MAS6_SAS	0x00000001
-#define MAS6_SPID	MAS6_SPID0
-
-#define MAS7_RPN	0xFFFFFFFF
-
-#endif /* _PPC_MMU_H_ */
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/mmu_context.h b/include/asm-ppc/mmu_context.h
deleted file mode 100644
index 9f097e25b16..00000000000
--- a/include/asm-ppc/mmu_context.h
+++ /dev/null
@@ -1,198 +0,0 @@
-#ifdef __KERNEL__
-#ifndef __PPC_MMU_CONTEXT_H
-#define __PPC_MMU_CONTEXT_H
-
-#include <linux/bitops.h>
-
-#include <asm/atomic.h>
-#include <asm/mmu.h>
-#include <asm/cputable.h>
-#include <asm-generic/mm_hooks.h>
-
-/*
- * On 32-bit PowerPC 6xx/7xx/7xxx CPUs, we use a set of 16 VSIDs
- * (virtual segment identifiers) for each context.  Although the
- * hardware supports 24-bit VSIDs, and thus >1 million contexts,
- * we only use 32,768 of them.  That is ample, since there can be
- * at most around 30,000 tasks in the system anyway, and it means
- * that we can use a bitmap to indicate which contexts are in use.
- * Using a bitmap means that we entirely avoid all of the problems
- * that we used to have when the context number overflowed,
- * particularly on SMP systems.
- *  -- paulus.
- */
-
-/*
- * This function defines the mapping from contexts to VSIDs (virtual
- * segment IDs).  We use a skew on both the context and the high 4 bits
- * of the 32-bit virtual address (the "effective segment ID") in order
- * to spread out the entries in the MMU hash table.  Note, if this
- * function is changed then arch/ppc/mm/hashtable.S will have to be
- * changed to correspond.
- */
-#define CTX_TO_VSID(ctx, va)	(((ctx) * (897 * 16) + ((va) >> 28) * 0x111) \
-				 & 0xffffff)
-
-/*
-   The MPC8xx has only 16 contexts.  We rotate through them on each
-   task switch.  A better way would be to keep track of tasks that
-   own contexts, and implement an LRU usage.  That way very active
-   tasks don't always have to pay the TLB reload overhead.  The
-   kernel pages are mapped shared, so the kernel can run on behalf
-   of any task that makes a kernel entry.  Shared does not mean they
-   are not protected, just that the ASID comparison is not performed.
-        -- Dan
-
-   The IBM4xx has 256 contexts, so we can just rotate through these
-   as a way of "switching" contexts.  If the TID of the TLB is zero,
-   the PID/TID comparison is disabled, so we can use a TID of zero
-   to represent all kernel pages as shared among all contexts.
-   	-- Dan
- */
-
-static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
-{
-}
-
-#ifdef CONFIG_8xx
-#define NO_CONTEXT      	16
-#define LAST_CONTEXT    	15
-#define FIRST_CONTEXT    	0
-
-#elif defined(CONFIG_4xx)
-#define NO_CONTEXT      	256
-#define LAST_CONTEXT    	255
-#define FIRST_CONTEXT    	1
-
-#else
-
-/* PPC 6xx, 7xx CPUs */
-#define NO_CONTEXT      	((unsigned long) -1)
-#define LAST_CONTEXT    	32767
-#define FIRST_CONTEXT    	1
-#endif
-
-/*
- * Set the current MMU context.
- * On 32-bit PowerPCs (other than the 8xx embedded chips), this is done by
- * loading up the segment registers for the user part of the address space.
- *
- * Since the PGD is immediately available, it is much faster to simply
- * pass this along as a second parameter, which is required for 8xx and
- * can be used for debugging on all processors (if you happen to have
- * an Abatron).
- */
-extern void set_context(unsigned long contextid, pgd_t *pgd);
-
-/*
- * Bitmap of contexts in use.
- * The size of this bitmap is LAST_CONTEXT + 1 bits.
- */
-extern unsigned long context_map[];
-
-/*
- * This caches the next context number that we expect to be free.
- * Its use is an optimization only, we can't rely on this context
- * number to be free, but it usually will be.
- */
-extern unsigned long next_mmu_context;
-
-/*
- * If we don't have sufficient contexts to give one to every task
- * that could be in the system, we need to be able to steal contexts.
- * These variables support that.
- */
-#if LAST_CONTEXT < 30000
-#define FEW_CONTEXTS	1
-extern atomic_t nr_free_contexts;
-extern struct mm_struct *context_mm[LAST_CONTEXT+1];
-extern void steal_context(void);
-#endif
-
-/*
- * Get a new mmu context for the address space described by `mm'.
- */
-static inline void get_mmu_context(struct mm_struct *mm)
-{
-	unsigned long ctx;
-
-	if (mm->context.id != NO_CONTEXT)
-		return;
-#ifdef FEW_CONTEXTS
-	while (atomic_dec_if_positive(&nr_free_contexts) < 0)
-		steal_context();
-#endif
-	ctx = next_mmu_context;
-	while (test_and_set_bit(ctx, context_map)) {
-		ctx = find_next_zero_bit(context_map, LAST_CONTEXT+1, ctx);
-		if (ctx > LAST_CONTEXT)
-			ctx = 0;
-	}
-	next_mmu_context = (ctx + 1) & LAST_CONTEXT;
-	mm->context.id = ctx;
-#ifdef FEW_CONTEXTS
-	context_mm[ctx] = mm;
-#endif
-}
-
-/*
- * Set up the context for a new address space.
- */
-static inline int init_new_context(struct task_struct *t, struct mm_struct *mm)
-{
-	mm->context.id = NO_CONTEXT;
-	mm->context.vdso_base = 0;
-	return 0;
-}
-
-/*
- * We're finished using the context for an address space.
- */
-static inline void destroy_context(struct mm_struct *mm)
-{
-	preempt_disable();
-	if (mm->context.id != NO_CONTEXT) {
-		clear_bit(mm->context.id, context_map);
-		mm->context.id = NO_CONTEXT;
-#ifdef FEW_CONTEXTS
-		atomic_inc(&nr_free_contexts);
-#endif
-	}
-	preempt_enable();
-}
-
-static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
-			     struct task_struct *tsk)
-{
-#ifdef CONFIG_ALTIVEC
-	if (cpu_has_feature(CPU_FTR_ALTIVEC))
-	asm volatile ("dssall;\n"
-#ifndef CONFIG_POWER4
-	 "sync;\n" /* G4 needs a sync here, G5 apparently not */
-#endif
-	 : : );
-#endif /* CONFIG_ALTIVEC */
-
-	tsk->thread.pgdir = next->pgd;
-
-	/* No need to flush userspace segments if the mm doesnt change */
-	if (prev == next)
-		return;
-
-	/* Setup new userspace context */
-	get_mmu_context(next);
-	set_context(next->context.id, next->pgd);
-}
-
-#define deactivate_mm(tsk,mm)	do { } while (0)
-
-/*
- * After we have set current->mm to a new value, this activates
- * the context for the new mm so we see the new mappings.
- */
-#define activate_mm(active_mm, mm)   switch_mm(active_mm, mm, current)
-
-extern void mmu_context_init(void);
-
-#endif /* __PPC_MMU_CONTEXT_H */
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/mpc10x.h b/include/asm-ppc/mpc10x.h
deleted file mode 100644
index b30a6a3b5bd..00000000000
--- a/include/asm-ppc/mpc10x.h
+++ /dev/null
@@ -1,180 +0,0 @@
-/*
- * Common routines for the Motorola SPS MPC106/8240/107 Host bridge/Mem
- * ctlr/EPIC/etc.
- *
- * Author: Mark A. Greer
- *         mgreer@mvista.com
- *
- * 2001 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifndef __PPC_KERNEL_MPC10X_H
-#define __PPC_KERNEL_MPC10X_H
-
-#include <linux/pci_ids.h>
-#include <asm/pci-bridge.h>
-
-/*
- * The values here don't completely map everything but should work in most
- * cases.
- *
- * MAP A (PReP Map)
- *   Processor: 0x80000000 - 0x807fffff -> PCI I/O: 0x00000000 - 0x007fffff
- *   Processor: 0xc0000000 - 0xdfffffff -> PCI MEM: 0x00000000 - 0x1fffffff
- *   PCI MEM:   0x80000000 -> Processor System Memory: 0x00000000
- *   EUMB mapped to: ioremap_base - 0x00100000 (ioremap_base - 1 MB)
- *
- * MAP B (CHRP Map)
- *   Processor: 0xfe000000 - 0xfebfffff -> PCI I/O: 0x00000000 - 0x00bfffff
- *   Processor: 0x80000000 - 0xbfffffff -> PCI MEM: 0x80000000 - 0xbfffffff
- *   PCI MEM:   0x00000000 -> Processor System Memory: 0x00000000
- *   EUMB mapped to: ioremap_base - 0x00100000 (ioremap_base - 1 MB)
- */
-
-/*
- * Define the vendor/device IDs for the various bridges--should be added to
- * <linux/pci_ids.h>
- */
-#define	MPC10X_BRIDGE_106	((PCI_DEVICE_ID_MOTOROLA_MPC106 << 16) |  \
-				  PCI_VENDOR_ID_MOTOROLA)
-#define	MPC10X_BRIDGE_8240	((0x0003 << 16) | PCI_VENDOR_ID_MOTOROLA)
-#define	MPC10X_BRIDGE_107	((0x0004 << 16) | PCI_VENDOR_ID_MOTOROLA)
-#define	MPC10X_BRIDGE_8245	((0x0006 << 16) | PCI_VENDOR_ID_MOTOROLA)
-
-/* Define the type of map to use */
-#define	MPC10X_MEM_MAP_A		1
-#define	MPC10X_MEM_MAP_B		2
-
-/* Map A (PReP Map) Defines */
-#define	MPC10X_MAPA_CNFG_ADDR		0x80000cf8
-#define	MPC10X_MAPA_CNFG_DATA		0x80000cfc
-
-#define MPC10X_MAPA_ISA_IO_BASE		0x80000000
-#define MPC10X_MAPA_ISA_MEM_BASE	0xc0000000
-#define	MPC10X_MAPA_DRAM_OFFSET		0x80000000
-
-#define	MPC10X_MAPA_PCI_INTACK_ADDR	0xbffffff0
-#define	MPC10X_MAPA_PCI_IO_START	0x00000000
-#define	MPC10X_MAPA_PCI_IO_END	       (0x00800000 - 1)
-#define	MPC10X_MAPA_PCI_MEM_START	0x00000000
-#define	MPC10X_MAPA_PCI_MEM_END	       (0x20000000 - 1)
-
-#define	MPC10X_MAPA_PCI_MEM_OFFSET	(MPC10X_MAPA_ISA_MEM_BASE -	\
-					 MPC10X_MAPA_PCI_MEM_START)
-
-/* Map B (CHRP Map) Defines */
-#define	MPC10X_MAPB_CNFG_ADDR		0xfec00000
-#define	MPC10X_MAPB_CNFG_DATA		0xfee00000
-
-#define MPC10X_MAPB_ISA_IO_BASE		0xfe000000
-#define MPC10X_MAPB_ISA_MEM_BASE	0x80000000
-#define	MPC10X_MAPB_DRAM_OFFSET		0x00000000
-
-#define	MPC10X_MAPB_PCI_INTACK_ADDR	0xfef00000
-#define	MPC10X_MAPB_PCI_IO_START	0x00000000
-#define	MPC10X_MAPB_PCI_IO_END	       (0x00c00000 - 1)
-#define	MPC10X_MAPB_PCI_MEM_START	0x80000000
-#define	MPC10X_MAPB_PCI_MEM_END	       (0xc0000000 - 1)
-
-#define	MPC10X_MAPB_PCI_MEM_OFFSET	(MPC10X_MAPB_ISA_MEM_BASE -	\
-					 MPC10X_MAPB_PCI_MEM_START)
-
-/* Set hose members to values appropriate for the mem map used */
-#define	MPC10X_SETUP_HOSE(hose, map) {					\
-	(hose)->pci_mem_offset = MPC10X_MAP##map##_PCI_MEM_OFFSET;	\
-	(hose)->io_space.start = MPC10X_MAP##map##_PCI_IO_START;	\
-	(hose)->io_space.end = MPC10X_MAP##map##_PCI_IO_END;		\
-	(hose)->mem_space.start = MPC10X_MAP##map##_PCI_MEM_START;	\
-	(hose)->mem_space.end = MPC10X_MAP##map##_PCI_MEM_END;		\
-	(hose)->io_base_virt = (void *)MPC10X_MAP##map##_ISA_IO_BASE;	\
-}
-
-
-/* Miscellaneous Configuration register offsets */
-#define	MPC10X_CFG_PIR_REG		0x09
-#define	MPC10X_CFG_PIR_HOST_BRIDGE	0x00
-#define	MPC10X_CFG_PIR_AGENT		0x01
-
-#define	MPC10X_CFG_EUMBBAR		0x78
-
-#define	MPC10X_CFG_PICR1_REG		0xa8
-#define	MPC10X_CFG_PICR1_ADDR_MAP_MASK	0x00010000
-#define	MPC10X_CFG_PICR1_ADDR_MAP_A	0x00010000
-#define	MPC10X_CFG_PICR1_ADDR_MAP_B	0x00000000
-#define	MPC10X_CFG_PICR1_SPEC_PCI_RD	0x00000004
-#define	MPC10X_CFG_PICR1_ST_GATH_EN	0x00000040
-
-#define	MPC10X_CFG_PICR2_REG		0xac
-#define	MPC10X_CFG_PICR2_COPYBACK_OPT	0x00000001
-
-#define	MPC10X_CFG_MAPB_OPTIONS_REG	0xe0
-#define	MPC10X_CFG_MAPB_OPTIONS_CFAE	0x80	/* CPU_FD_ALIAS_EN */
-#define	MPC10X_CFG_MAPB_OPTIONS_PFAE	0x40	/* PCI_FD_ALIAS_EN */
-#define	MPC10X_CFG_MAPB_OPTIONS_DR	0x20	/* DLL_RESET */
-#define	MPC10X_CFG_MAPB_OPTIONS_PCICH	0x08	/* PCI_COMPATIBILITY_HOLE */
-#define	MPC10X_CFG_MAPB_OPTIONS_PROCCH	0x04	/* PROC_COMPATIBILITY_HOLE */
-
-/* Define offsets for the memory controller registers in the config space */
-#define MPC10X_MCTLR_MEM_START_1	0x80	/* Banks 0-3 */
-#define MPC10X_MCTLR_MEM_START_2	0x84	/* Banks 4-7 */
-#define MPC10X_MCTLR_EXT_MEM_START_1	0x88	/* Banks 0-3 */
-#define MPC10X_MCTLR_EXT_MEM_START_2	0x8c	/* Banks 4-7 */
-
-#define MPC10X_MCTLR_MEM_END_1		0x90	/* Banks 0-3 */
-#define MPC10X_MCTLR_MEM_END_2		0x94	/* Banks 4-7 */
-#define MPC10X_MCTLR_EXT_MEM_END_1	0x98	/* Banks 0-3 */
-#define MPC10X_MCTLR_EXT_MEM_END_2	0x9c	/* Banks 4-7 */
-
-#define MPC10X_MCTLR_MEM_BANK_ENABLES	0xa0
-
-/* Define some offset in the EUMB */
-#define	MPC10X_EUMB_SIZE		0x00100000 /* Total EUMB size (1MB) */
-
-#define MPC10X_EUMB_MU_OFFSET		0x00000000 /* Msg Unit reg offset */
-#define MPC10X_EUMB_MU_SIZE		0x00001000 /* Msg Unit reg size */
-#define MPC10X_EUMB_DMA_OFFSET		0x00001000 /* DMA Unit reg offset */
-#define MPC10X_EUMB_DMA_SIZE		0x00001000 /* DMA Unit reg size  */
-#define MPC10X_EUMB_ATU_OFFSET		0x00002000 /* Addr xlate reg offset */
-#define MPC10X_EUMB_ATU_SIZE		0x00001000 /* Addr xlate reg size  */
-#define MPC10X_EUMB_I2C_OFFSET		0x00003000 /* I2C Unit reg offset */
-#define MPC10X_EUMB_I2C_SIZE		0x00001000 /* I2C Unit reg size  */
-#define MPC10X_EUMB_DUART_OFFSET	0x00004000 /* DUART Unit reg offset (8245) */
-#define MPC10X_EUMB_DUART_SIZE		0x00001000 /* DUART Unit reg size (8245) */
-#define	MPC10X_EUMB_EPIC_OFFSET		0x00040000 /* EPIC offset in EUMB */
-#define	MPC10X_EUMB_EPIC_SIZE		0x00030000 /* EPIC size */
-#define MPC10X_EUMB_PM_OFFSET		0x000fe000 /* Performance Monitor reg offset (8245) */
-#define MPC10X_EUMB_PM_SIZE		0x00001000 /* Performance Monitor reg size (8245) */
-#define MPC10X_EUMB_WP_OFFSET		0x000ff000 /* Data path diagnostic, watchpoint reg offset */
-#define MPC10X_EUMB_WP_SIZE		0x00001000 /* Data path diagnostic, watchpoint reg size */
-
-/*
- * Define some recommended places to put the EUMB regs.
- * For both maps, recommend putting the EUMB from 0xeff00000 to 0xefffffff.
- */
-extern unsigned long			ioremap_base;
-#define	MPC10X_MAPA_EUMB_BASE		(ioremap_base - MPC10X_EUMB_SIZE)
-#define	MPC10X_MAPB_EUMB_BASE		MPC10X_MAPA_EUMB_BASE
-
-enum ppc_sys_devices {
-	MPC10X_IIC1,
-	MPC10X_DMA0,
-	MPC10X_DMA1,
-	MPC10X_UART0,
-	MPC10X_UART1,
-	NUM_PPC_SYS_DEVS,
-};
-
-int mpc10x_bridge_init(struct pci_controller *hose,
-		       uint current_map,
-		       uint new_map,
-		       uint phys_eumb_base);
-unsigned long mpc10x_get_mem_size(uint mem_map);
-int mpc10x_enable_store_gathering(struct pci_controller *hose);
-int mpc10x_disable_store_gathering(struct pci_controller *hose);
-
-/* For MPC107 boards that use the built-in openpic */
-void mpc10x_set_openpic(void);
-
-#endif	/* __PPC_KERNEL_MPC10X_H */
diff --git a/include/asm-ppc/mpc52xx.h b/include/asm-ppc/mpc52xx.h
deleted file mode 100644
index d9d21aa68ba..00000000000
--- a/include/asm-ppc/mpc52xx.h
+++ /dev/null
@@ -1,450 +0,0 @@
-/*
- * include/asm-ppc/mpc52xx.h
- * 
- * Prototypes, etc. for the Freescale MPC52xx embedded cpu chips
- * May need to be cleaned as the port goes on ...
- *
- *
- * Maintainer : Sylvain Munaut <tnt@246tNt.com>
- *
- * Originally written by Dale Farnsworth <dfarnsworth@mvista.com> 
- * for the 2.4 kernel.
- *
- * Copyright (C) 2004-2005 Sylvain Munaut <tnt@246tNt.com>
- * Copyright (C) 2003 MontaVista, Software, Inc.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-#ifndef __ASM_MPC52xx_H__
-#define __ASM_MPC52xx_H__
-
-#ifndef __ASSEMBLY__
-#include <asm/ppcboot.h>
-#include <asm/types.h>
-
-struct pt_regs;
-#endif /* __ASSEMBLY__ */
-
-
-/* ======================================================================== */
-/* PPC Sys devices definition                                               */
-/* ======================================================================== */
-
-enum ppc_sys_devices {
-	MPC52xx_MSCAN1,
-	MPC52xx_MSCAN2,
-	MPC52xx_SPI,
-	MPC52xx_USB,
-	MPC52xx_BDLC,
-	MPC52xx_PSC1,
-	MPC52xx_PSC2,
-	MPC52xx_PSC3,
-	MPC52xx_PSC4,
-	MPC52xx_PSC5,
-	MPC52xx_PSC6,
-	MPC52xx_FEC,
-	MPC52xx_ATA,
-	MPC52xx_I2C1,
-	MPC52xx_I2C2,
-	NUM_PPC_SYS_DEVS,
-};
-
-
-/* ======================================================================== */
-/* Main registers/struct addresses                                          */
-/* ======================================================================== */
-
-/* MBAR position */
-#define MPC52xx_MBAR		0xf0000000	/* Phys address */
-#define MPC52xx_MBAR_VIRT	0xf0000000	/* Virt address */
-#define MPC52xx_MBAR_SIZE	0x00010000
-
-#define MPC52xx_PA(x)		((phys_addr_t)(MPC52xx_MBAR + (x)))
-#define MPC52xx_VA(x)		((void __iomem *)(MPC52xx_MBAR_VIRT + (x)))
-
-/* Registers zone offset/size  */
-#define MPC52xx_MMAP_CTL_OFFSET		0x0000
-#define MPC52xx_MMAP_CTL_SIZE		0x068
-#define MPC52xx_SDRAM_OFFSET		0x0100
-#define MPC52xx_SDRAM_SIZE		0x010
-#define MPC52xx_CDM_OFFSET		0x0200
-#define MPC52xx_CDM_SIZE		0x038
-#define MPC52xx_INTR_OFFSET		0x0500
-#define MPC52xx_INTR_SIZE		0x04c
-#define MPC52xx_GPTx_OFFSET(x)		(0x0600 + ((x)<<4))
-#define MPC52xx_GPT_SIZE		0x010
-#define MPC52xx_RTC_OFFSET		0x0800
-#define MPC52xx_RTC_SIZE		0x024
-#define MPC52xx_GPIO_OFFSET		0x0b00
-#define MPC52xx_GPIO_SIZE		0x040
-#define MPC52xx_GPIO_WKUP_OFFSET	0x0c00
-#define MPC52xx_GPIO_WKUP_SIZE		0x028
-#define MPC52xx_PCI_OFFSET		0x0d00
-#define MPC52xx_PCI_SIZE		0x100
-#define MPC52xx_SDMA_OFFSET		0x1200
-#define MPC52xx_SDMA_SIZE		0x100
-#define MPC52xx_XLB_OFFSET		0x1f00
-#define MPC52xx_XLB_SIZE		0x100
-#define MPC52xx_PSCx_OFFSET(x)		(((x)!=6)?(0x1e00+((x)<<9)):0x2c00)
-#define MPC52xx_PSC_SIZE		0x0a0
-
-/* SRAM used for SDMA */
-#define MPC52xx_SRAM_OFFSET		0x8000
-#define MPC52xx_SRAM_SIZE		0x4000
-
-
-/* ======================================================================== */
-/* IRQ mapping                                                              */
-/* ======================================================================== */
-/* Be sure to look at mpc52xx_pic.h if you wish for whatever reason to change
- * this
- */
-
-#define MPC52xx_CRIT_IRQ_NUM	4
-#define MPC52xx_MAIN_IRQ_NUM	17
-#define MPC52xx_SDMA_IRQ_NUM	17
-#define MPC52xx_PERP_IRQ_NUM	23
-
-#define MPC52xx_CRIT_IRQ_BASE	1
-#define MPC52xx_MAIN_IRQ_BASE	(MPC52xx_CRIT_IRQ_BASE + MPC52xx_CRIT_IRQ_NUM)
-#define MPC52xx_SDMA_IRQ_BASE	(MPC52xx_MAIN_IRQ_BASE + MPC52xx_MAIN_IRQ_NUM)
-#define MPC52xx_PERP_IRQ_BASE	(MPC52xx_SDMA_IRQ_BASE + MPC52xx_SDMA_IRQ_NUM)
-
-#define MPC52xx_IRQ0			(MPC52xx_CRIT_IRQ_BASE + 0)
-#define MPC52xx_SLICE_TIMER_0_IRQ	(MPC52xx_CRIT_IRQ_BASE + 1)
-#define MPC52xx_HI_INT_IRQ		(MPC52xx_CRIT_IRQ_BASE + 2)
-#define MPC52xx_CCS_IRQ			(MPC52xx_CRIT_IRQ_BASE + 3)
-
-#define MPC52xx_IRQ1			(MPC52xx_MAIN_IRQ_BASE + 1)
-#define MPC52xx_IRQ2			(MPC52xx_MAIN_IRQ_BASE + 2)
-#define MPC52xx_IRQ3			(MPC52xx_MAIN_IRQ_BASE + 3)
-
-#define MPC52xx_SDMA_IRQ		(MPC52xx_PERP_IRQ_BASE + 0)
-#define MPC52xx_PSC1_IRQ		(MPC52xx_PERP_IRQ_BASE + 1)
-#define MPC52xx_PSC2_IRQ		(MPC52xx_PERP_IRQ_BASE + 2)
-#define MPC52xx_PSC3_IRQ		(MPC52xx_PERP_IRQ_BASE + 3)
-#define MPC52xx_PSC6_IRQ		(MPC52xx_PERP_IRQ_BASE + 4)
-#define MPC52xx_IRDA_IRQ		(MPC52xx_PERP_IRQ_BASE + 4)
-#define MPC52xx_FEC_IRQ			(MPC52xx_PERP_IRQ_BASE + 5)
-#define MPC52xx_USB_IRQ			(MPC52xx_PERP_IRQ_BASE + 6)
-#define MPC52xx_ATA_IRQ			(MPC52xx_PERP_IRQ_BASE + 7)
-#define MPC52xx_PCI_CNTRL_IRQ		(MPC52xx_PERP_IRQ_BASE + 8)
-#define MPC52xx_PCI_SCIRX_IRQ		(MPC52xx_PERP_IRQ_BASE + 9)
-#define MPC52xx_PCI_SCITX_IRQ		(MPC52xx_PERP_IRQ_BASE + 10)
-#define MPC52xx_PSC4_IRQ		(MPC52xx_PERP_IRQ_BASE + 11)
-#define MPC52xx_PSC5_IRQ		(MPC52xx_PERP_IRQ_BASE + 12)
-#define MPC52xx_SPI_MODF_IRQ		(MPC52xx_PERP_IRQ_BASE + 13)
-#define MPC52xx_SPI_SPIF_IRQ		(MPC52xx_PERP_IRQ_BASE + 14)
-#define MPC52xx_I2C1_IRQ		(MPC52xx_PERP_IRQ_BASE + 15)
-#define MPC52xx_I2C2_IRQ		(MPC52xx_PERP_IRQ_BASE + 16)
-#define MPC52xx_MSCAN1_IRQ		(MPC52xx_PERP_IRQ_BASE + 17)
-#define MPC52xx_MSCAN2_IRQ		(MPC52xx_PERP_IRQ_BASE + 18)
-#define MPC52xx_IR_RX_IRQ		(MPC52xx_PERP_IRQ_BASE + 19)
-#define MPC52xx_IR_TX_IRQ		(MPC52xx_PERP_IRQ_BASE + 20)
-#define MPC52xx_XLB_ARB_IRQ		(MPC52xx_PERP_IRQ_BASE + 21)
-#define MPC52xx_BDLC_IRQ		(MPC52xx_PERP_IRQ_BASE + 22)
-
-
-
-/* ======================================================================== */
-/* Structures mapping of some unit register set                             */
-/* ======================================================================== */
-
-#ifndef __ASSEMBLY__
-
-/* Memory Mapping Control */
-struct mpc52xx_mmap_ctl {
-	u32	mbar;		/* MMAP_CTRL + 0x00 */
-
-	u32	cs0_start;	/* MMAP_CTRL + 0x04 */
-	u32	cs0_stop;	/* MMAP_CTRL + 0x08 */
-	u32	cs1_start;	/* MMAP_CTRL + 0x0c */
-	u32	cs1_stop;	/* MMAP_CTRL + 0x10 */
-	u32	cs2_start;	/* MMAP_CTRL + 0x14 */
-	u32	cs2_stop;	/* MMAP_CTRL + 0x18 */
-	u32	cs3_start;	/* MMAP_CTRL + 0x1c */
-	u32	cs3_stop;	/* MMAP_CTRL + 0x20 */
-	u32	cs4_start;	/* MMAP_CTRL + 0x24 */
-	u32	cs4_stop;	/* MMAP_CTRL + 0x28 */
-	u32	cs5_start;	/* MMAP_CTRL + 0x2c */
-	u32	cs5_stop;	/* MMAP_CTRL + 0x30 */
-
-	u32	sdram0;		/* MMAP_CTRL + 0x34 */
-	u32	sdram1;		/* MMAP_CTRL + 0X38 */
-
-	u32	reserved[4];	/* MMAP_CTRL + 0x3c .. 0x48 */
-
-	u32	boot_start;	/* MMAP_CTRL + 0x4c */
-	u32	boot_stop;	/* MMAP_CTRL + 0x50 */
-
-	u32	ipbi_ws_ctrl;	/* MMAP_CTRL + 0x54 */
-
-	u32	cs6_start;	/* MMAP_CTRL + 0x58 */
-	u32	cs6_stop;	/* MMAP_CTRL + 0x5c */
-	u32	cs7_start;	/* MMAP_CTRL + 0x60 */
-	u32	cs7_stop;	/* MMAP_CTRL + 0x64 */
-};
-
-/* SDRAM control */
-struct mpc52xx_sdram {
-	u32	mode;		/* SDRAM + 0x00 */
-	u32	ctrl;		/* SDRAM + 0x04 */
-	u32	config1;	/* SDRAM + 0x08 */
-	u32	config2;	/* SDRAM + 0x0c */
-};
-
-/* Interrupt controller */
-struct mpc52xx_intr {
-	u32	per_mask;	/* INTR + 0x00 */
-	u32	per_pri1;	/* INTR + 0x04 */
-	u32	per_pri2;	/* INTR + 0x08 */
-	u32	per_pri3;	/* INTR + 0x0c */
-	u32	ctrl;		/* INTR + 0x10 */
-	u32	main_mask;	/* INTR + 0x14 */
-	u32	main_pri1;	/* INTR + 0x18 */
-	u32	main_pri2;	/* INTR + 0x1c */
-	u32	reserved1;	/* INTR + 0x20 */
-	u32	enc_status;	/* INTR + 0x24 */
-	u32	crit_status;	/* INTR + 0x28 */
-	u32	main_status;	/* INTR + 0x2c */
-	u32	per_status;	/* INTR + 0x30 */
-	u32	reserved2;	/* INTR + 0x34 */
-	u32	per_error;	/* INTR + 0x38 */
-};
-
-/* SDMA */
-struct mpc52xx_sdma {
-	u32	taskBar;	/* SDMA + 0x00 */
-	u32	currentPointer;	/* SDMA + 0x04 */
-	u32	endPointer;	/* SDMA + 0x08 */
-	u32	variablePointer;/* SDMA + 0x0c */
-
-	u8	IntVect1;	/* SDMA + 0x10 */
-	u8	IntVect2;	/* SDMA + 0x11 */
-	u16	PtdCntrl;	/* SDMA + 0x12 */
-
-	u32	IntPend;	/* SDMA + 0x14 */
-	u32	IntMask;	/* SDMA + 0x18 */
-
-	u16	tcr[16];	/* SDMA + 0x1c .. 0x3a */
-
-	u8	ipr[32];	/* SDMA + 0x3c .. 0x5b */
-
-	u32	cReqSelect;	/* SDMA + 0x5c */
-	u32	task_size0;	/* SDMA + 0x60 */
-	u32	task_size1;	/* SDMA + 0x64 */
-	u32	MDEDebug;	/* SDMA + 0x68 */
-	u32	ADSDebug;	/* SDMA + 0x6c */
-	u32	Value1;		/* SDMA + 0x70 */
-	u32	Value2;		/* SDMA + 0x74 */
-	u32	Control;	/* SDMA + 0x78 */
-	u32	Status;		/* SDMA + 0x7c */
-	u32	PTDDebug;	/* SDMA + 0x80 */
-};
-
-/* GPT */
-struct mpc52xx_gpt {
-	u32	mode;		/* GPTx + 0x00 */
-	u32	count;		/* GPTx + 0x04 */
-	u32	pwm;		/* GPTx + 0x08 */
-	u32	status;		/* GPTx + 0X0c */
-};
-
-/* RTC */
-struct mpc52xx_rtc {
-	u32	time_set;	/* RTC + 0x00 */
-	u32	date_set;	/* RTC + 0x04 */
-	u32	stopwatch;	/* RTC + 0x08 */
-	u32	int_enable;	/* RTC + 0x0c */
-	u32	time;		/* RTC + 0x10 */
-	u32	date;		/* RTC + 0x14 */
-	u32	stopwatch_intr;	/* RTC + 0x18 */
-	u32	bus_error;	/* RTC + 0x1c */
-	u32	dividers;	/* RTC + 0x20 */
-};
-
-/* GPIO */
-struct mpc52xx_gpio {
-	u32	port_config;	/* GPIO + 0x00 */
-	u32	simple_gpioe;	/* GPIO + 0x04 */
-	u32	simple_ode;	/* GPIO + 0x08 */
-	u32	simple_ddr;	/* GPIO + 0x0c */
-	u32	simple_dvo;	/* GPIO + 0x10 */
-	u32	simple_ival;	/* GPIO + 0x14 */
-	u8	outo_gpioe;	/* GPIO + 0x18 */
-	u8	reserved1[3];	/* GPIO + 0x19 */
-	u8	outo_dvo;	/* GPIO + 0x1c */
-	u8	reserved2[3];	/* GPIO + 0x1d */
-	u8	sint_gpioe;	/* GPIO + 0x20 */
-	u8	reserved3[3];	/* GPIO + 0x21 */
-	u8	sint_ode;	/* GPIO + 0x24 */
-	u8	reserved4[3];	/* GPIO + 0x25 */
-	u8	sint_ddr;	/* GPIO + 0x28 */
-	u8	reserved5[3];	/* GPIO + 0x29 */
-	u8	sint_dvo;	/* GPIO + 0x2c */
-	u8	reserved6[3];	/* GPIO + 0x2d */
-	u8	sint_inten;	/* GPIO + 0x30 */
-	u8	reserved7[3];	/* GPIO + 0x31 */
-	u16	sint_itype;	/* GPIO + 0x34 */
-	u16	reserved8;	/* GPIO + 0x36 */
-	u8	gpio_control;	/* GPIO + 0x38 */
-	u8	reserved9[3];	/* GPIO + 0x39 */
-	u8	sint_istat;	/* GPIO + 0x3c */
-	u8	sint_ival;	/* GPIO + 0x3d */
-	u8	bus_errs;	/* GPIO + 0x3e */
-	u8	reserved10;	/* GPIO + 0x3f */
-};
-
-#define MPC52xx_GPIO_PSC_CONFIG_UART_WITHOUT_CD	4
-#define MPC52xx_GPIO_PSC_CONFIG_UART_WITH_CD	5
-#define MPC52xx_GPIO_PCI_DIS			(1<<15)
-
-/* GPIO with WakeUp*/
-struct mpc52xx_gpio_wkup {
-	u8	wkup_gpioe;	/* GPIO_WKUP + 0x00 */
-	u8	reserved1[3];	/* GPIO_WKUP + 0x03 */
-	u8	wkup_ode;	/* GPIO_WKUP + 0x04 */
-	u8	reserved2[3];	/* GPIO_WKUP + 0x05 */
-	u8	wkup_ddr;	/* GPIO_WKUP + 0x08 */
-	u8	reserved3[3];	/* GPIO_WKUP + 0x09 */
-	u8	wkup_dvo;	/* GPIO_WKUP + 0x0C */
-	u8	reserved4[3];	/* GPIO_WKUP + 0x0D */
-	u8	wkup_inten;	/* GPIO_WKUP + 0x10 */
-	u8	reserved5[3];	/* GPIO_WKUP + 0x11 */
-	u8	wkup_iinten;	/* GPIO_WKUP + 0x14 */
-	u8	reserved6[3];	/* GPIO_WKUP + 0x15 */
-	u16	wkup_itype;	/* GPIO_WKUP + 0x18 */
-	u8	reserved7[2];	/* GPIO_WKUP + 0x1A */
-	u8	wkup_maste;	/* GPIO_WKUP + 0x1C */
-	u8	reserved8[3];	/* GPIO_WKUP + 0x1D */
-	u8	wkup_ival;	/* GPIO_WKUP + 0x20 */
-	u8	reserved9[3];	/* GPIO_WKUP + 0x21 */
-	u8	wkup_istat;	/* GPIO_WKUP + 0x24 */
-	u8	reserved10[3];	/* GPIO_WKUP + 0x25 */
-};
-
-/* XLB Bus control */
-struct mpc52xx_xlb {
-	u8	reserved[0x40];
-	u32	config;			/* XLB + 0x40 */
-	u32	version;		/* XLB + 0x44 */
-	u32	status;			/* XLB + 0x48 */
-	u32	int_enable;		/* XLB + 0x4c */
-	u32	addr_capture;		/* XLB + 0x50 */
-	u32	bus_sig_capture;	/* XLB + 0x54 */
-	u32	addr_timeout;		/* XLB + 0x58 */
-	u32	data_timeout;		/* XLB + 0x5c */
-	u32	bus_act_timeout;	/* XLB + 0x60 */
-	u32	master_pri_enable;	/* XLB + 0x64 */
-	u32	master_priority;	/* XLB + 0x68 */
-	u32	base_address;		/* XLB + 0x6c */
-	u32	snoop_window;		/* XLB + 0x70 */
-};
-
-#define MPC52xx_XLB_CFG_PLDIS		(1 << 31)
-#define MPC52xx_XLB_CFG_SNOOP		(1 << 15)
-
-/* Clock Distribution control */
-struct mpc52xx_cdm {
-	u32	jtag_id;		/* CDM + 0x00  reg0 read only */
-	u32	rstcfg;			/* CDM + 0x04  reg1 read only */
-	u32	breadcrumb;		/* CDM + 0x08  reg2 */
-
-	u8	mem_clk_sel;		/* CDM + 0x0c  reg3 byte0 */
-	u8	xlb_clk_sel;		/* CDM + 0x0d  reg3 byte1 read only */
-	u8	ipb_clk_sel;		/* CDM + 0x0e  reg3 byte2 */
-	u8	pci_clk_sel;		/* CDM + 0x0f  reg3 byte3 */
-
-	u8	ext_48mhz_en;		/* CDM + 0x10  reg4 byte0 */
-	u8	fd_enable;		/* CDM + 0x11  reg4 byte1 */
-	u16	fd_counters;		/* CDM + 0x12  reg4 byte2,3 */
-
-	u32	clk_enables;		/* CDM + 0x14  reg5 */
-
-	u8	osc_disable;		/* CDM + 0x18  reg6 byte0 */
-	u8	reserved0[3];		/* CDM + 0x19  reg6 byte1,2,3 */
-
-	u8	ccs_sleep_enable;	/* CDM + 0x1c  reg7 byte0 */
-	u8	osc_sleep_enable;	/* CDM + 0x1d  reg7 byte1 */
-	u8	reserved1;		/* CDM + 0x1e  reg7 byte2 */
-	u8	ccs_qreq_test;		/* CDM + 0x1f  reg7 byte3 */
-
-	u8	soft_reset;		/* CDM + 0x20  u8 byte0 */
-	u8	no_ckstp;		/* CDM + 0x21  u8 byte0 */
-	u8	reserved2[2];		/* CDM + 0x22  u8 byte1,2,3 */
-
-	u8	pll_lock;		/* CDM + 0x24  reg9 byte0 */
-	u8	pll_looselock;		/* CDM + 0x25  reg9 byte1 */
-	u8	pll_sm_lockwin;		/* CDM + 0x26  reg9 byte2 */
-	u8	reserved3;		/* CDM + 0x27  reg9 byte3 */
-
-	u16	reserved4;		/* CDM + 0x28  reg10 byte0,1 */
-	u16	mclken_div_psc1;	/* CDM + 0x2a  reg10 byte2,3 */
-
-	u16	reserved5;		/* CDM + 0x2c  reg11 byte0,1 */
-	u16	mclken_div_psc2;	/* CDM + 0x2e  reg11 byte2,3 */
-
-	u16	reserved6;		/* CDM + 0x30  reg12 byte0,1 */
-	u16	mclken_div_psc3;	/* CDM + 0x32  reg12 byte2,3 */
-
-	u16	reserved7;		/* CDM + 0x34  reg13 byte0,1 */
-	u16	mclken_div_psc6;	/* CDM + 0x36  reg13 byte2,3 */
-};
-
-#endif /* __ASSEMBLY__ */
-
-
-/* ========================================================================= */
-/* Prototypes for MPC52xx syslib                                             */
-/* ========================================================================= */
-
-#ifndef __ASSEMBLY__
-
-extern void mpc52xx_init_irq(void);
-extern int mpc52xx_get_irq(void);
-
-extern unsigned long mpc52xx_find_end_of_memory(void);
-extern void mpc52xx_set_bat(void);
-extern void mpc52xx_map_io(void);
-extern void mpc52xx_restart(char *cmd);
-extern void mpc52xx_halt(void);
-extern void mpc52xx_power_off(void);
-extern void mpc52xx_progress(char *s, unsigned short hex);
-extern void mpc52xx_calibrate_decr(void);
-
-extern void mpc52xx_find_bridges(void);
-
-extern void mpc52xx_setup_cpu(void);
-
-
-
-	/* Matching of PSC function */
-struct mpc52xx_psc_func {
-	int id;
-	char *func;
-};
-
-extern int mpc52xx_match_psc_function(int psc_idx, const char *func);
-extern struct  mpc52xx_psc_func mpc52xx_psc_functions[];
-	/* This array is to be defined in platform file */
-
-#endif /* __ASSEMBLY__ */
-
-
-/* ========================================================================= */
-/* Platform configuration                                                    */
-/* ========================================================================= */
-
-/* The U-Boot platform information struct */
-extern bd_t __res;
-
-/* Platform options */
-#if defined(CONFIG_LITE5200)
-#include <platforms/lite5200.h>
-#endif
-
-
-#endif /* __ASM_MPC52xx_H__ */
diff --git a/include/asm-ppc/mpc52xx_psc.h b/include/asm-ppc/mpc52xx_psc.h
deleted file mode 100644
index 39fcd02cd4e..00000000000
--- a/include/asm-ppc/mpc52xx_psc.h
+++ /dev/null
@@ -1,200 +0,0 @@
-/*
- * include/asm-ppc/mpc52xx_psc.h
- * 
- * Definitions of consts/structs to drive the Freescale MPC52xx OnChip
- * PSCs. Theses are shared between multiple drivers since a PSC can be
- * UART, AC97, IR, I2S, ... So this header is in asm-ppc.
- *
- *
- * Maintainer : Sylvain Munaut <tnt@246tNt.com>
- *
- * Based/Extracted from some header of the 2.4 originally written by 
- * Dale Farnsworth <dfarnsworth@mvista.com> 
- *
- * Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
- * Copyright (C) 2003 MontaVista, Software, Inc.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-#ifndef __ASM_MPC52xx_PSC_H__
-#define __ASM_MPC52xx_PSC_H__
-
-#include <asm/types.h>
-
-/* Max number of PSCs */
-#define MPC52xx_PSC_MAXNUM	6
-
-/* Programmable Serial Controller (PSC) status register bits */
-#define MPC52xx_PSC_SR_UNEX_RX	0x0001
-#define MPC52xx_PSC_SR_DATA_VAL	0x0002
-#define MPC52xx_PSC_SR_DATA_OVR	0x0004
-#define MPC52xx_PSC_SR_CMDSEND	0x0008
-#define MPC52xx_PSC_SR_CDE	0x0080
-#define MPC52xx_PSC_SR_RXRDY	0x0100
-#define MPC52xx_PSC_SR_RXFULL	0x0200
-#define MPC52xx_PSC_SR_TXRDY	0x0400
-#define MPC52xx_PSC_SR_TXEMP	0x0800
-#define MPC52xx_PSC_SR_OE	0x1000
-#define MPC52xx_PSC_SR_PE	0x2000
-#define MPC52xx_PSC_SR_FE	0x4000
-#define MPC52xx_PSC_SR_RB	0x8000
-
-/* PSC Command values */
-#define MPC52xx_PSC_RX_ENABLE		0x0001
-#define MPC52xx_PSC_RX_DISABLE		0x0002
-#define MPC52xx_PSC_TX_ENABLE		0x0004
-#define MPC52xx_PSC_TX_DISABLE		0x0008
-#define MPC52xx_PSC_SEL_MODE_REG_1	0x0010
-#define MPC52xx_PSC_RST_RX		0x0020
-#define MPC52xx_PSC_RST_TX		0x0030
-#define MPC52xx_PSC_RST_ERR_STAT	0x0040
-#define MPC52xx_PSC_RST_BRK_CHG_INT	0x0050
-#define MPC52xx_PSC_START_BRK		0x0060
-#define MPC52xx_PSC_STOP_BRK		0x0070
-
-/* PSC TxRx FIFO status bits */
-#define MPC52xx_PSC_RXTX_FIFO_ERR	0x0040
-#define MPC52xx_PSC_RXTX_FIFO_UF	0x0020
-#define MPC52xx_PSC_RXTX_FIFO_OF	0x0010
-#define MPC52xx_PSC_RXTX_FIFO_FR	0x0008
-#define MPC52xx_PSC_RXTX_FIFO_FULL	0x0004
-#define MPC52xx_PSC_RXTX_FIFO_ALARM	0x0002
-#define MPC52xx_PSC_RXTX_FIFO_EMPTY	0x0001
-
-/* PSC interrupt mask bits */
-#define MPC52xx_PSC_IMR_TXRDY		0x0100
-#define MPC52xx_PSC_IMR_RXRDY		0x0200
-#define MPC52xx_PSC_IMR_DB		0x0400
-#define MPC52xx_PSC_IMR_IPC		0x8000
-
-/* PSC input port change bit */
-#define MPC52xx_PSC_CTS			0x01
-#define MPC52xx_PSC_DCD			0x02
-#define MPC52xx_PSC_D_CTS		0x10
-#define MPC52xx_PSC_D_DCD		0x20
-
-/* PSC mode fields */
-#define MPC52xx_PSC_MODE_5_BITS			0x00
-#define MPC52xx_PSC_MODE_6_BITS			0x01
-#define MPC52xx_PSC_MODE_7_BITS			0x02
-#define MPC52xx_PSC_MODE_8_BITS			0x03
-#define MPC52xx_PSC_MODE_BITS_MASK		0x03
-#define MPC52xx_PSC_MODE_PAREVEN		0x00
-#define MPC52xx_PSC_MODE_PARODD			0x04
-#define MPC52xx_PSC_MODE_PARFORCE		0x08
-#define MPC52xx_PSC_MODE_PARNONE		0x10
-#define MPC52xx_PSC_MODE_ERR			0x20
-#define MPC52xx_PSC_MODE_FFULL			0x40
-#define MPC52xx_PSC_MODE_RXRTS			0x80
-
-#define MPC52xx_PSC_MODE_ONE_STOP_5_BITS	0x00
-#define MPC52xx_PSC_MODE_ONE_STOP		0x07
-#define MPC52xx_PSC_MODE_TWO_STOP		0x0f
-
-#define MPC52xx_PSC_RFNUM_MASK	0x01ff
-
-
-/* Structure of the hardware registers */
-struct mpc52xx_psc {
-	u8		mode;		/* PSC + 0x00 */
-	u8		reserved0[3];
-	union {				/* PSC + 0x04 */
-		u16	status;
-		u16	clock_select;
-	} sr_csr;
-#define mpc52xx_psc_status	sr_csr.status
-#define mpc52xx_psc_clock_select sr_csr.clock_select
-	u16		reserved1;
-	u8		command;	/* PSC + 0x08 */
-	u8		reserved2[3];
-	union {				/* PSC + 0x0c */
-		u8	buffer_8;
-		u16	buffer_16;
-		u32	buffer_32;
-	} buffer;
-#define mpc52xx_psc_buffer_8	buffer.buffer_8
-#define mpc52xx_psc_buffer_16	buffer.buffer_16
-#define mpc52xx_psc_buffer_32	buffer.buffer_32
-	union {				/* PSC + 0x10 */
-		u8	ipcr;
-		u8	acr;
-	} ipcr_acr;
-#define mpc52xx_psc_ipcr	ipcr_acr.ipcr
-#define mpc52xx_psc_acr		ipcr_acr.acr
-	u8		reserved3[3];
-	union {				/* PSC + 0x14 */
-		u16	isr;
-		u16	imr;
-	} isr_imr;
-#define mpc52xx_psc_isr		isr_imr.isr
-#define mpc52xx_psc_imr		isr_imr.imr
-	u16		reserved4;
-	u8		ctur;		/* PSC + 0x18 */
-	u8		reserved5[3];
-	u8		ctlr;		/* PSC + 0x1c */
-	u8		reserved6[3];
-	u32		ccr;		/* PSC + 0x20 */
-	u32		ac97_slots;	/* PSC + 0x24 */
-	u32		ac97_cmd;	/* PSC + 0x28 */
-	u32		ac97_data;	/* PSC + 0x2c */
-	u8		ivr;		/* PSC + 0x30 */
-	u8		reserved8[3];
-	u8		ip;		/* PSC + 0x34 */
-	u8		reserved9[3];
-	u8		op1;		/* PSC + 0x38 */
-	u8		reserved10[3];
-	u8		op0;		/* PSC + 0x3c */
-	u8		reserved11[3];
-	u32		sicr;		/* PSC + 0x40 */
-	u8		ircr1;		/* PSC + 0x44 */
-	u8		reserved13[3];
-	u8		ircr2;		/* PSC + 0x44 */
-	u8		reserved14[3];
-	u8		irsdr;		/* PSC + 0x4c */
-	u8		reserved15[3];
-	u8		irmdr;		/* PSC + 0x50 */
-	u8		reserved16[3];
-	u8		irfdr;		/* PSC + 0x54 */
-	u8		reserved17[3];
-};
-
-struct mpc52xx_psc_fifo {
-	u16		rfnum;		/* PSC + 0x58 */
-	u16		reserved18;
-	u16		tfnum;		/* PSC + 0x5c */
-	u16		reserved19;
-	u32		rfdata;		/* PSC + 0x60 */
-	u16		rfstat;		/* PSC + 0x64 */
-	u16		reserved20;
-	u8		rfcntl;		/* PSC + 0x68 */
-	u8		reserved21[5];
-	u16		rfalarm;	/* PSC + 0x6e */
-	u16		reserved22;
-	u16		rfrptr;		/* PSC + 0x72 */
-	u16		reserved23;
-	u16		rfwptr;		/* PSC + 0x76 */
-	u16		reserved24;
-	u16		rflrfptr;	/* PSC + 0x7a */
-	u16		reserved25;
-	u16		rflwfptr;	/* PSC + 0x7e */
-	u32		tfdata;		/* PSC + 0x80 */
-	u16		tfstat;		/* PSC + 0x84 */
-	u16		reserved26;
-	u8		tfcntl;		/* PSC + 0x88 */
-	u8		reserved27[5];
-	u16		tfalarm;	/* PSC + 0x8e */
-	u16		reserved28;
-	u16		tfrptr;		/* PSC + 0x92 */
-	u16		reserved29;
-	u16		tfwptr;		/* PSC + 0x96 */
-	u16		reserved30;
-	u16		tflrfptr;	/* PSC + 0x9a */
-	u16		reserved31;
-	u16		tflwfptr;	/* PSC + 0x9e */
-};
-
-
-#endif  /* __ASM_MPC52xx_PSC_H__ */
diff --git a/include/asm-ppc/mpc8260.h b/include/asm-ppc/mpc8260.h
deleted file mode 100644
index 402ba15c2e8..00000000000
--- a/include/asm-ppc/mpc8260.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * Since there are many different boards and no standard configuration,
- * we have a unique include file for each.  Rather than change every
- * file that has to include MPC8260 configuration, they all include
- * this one and the configuration switching is done here.
- */
-#ifdef __KERNEL__
-#ifndef __ASM_PPC_MPC8260_H__
-#define __ASM_PPC_MPC8260_H__
-
-
-#ifdef CONFIG_8260
-
-#ifdef CONFIG_EST8260
-#include <platforms/est8260.h>
-#endif
-
-#ifdef CONFIG_SBC82xx
-#include <platforms/sbc82xx.h>
-#endif
-
-#ifdef CONFIG_SBS8260
-#include <platforms/sbs8260.h>
-#endif
-
-#ifdef CONFIG_RPX8260
-#include <platforms/rpx8260.h>
-#endif
-
-#ifdef CONFIG_WILLOW
-#include <platforms/willow.h>
-#endif
-
-#ifdef CONFIG_TQM8260
-#include <platforms/tqm8260.h>
-#endif
-
-#ifdef CONFIG_PCI_8260
-#include <syslib/m82xx_pci.h>
-#endif
-
-/* Make sure the memory translation stuff is there if PCI not used.
- */
-#ifndef _IO_BASE
-#define _IO_BASE        0
-#endif
-
-#ifndef _ISA_MEM_BASE
-#define _ISA_MEM_BASE   0
-#endif
-
-#ifndef PCI_DRAM_OFFSET
-#define PCI_DRAM_OFFSET 0
-#endif
-
-/* Map 256MB I/O region
- */
-#ifndef IO_PHYS_ADDR
-#define IO_PHYS_ADDR	0xe0000000
-#endif
-#ifndef IO_VIRT_ADDR
-#define IO_VIRT_ADDR	IO_PHYS_ADDR
-#endif
-
-enum ppc_sys_devices {
-	MPC82xx_CPM_FCC1,
-	MPC82xx_CPM_FCC2,
-	MPC82xx_CPM_FCC3,
-	MPC82xx_CPM_I2C,
-	MPC82xx_CPM_SCC1,
-	MPC82xx_CPM_SCC2,
-	MPC82xx_CPM_SCC3,
-	MPC82xx_CPM_SCC4,
-	MPC82xx_CPM_SPI,
-	MPC82xx_CPM_MCC1,
-	MPC82xx_CPM_MCC2,
-	MPC82xx_CPM_SMC1,
-	MPC82xx_CPM_SMC2,
-	MPC82xx_CPM_USB,
-	MPC82xx_SEC1,
-	MPC82xx_MDIO_BB,
-	NUM_PPC_SYS_DEVS,
-};
-
-#ifndef __ASSEMBLY__
-/* The "residual" data board information structure the boot loader
- * hands to us.
- */
-extern unsigned char __res[];
-#endif
-
-#ifndef BOARD_CHIP_NAME
-#define BOARD_CHIP_NAME ""
-#endif
-
-#endif /* CONFIG_8260 */
-#endif /* !__ASM_PPC_MPC8260_H__ */
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/mpc8260_pci9.h b/include/asm-ppc/mpc8260_pci9.h
deleted file mode 100644
index 9f7176881c5..00000000000
--- a/include/asm-ppc/mpc8260_pci9.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/* include/asm-ppc/mpc8260_pci9.h
- *
- * Undefine the PCI read* and in* macros so we can define them as functions
- * that implement the workaround for the MPC8260 device erratum PCI 9.
- *
- * This header file should only be included at the end of include/asm-ppc/io.h
- * and never included directly anywhere else.
- *
- * Author:  andy_lowe@mvista.com
- *
- * 2003 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifndef _PPC_IO_H
-#error "Do not include mpc8260_pci9.h directly."
-#endif
-
-#ifdef __KERNEL__
-#ifndef __CONFIG_8260_PCI9_DEFS
-#define __CONFIG_8260_PCI9_DEFS
-
-#undef readb
-#undef readw
-#undef readl
-#undef insb
-#undef insw
-#undef insl
-#undef inb
-#undef inw
-#undef inl
-#undef memcpy_fromio
-
-extern int readb(volatile unsigned char *addr);
-extern int readw(volatile unsigned short *addr);
-extern unsigned readl(volatile unsigned *addr);
-extern void insb(unsigned port, void *buf, int ns);
-extern void insw(unsigned port, void *buf, int ns);
-extern void insl(unsigned port, void *buf, int nl);
-extern int inb(unsigned port);
-extern int inw(unsigned port);
-extern unsigned inl(unsigned port);
-extern void *memcpy_fromio(void *dest, unsigned long src, size_t count);
-
-#endif /* !__CONFIG_8260_PCI9_DEFS */
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/mpc8xx.h b/include/asm-ppc/mpc8xx.h
deleted file mode 100644
index b9e3060b027..00000000000
--- a/include/asm-ppc/mpc8xx.h
+++ /dev/null
@@ -1,122 +0,0 @@
-/* This is the single file included by all MPC8xx build options.
- * Since there are many different boards and no standard configuration,
- * we have a unique include file for each.  Rather than change every
- * file that has to include MPC8xx configuration, they all include
- * this one and the configuration switching is done here.
- */
-#ifdef __KERNEL__
-#ifndef __CONFIG_8xx_DEFS
-#define __CONFIG_8xx_DEFS
-
-
-#ifdef CONFIG_8xx
-
-#ifdef CONFIG_MBX
-#include <platforms/mbx.h>
-#endif
-
-#ifdef CONFIG_FADS
-#include <platforms/fads.h>
-#endif
-
-#ifdef CONFIG_RPXLITE
-#include <platforms/rpxlite.h>
-#endif
-
-#ifdef CONFIG_BSEIP
-#include <platforms/bseip.h>
-#endif
-
-#ifdef CONFIG_RPXCLASSIC
-#include <platforms/rpxclassic.h>
-#endif
-
-#if defined(CONFIG_TQM8xxL)
-#include <platforms/tqm8xx.h>
-#endif
-
-#if defined(CONFIG_IVMS8) || defined(CONFIG_IVML24)
-#include <platforms/ivms8.h>
-#endif
-
-#if defined(CONFIG_HERMES_PRO)
-#include <platforms/hermes.h>
-#endif
-
-#if defined(CONFIG_IP860)
-#include <platforms/ip860.h>
-#endif
-
-#if defined(CONFIG_LWMON)
-#include <platforms/lwmon.h>
-#endif
-
-#if defined(CONFIG_PCU_E)
-#include <platforms/pcu_e.h>
-#endif
-
-#if defined(CONFIG_CCM)
-#include <platforms/ccm.h>
-#endif
-
-#if defined(CONFIG_LANTEC)
-#include <platforms/lantec.h>
-#endif
-
-/* Currently, all 8xx boards that support a processor to PCI/ISA bridge
- * use the same memory map.
- */
-#if 0
-#if defined(CONFIG_PCI) && defined(PCI_ISA_IO_ADDR)
-#define	_IO_BASE PCI_ISA_IO_ADDR
-#define	_ISA_MEM_BASE PCI_ISA_MEM_ADDR
-#define PCI_DRAM_OFFSET 0x80000000
-#else
-#define _IO_BASE        0
-#define _ISA_MEM_BASE   0
-#define PCI_DRAM_OFFSET 0
-#endif
-#else
-#if !defined(_IO_BASE)  /* defined in board specific header */
-#define _IO_BASE        0
-#endif
-#define _ISA_MEM_BASE   0
-#define PCI_DRAM_OFFSET 0
-#endif
-
-#ifndef __ASSEMBLY__
-/* The "residual" data board information structure the boot loader
- * hands to us.
- */
-extern unsigned char __res[];
-
-struct pt_regs;
-
-enum ppc_sys_devices {
-	MPC8xx_CPM_FEC1,
-	MPC8xx_CPM_FEC2,
-	MPC8xx_CPM_I2C,
-	MPC8xx_CPM_SCC1,
-	MPC8xx_CPM_SCC2,
-	MPC8xx_CPM_SCC3,
-	MPC8xx_CPM_SCC4,
-	MPC8xx_CPM_SPI,
-	MPC8xx_CPM_MCC1,
-	MPC8xx_CPM_MCC2,
-	MPC8xx_CPM_SMC1,
-	MPC8xx_CPM_SMC2,
-	MPC8xx_CPM_USB,
-	MPC8xx_MDIO_FEC,
-	NUM_PPC_SYS_DEVS,
-};
-
-#define PPC_PIN_SIZE	(24 * 1024 * 1024)	/* 24Mbytes of data pinned */
-
-#ifndef BOARD_CHIP_NAME
-#define BOARD_CHIP_NAME ""
-#endif
-
-#endif /* !__ASSEMBLY__ */
-#endif /* CONFIG_8xx */
-#endif /* __CONFIG_8xx_DEFS */
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/mv64x60.h b/include/asm-ppc/mv64x60.h
deleted file mode 100644
index 2963d6aa3ea..00000000000
--- a/include/asm-ppc/mv64x60.h
+++ /dev/null
@@ -1,353 +0,0 @@
-/*
- * include/asm-ppc/mv64x60.h
- *
- * Prototypes, etc. for the Marvell/Galileo MV64x60 host bridge routines.
- *
- * Author: Mark A. Greer <mgreer@mvista.com>
- *
- * 2001-2002 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifndef __ASMPPC_MV64x60_H
-#define __ASMPPC_MV64x60_H
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/pci.h>
-#include <linux/slab.h>
-
-#include <asm/byteorder.h>
-#include <asm/io.h>
-#include <asm/irq.h>
-#include <asm/uaccess.h>
-#include <asm/machdep.h>
-#include <asm/pci-bridge.h>
-#include <asm/mv64x60_defs.h>
-
-struct platform_device;
-
-extern u8	mv64x60_pci_exclude_bridge;
-
-extern spinlock_t mv64x60_lock;
-
-/* 32-bit Window table entry defines */
-#define	MV64x60_CPU2MEM_0_WIN			0
-#define	MV64x60_CPU2MEM_1_WIN			1
-#define	MV64x60_CPU2MEM_2_WIN			2
-#define	MV64x60_CPU2MEM_3_WIN			3
-#define	MV64x60_CPU2DEV_0_WIN			4
-#define	MV64x60_CPU2DEV_1_WIN			5
-#define	MV64x60_CPU2DEV_2_WIN			6
-#define	MV64x60_CPU2DEV_3_WIN			7
-#define	MV64x60_CPU2BOOT_WIN			8
-#define	MV64x60_CPU2PCI0_IO_WIN			9
-#define	MV64x60_CPU2PCI0_MEM_0_WIN		10
-#define	MV64x60_CPU2PCI0_MEM_1_WIN		11
-#define	MV64x60_CPU2PCI0_MEM_2_WIN		12
-#define	MV64x60_CPU2PCI0_MEM_3_WIN		13
-#define	MV64x60_CPU2PCI1_IO_WIN			14
-#define	MV64x60_CPU2PCI1_MEM_0_WIN		15
-#define	MV64x60_CPU2PCI1_MEM_1_WIN		16
-#define	MV64x60_CPU2PCI1_MEM_2_WIN		17
-#define	MV64x60_CPU2PCI1_MEM_3_WIN		18
-#define	MV64x60_CPU2SRAM_WIN			19
-#define	MV64x60_CPU2PCI0_IO_REMAP_WIN		20
-#define	MV64x60_CPU2PCI1_IO_REMAP_WIN		21
-#define	MV64x60_CPU_PROT_0_WIN			22
-#define	MV64x60_CPU_PROT_1_WIN			23
-#define	MV64x60_CPU_PROT_2_WIN			24
-#define	MV64x60_CPU_PROT_3_WIN			25
-#define	MV64x60_CPU_SNOOP_0_WIN			26
-#define	MV64x60_CPU_SNOOP_1_WIN			27
-#define	MV64x60_CPU_SNOOP_2_WIN			28
-#define	MV64x60_CPU_SNOOP_3_WIN			29
-#define	MV64x60_PCI02MEM_REMAP_0_WIN		30
-#define	MV64x60_PCI02MEM_REMAP_1_WIN		31
-#define	MV64x60_PCI02MEM_REMAP_2_WIN		32
-#define	MV64x60_PCI02MEM_REMAP_3_WIN		33
-#define	MV64x60_PCI12MEM_REMAP_0_WIN		34
-#define	MV64x60_PCI12MEM_REMAP_1_WIN		35
-#define	MV64x60_PCI12MEM_REMAP_2_WIN		36
-#define	MV64x60_PCI12MEM_REMAP_3_WIN		37
-#define	MV64x60_ENET2MEM_0_WIN			38
-#define	MV64x60_ENET2MEM_1_WIN			39
-#define	MV64x60_ENET2MEM_2_WIN			40
-#define	MV64x60_ENET2MEM_3_WIN			41
-#define	MV64x60_ENET2MEM_4_WIN			42
-#define	MV64x60_ENET2MEM_5_WIN			43
-#define	MV64x60_MPSC2MEM_0_WIN			44
-#define	MV64x60_MPSC2MEM_1_WIN			45
-#define	MV64x60_MPSC2MEM_2_WIN			46
-#define	MV64x60_MPSC2MEM_3_WIN			47
-#define	MV64x60_IDMA2MEM_0_WIN			48
-#define	MV64x60_IDMA2MEM_1_WIN			49
-#define	MV64x60_IDMA2MEM_2_WIN			50
-#define	MV64x60_IDMA2MEM_3_WIN			51
-#define	MV64x60_IDMA2MEM_4_WIN			52
-#define	MV64x60_IDMA2MEM_5_WIN			53
-#define	MV64x60_IDMA2MEM_6_WIN			54
-#define	MV64x60_IDMA2MEM_7_WIN			55
-
-#define	MV64x60_32BIT_WIN_COUNT			56
-
-/* 64-bit Window table entry defines */
-#define	MV64x60_CPU2PCI0_MEM_0_REMAP_WIN	0
-#define	MV64x60_CPU2PCI0_MEM_1_REMAP_WIN	1
-#define	MV64x60_CPU2PCI0_MEM_2_REMAP_WIN	2
-#define	MV64x60_CPU2PCI0_MEM_3_REMAP_WIN	3
-#define	MV64x60_CPU2PCI1_MEM_0_REMAP_WIN	4
-#define	MV64x60_CPU2PCI1_MEM_1_REMAP_WIN	5
-#define	MV64x60_CPU2PCI1_MEM_2_REMAP_WIN	6
-#define	MV64x60_CPU2PCI1_MEM_3_REMAP_WIN	7
-#define	MV64x60_PCI02MEM_ACC_CNTL_0_WIN		8
-#define	MV64x60_PCI02MEM_ACC_CNTL_1_WIN		9
-#define	MV64x60_PCI02MEM_ACC_CNTL_2_WIN		10
-#define	MV64x60_PCI02MEM_ACC_CNTL_3_WIN		11
-#define	MV64x60_PCI12MEM_ACC_CNTL_0_WIN		12
-#define	MV64x60_PCI12MEM_ACC_CNTL_1_WIN		13
-#define	MV64x60_PCI12MEM_ACC_CNTL_2_WIN		14
-#define	MV64x60_PCI12MEM_ACC_CNTL_3_WIN		15
-#define	MV64x60_PCI02MEM_SNOOP_0_WIN		16
-#define	MV64x60_PCI02MEM_SNOOP_1_WIN		17
-#define	MV64x60_PCI02MEM_SNOOP_2_WIN		18
-#define	MV64x60_PCI02MEM_SNOOP_3_WIN		19
-#define	MV64x60_PCI12MEM_SNOOP_0_WIN		20
-#define	MV64x60_PCI12MEM_SNOOP_1_WIN		21
-#define	MV64x60_PCI12MEM_SNOOP_2_WIN		22
-#define	MV64x60_PCI12MEM_SNOOP_3_WIN		23
-
-#define	MV64x60_64BIT_WIN_COUNT			24
-
-/*
- * Define a structure that's used to pass in config information to the
- * core routines.
- */
-struct mv64x60_pci_window {
-	u32	cpu_base;
-	u32	pci_base_hi;
-	u32	pci_base_lo;
-	u32	size;
-	u32	swap;
-};
-
-struct mv64x60_pci_info {
-	u8	enable_bus;	/* allow access to this PCI bus? */
-
-	struct mv64x60_pci_window	pci_io;
-	struct mv64x60_pci_window	pci_mem[3];
-
-	u32	acc_cntl_options[MV64x60_CPU2MEM_WINDOWS];
-	u32	snoop_options[MV64x60_CPU2MEM_WINDOWS];
-	u16	pci_cmd_bits;
-	u16	latency_timer;
-};
-
-struct mv64x60_setup_info {
-	u32	phys_reg_base;
-	u32	window_preserve_mask_32_hi;
-	u32	window_preserve_mask_32_lo;
-	u32	window_preserve_mask_64;
-
-	u32	cpu_prot_options[MV64x60_CPU2MEM_WINDOWS];
-	u32	cpu_snoop_options[MV64x60_CPU2MEM_WINDOWS];
-	u32	enet_options[MV64x60_CPU2MEM_WINDOWS];
-	u32	mpsc_options[MV64x60_CPU2MEM_WINDOWS];
-	u32	idma_options[MV64x60_CPU2MEM_WINDOWS];
-
-	struct mv64x60_pci_info	pci_0;
-	struct mv64x60_pci_info	pci_1;
-};
-
-/* Define what the top bits in the extra member of a window entry means. */
-#define	MV64x60_EXTRA_INVALID		0x00000000
-#define	MV64x60_EXTRA_CPUWIN_ENAB	0x10000000
-#define	MV64x60_EXTRA_CPUPROT_ENAB	0x20000000
-#define	MV64x60_EXTRA_ENET_ENAB		0x30000000
-#define	MV64x60_EXTRA_MPSC_ENAB		0x40000000
-#define	MV64x60_EXTRA_IDMA_ENAB		0x50000000
-#define	MV64x60_EXTRA_PCIACC_ENAB	0x60000000
-
-#define	MV64x60_EXTRA_MASK		0xf0000000
-
-/*
- * Define the 'handle' struct that will be passed between the 64x60 core
- * code and the platform-specific code that will use it.  The handle
- * will contain pointers to chip-specific routines & information.
- */
-struct mv64x60_32bit_window {
-	u32	base_reg;
-	u32	size_reg;
-	u8	base_bits;
-	u8	size_bits;
-	u32	(*get_from_field)(u32 val, u32 num_bits);
-	u32	(*map_to_field)(u32 val, u32 num_bits);
-	u32	extra;
-};
-
-struct mv64x60_64bit_window {
-	u32	base_hi_reg;
-	u32	base_lo_reg;
-	u32	size_reg;
-	u8	base_lo_bits;
-	u8	size_bits;
-	u32	(*get_from_field)(u32 val, u32 num_bits);
-	u32	(*map_to_field)(u32 val, u32 num_bits);
-	u32	extra;
-};
-
-typedef struct mv64x60_handle	mv64x60_handle_t;
-struct mv64x60_chip_info {
-	u32	(*translate_size)(u32 base, u32 size, u32 num_bits);
-	u32	(*untranslate_size)(u32 base, u32 size, u32 num_bits);
-	void	(*set_pci2mem_window)(struct pci_controller *hose, u32 bus,
-			u32 window, u32 base);
-	void 	(*set_pci2regs_window)(struct mv64x60_handle *bh,
-			struct pci_controller *hose, u32 bus, u32 base);
-	u32	(*is_enabled_32bit)(mv64x60_handle_t *bh, u32 window);
-	void	(*enable_window_32bit)(mv64x60_handle_t *bh, u32 window);
-	void	(*disable_window_32bit)(mv64x60_handle_t *bh, u32 window);
-	void	(*enable_window_64bit)(mv64x60_handle_t *bh, u32 window);
-	void	(*disable_window_64bit)(mv64x60_handle_t *bh, u32 window);
-	void	(*disable_all_windows)(mv64x60_handle_t *bh,
-			struct mv64x60_setup_info *si);
-	void	(*config_io2mem_windows)(mv64x60_handle_t *bh,
-			struct mv64x60_setup_info *si,
-			u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]);
-	void 	(*set_mpsc2regs_window)(struct mv64x60_handle *bh, u32 base);
-	void	(*chip_specific_init)(mv64x60_handle_t *bh,
-			struct mv64x60_setup_info *si);
-
-	struct mv64x60_32bit_window	*window_tab_32bit;
-	struct mv64x60_64bit_window	*window_tab_64bit;
-};
-
-struct mv64x60_handle {
-	u32		type;		/* type of bridge */
-	u32		rev;		/* revision of bridge */
-	void		__iomem *v_base;/* virtual base addr of bridge regs */
-	phys_addr_t	p_base;		/* physical base addr of bridge regs */
-
-	u32		pci_mode_a;	/* pci 0 mode: conventional pci, pci-x*/
-	u32		pci_mode_b;	/* pci 1 mode: conventional pci, pci-x*/
-
-	u32		io_base_a;	/* vaddr of pci 0's I/O space */
-	u32		io_base_b;	/* vaddr of pci 1's I/O space */
-
-	struct pci_controller	*hose_a;
-	struct pci_controller	*hose_b;
-
-	struct mv64x60_chip_info *ci;	/* chip/bridge-specific info */
-};
-
-
-/* Define I/O routines for accessing registers on the 64x60 bridge. */
-extern inline void
-mv64x60_write(struct mv64x60_handle *bh, u32 offset, u32 val) {
-	ulong	flags;
-
-	spin_lock_irqsave(&mv64x60_lock, flags);
-	out_le32(bh->v_base + offset, val);
-	spin_unlock_irqrestore(&mv64x60_lock, flags);
-}
-
-extern inline u32
-mv64x60_read(struct mv64x60_handle *bh, u32 offset) {
-	ulong	flags;
-	u32     reg;
-
-	spin_lock_irqsave(&mv64x60_lock, flags);
-	reg = in_le32(bh->v_base + offset);
-	spin_unlock_irqrestore(&mv64x60_lock, flags);
-	return reg;
-}
-
-extern inline void
-mv64x60_modify(struct mv64x60_handle *bh, u32 offs, u32 data, u32 mask)
-{
-	u32	reg;
-	ulong	flags;
-
-	spin_lock_irqsave(&mv64x60_lock, flags);
-	reg = in_le32(bh->v_base + offs) & (~mask);
-	reg |= data & mask;
-	out_le32(bh->v_base + offs, reg);
-	spin_unlock_irqrestore(&mv64x60_lock, flags);
-}
-
-#define	mv64x60_set_bits(bh, offs, bits) mv64x60_modify(bh, offs, ~0, bits)
-#define	mv64x60_clr_bits(bh, offs, bits) mv64x60_modify(bh, offs, 0, bits)
-
-#if defined(CONFIG_SYSFS) && !defined(CONFIG_GT64260)
-#define	MV64XXX_DEV_NAME	"mv64xxx"
-
-struct mv64xxx_pdata {
-	u32	hs_reg_valid;
-};
-#endif
-
-/* Externally visible function prototypes */
-int mv64x60_init(struct mv64x60_handle *bh, struct mv64x60_setup_info *si);
-u32 mv64x60_get_mem_size(u32 bridge_base, u32 chip_type);
-void mv64x60_early_init(struct mv64x60_handle *bh,
-	struct mv64x60_setup_info *si);
-void mv64x60_alloc_hose(struct mv64x60_handle *bh, u32 cfg_addr,
-	u32 cfg_data, struct pci_controller **hose);
-int mv64x60_get_type(struct mv64x60_handle *bh);
-int mv64x60_setup_for_chip(struct mv64x60_handle *bh);
-void __iomem *mv64x60_get_bridge_vbase(void);
-u32 mv64x60_get_bridge_type(void);
-u32 mv64x60_get_bridge_rev(void);
-void mv64x60_get_mem_windows(struct mv64x60_handle *bh,
-	u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]);
-void mv64x60_config_cpu2mem_windows(struct mv64x60_handle *bh,
-	struct mv64x60_setup_info *si,
-	u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]);
-void mv64x60_config_cpu2pci_windows(struct mv64x60_handle *bh,
-	struct mv64x60_pci_info *pi, u32 bus);
-void mv64x60_config_pci2mem_windows(struct mv64x60_handle *bh,
-	struct pci_controller *hose, struct mv64x60_pci_info *pi, u32 bus,
-	u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]);
-void mv64x60_config_resources(struct pci_controller *hose,
-	struct mv64x60_pci_info *pi, u32 io_base);
-void mv64x60_config_pci_params(struct pci_controller *hose,
-	struct mv64x60_pci_info *pi);
-void mv64x60_pd_fixup(struct mv64x60_handle *bh,
-	struct platform_device *pd_devs[], u32 entries);
-void mv64x60_get_32bit_window(struct mv64x60_handle *bh, u32 window,
-	u32 *base, u32 *size);
-void mv64x60_set_32bit_window(struct mv64x60_handle *bh, u32 window, u32 base,
-	u32 size, u32 other_bits);
-void mv64x60_get_64bit_window(struct mv64x60_handle *bh, u32 window,
-	u32 *base_hi, u32 *base_lo, u32 *size);
-void mv64x60_set_64bit_window(struct mv64x60_handle *bh, u32 window,
-	u32 base_hi, u32 base_lo, u32 size, u32 other_bits);
-void mv64x60_set_bus(struct mv64x60_handle *bh, u32 bus, u32 child_bus);
-int mv64x60_pci_exclude_device(u8 bus, u8 devfn);
-
-
-void gt64260_init_irq(void);
-int gt64260_get_irq(void);
-void mv64360_init_irq(void);
-int mv64360_get_irq(void);
-
-u32 mv64x60_mask(u32 val, u32 num_bits);
-u32 mv64x60_shift_left(u32 val, u32 num_bits);
-u32 mv64x60_shift_right(u32 val, u32 num_bits);
-u32 mv64x60_calc_mem_size(struct mv64x60_handle *bh,
-	u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]);
-
-void mv64x60_progress_init(u32 base);
-void mv64x60_mpsc_progress(char *s, unsigned short hex);
-
-extern struct mv64x60_32bit_window
-	gt64260_32bit_windows[MV64x60_32BIT_WIN_COUNT];
-extern struct mv64x60_64bit_window
-	gt64260_64bit_windows[MV64x60_64BIT_WIN_COUNT];
-extern struct mv64x60_32bit_window
-	mv64360_32bit_windows[MV64x60_32BIT_WIN_COUNT];
-extern struct mv64x60_64bit_window
-	mv64360_64bit_windows[MV64x60_64BIT_WIN_COUNT];
-
-#endif /* __ASMPPC_MV64x60_H */
diff --git a/include/asm-ppc/mv64x60_defs.h b/include/asm-ppc/mv64x60_defs.h
deleted file mode 100644
index 5b0704a3e6e..00000000000
--- a/include/asm-ppc/mv64x60_defs.h
+++ /dev/null
@@ -1,976 +0,0 @@
-/*
- * include/asm-ppc/mv64x60_defs.h
- *
- * Register definitions for the Marvell/Galileo GT64260, MV64360, etc.
- * host bridges.
- *
- * Author: Mark A. Greer <mgreer@mvista.com>
- *
- * 2001-2002 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifndef __ASMPPC_MV64x60_DEFS_H
-#define __ASMPPC_MV64x60_DEFS_H
-
-/*
- * Define the Marvell bridges that are supported
- */
-#define	MV64x60_TYPE_INVALID			0
-#define	MV64x60_TYPE_GT64260A			1
-#define	MV64x60_TYPE_GT64260B			2
-#define	MV64x60_TYPE_MV64360			3
-#define	MV64x60_TYPE_MV64361			4
-#define	MV64x60_TYPE_MV64362			5
-#define	MV64x60_TYPE_MV64460			6
-
-
-/* Revisions of each supported chip */
-#define	GT64260_REV_A				0x10
-#define	GT64260_REV_B				0x20
-#define	MV64360					0x01
-#define	MV64460					0x01
-
-/* Minimum window size supported by 64260 is 1MB */
-#define GT64260_WINDOW_SIZE_MIN			0x00100000
-#define MV64360_WINDOW_SIZE_MIN			0x00010000
-
-#define	MV64x60_TCLK_FREQ_MAX			133333333U
-
-/* IRQ's for embedded controllers */
-#define	MV64x60_IRQ_DEV				1
-#define	MV64x60_IRQ_CPU_ERR			3
-#define	MV64x60_IRQ_TIMER_0_1			8
-#define	MV64x60_IRQ_TIMER_2_3			9
-#define	MV64x60_IRQ_TIMER_4_5			10
-#define	MV64x60_IRQ_TIMER_6_7			11
-#define	MV64x60_IRQ_P1_GPP_0_7			24
-#define	MV64x60_IRQ_P1_GPP_8_15			25
-#define	MV64x60_IRQ_P1_GPP_16_23		26
-#define	MV64x60_IRQ_P1_GPP_24_31		27
-#define	MV64x60_IRQ_DOORBELL			28
-#define	MV64x60_IRQ_ETH_0			32
-#define	MV64x60_IRQ_ETH_1			33
-#define	MV64x60_IRQ_ETH_2			34
-#define	MV64x60_IRQ_SDMA_0			36
-#define	MV64x60_IRQ_I2C				37
-#define	MV64x60_IRQ_BRG				39
-#define	MV64x60_IRQ_MPSC_0			40
-#define	MV64x60_IRQ_MPSC_1			42
-#define	MV64x60_IRQ_COMM			43
-#define	MV64x60_IRQ_P0_GPP_0_7			56
-#define	MV64x60_IRQ_P0_GPP_8_15			57
-#define	MV64x60_IRQ_P0_GPP_16_23		58
-#define	MV64x60_IRQ_P0_GPP_24_31		59
-
-#define	MV64360_IRQ_PCI0			12
-#define	MV64360_IRQ_SRAM_PAR_ERR		13
-#define	MV64360_IRQ_PCI1			16
-#define	MV64360_IRQ_SDMA_1			38
-
-#define	MV64x60_IRQ_GPP0			64
-#define	MV64x60_IRQ_GPP1			65
-#define	MV64x60_IRQ_GPP2			66
-#define	MV64x60_IRQ_GPP3			67
-#define	MV64x60_IRQ_GPP4			68
-#define	MV64x60_IRQ_GPP5			69
-#define	MV64x60_IRQ_GPP6			70
-#define	MV64x60_IRQ_GPP7			71
-#define	MV64x60_IRQ_GPP8			72
-#define	MV64x60_IRQ_GPP9			73
-#define	MV64x60_IRQ_GPP10			74
-#define	MV64x60_IRQ_GPP11			75
-#define	MV64x60_IRQ_GPP12			76
-#define	MV64x60_IRQ_GPP13			77
-#define	MV64x60_IRQ_GPP14			78
-#define	MV64x60_IRQ_GPP15			79
-#define	MV64x60_IRQ_GPP16			80
-#define	MV64x60_IRQ_GPP17			81
-#define	MV64x60_IRQ_GPP18			82
-#define	MV64x60_IRQ_GPP19			83
-#define	MV64x60_IRQ_GPP20			84
-#define	MV64x60_IRQ_GPP21			85
-#define	MV64x60_IRQ_GPP22			86
-#define	MV64x60_IRQ_GPP23			87
-#define	MV64x60_IRQ_GPP24			88
-#define	MV64x60_IRQ_GPP25			89
-#define	MV64x60_IRQ_GPP26			90
-#define	MV64x60_IRQ_GPP27			91
-#define	MV64x60_IRQ_GPP28			92
-#define	MV64x60_IRQ_GPP29			93
-#define	MV64x60_IRQ_GPP30			94
-#define	MV64x60_IRQ_GPP31			95
-
-/* Offsets for register blocks */
-#define	GT64260_ENET_PHY_ADDR			0x2000
-#define	GT64260_ENET_ESMIR			0x2010
-#define GT64260_ENET_0_OFFSET			0x2400
-#define GT64260_ENET_1_OFFSET			0x2800
-#define GT64260_ENET_2_OFFSET			0x2c00
-#define	MV64x60_SDMA_0_OFFSET			0x4000
-#define	MV64x60_SDMA_1_OFFSET			0x6000
-#define	MV64x60_MPSC_0_OFFSET			0x8000
-#define	MV64x60_MPSC_1_OFFSET			0x9000
-#define	MV64x60_MPSC_ROUTING_OFFSET		0xb400
-#define	MV64x60_SDMA_INTR_OFFSET		0xb800
-#define	MV64x60_BRG_0_OFFSET			0xb200
-#define	MV64x60_BRG_1_OFFSET			0xb208
-
-/*
- *****************************************************************************
- *
- *	CPU Interface Registers
- *
- *****************************************************************************
- */
-
-/* CPU physical address of bridge's registers */
-#define MV64x60_INTERNAL_SPACE_DECODE		0x0068
-#define MV64x60_INTERNAL_SPACE_SIZE		0x10000
-#define MV64x60_INTERNAL_SPACE_DEFAULT_ADDR	0x14000000
-
-#define	MV64360_CPU_BAR_ENABLE			0x0278
-
-/* CPU Memory Controller Window Registers (4 windows) */
-#define	MV64x60_CPU2MEM_WINDOWS			4
-
-#define	MV64x60_CPU2MEM_0_BASE			0x0008
-#define	MV64x60_CPU2MEM_0_SIZE			0x0010
-#define	MV64x60_CPU2MEM_1_BASE			0x0208
-#define	MV64x60_CPU2MEM_1_SIZE			0x0210
-#define	MV64x60_CPU2MEM_2_BASE			0x0018
-#define	MV64x60_CPU2MEM_2_SIZE			0x0020
-#define	MV64x60_CPU2MEM_3_BASE			0x0218
-#define	MV64x60_CPU2MEM_3_SIZE			0x0220
-
-/* CPU Device Controller Window Registers (4 windows) */
-#define	MV64x60_CPU2DEV_WINDOWS			4
-
-#define	MV64x60_CPU2DEV_0_BASE			0x0028
-#define	MV64x60_CPU2DEV_0_SIZE			0x0030
-#define	MV64x60_CPU2DEV_1_BASE			0x0228
-#define	MV64x60_CPU2DEV_1_SIZE			0x0230
-#define	MV64x60_CPU2DEV_2_BASE			0x0248
-#define	MV64x60_CPU2DEV_2_SIZE			0x0250
-#define	MV64x60_CPU2DEV_3_BASE			0x0038
-#define	MV64x60_CPU2DEV_3_SIZE			0x0040
-
-#define	MV64x60_CPU2BOOT_0_BASE			0x0238
-#define	MV64x60_CPU2BOOT_0_SIZE			0x0240
-
-#define	MV64360_CPU2SRAM_BASE			0x0268
-
-/* CPU Windows to PCI space (2 PCI buses each w/ 1 I/O & 4 MEM windows) */
-#define	MV64x60_PCI_BUSES			2
-#define	MV64x60_PCI_IO_WINDOWS_PER_BUS		1
-#define	MV64x60_PCI_MEM_WINDOWS_PER_BUS		4
-
-#define	MV64x60_CPU2PCI_SWAP_BYTE		0x00000000
-#define	MV64x60_CPU2PCI_SWAP_NONE		0x01000000
-#define	MV64x60_CPU2PCI_SWAP_BYTE_WORD		0x02000000
-#define	MV64x60_CPU2PCI_SWAP_WORD		0x03000000
-
-#define	MV64x60_CPU2PCI_MEM_REQ64		(1<<27)
-
-#define	MV64x60_CPU2PCI0_IO_BASE		0x0048
-#define	MV64x60_CPU2PCI0_IO_SIZE		0x0050
-#define	MV64x60_CPU2PCI0_MEM_0_BASE		0x0058
-#define	MV64x60_CPU2PCI0_MEM_0_SIZE		0x0060
-#define	MV64x60_CPU2PCI0_MEM_1_BASE		0x0080
-#define	MV64x60_CPU2PCI0_MEM_1_SIZE		0x0088
-#define	MV64x60_CPU2PCI0_MEM_2_BASE		0x0258
-#define	MV64x60_CPU2PCI0_MEM_2_SIZE		0x0260
-#define	MV64x60_CPU2PCI0_MEM_3_BASE		0x0280
-#define	MV64x60_CPU2PCI0_MEM_3_SIZE		0x0288
-
-#define	MV64x60_CPU2PCI0_IO_REMAP		0x00f0
-#define	MV64x60_CPU2PCI0_MEM_0_REMAP_LO		0x00f8
-#define	MV64x60_CPU2PCI0_MEM_0_REMAP_HI		0x0320
-#define	MV64x60_CPU2PCI0_MEM_1_REMAP_LO		0x0100
-#define	MV64x60_CPU2PCI0_MEM_1_REMAP_HI		0x0328
-#define	MV64x60_CPU2PCI0_MEM_2_REMAP_LO		0x02f8
-#define	MV64x60_CPU2PCI0_MEM_2_REMAP_HI		0x0330
-#define	MV64x60_CPU2PCI0_MEM_3_REMAP_LO		0x0300
-#define	MV64x60_CPU2PCI0_MEM_3_REMAP_HI		0x0338
-
-#define	MV64x60_CPU2PCI1_IO_BASE		0x0090
-#define	MV64x60_CPU2PCI1_IO_SIZE		0x0098
-#define	MV64x60_CPU2PCI1_MEM_0_BASE		0x00a0
-#define	MV64x60_CPU2PCI1_MEM_0_SIZE		0x00a8
-#define	MV64x60_CPU2PCI1_MEM_1_BASE		0x00b0
-#define	MV64x60_CPU2PCI1_MEM_1_SIZE		0x00b8
-#define	MV64x60_CPU2PCI1_MEM_2_BASE		0x02a0
-#define	MV64x60_CPU2PCI1_MEM_2_SIZE		0x02a8
-#define	MV64x60_CPU2PCI1_MEM_3_BASE		0x02b0
-#define	MV64x60_CPU2PCI1_MEM_3_SIZE		0x02b8
-
-#define	MV64x60_CPU2PCI1_IO_REMAP		0x0108
-#define	MV64x60_CPU2PCI1_MEM_0_REMAP_LO		0x0110
-#define	MV64x60_CPU2PCI1_MEM_0_REMAP_HI		0x0340
-#define	MV64x60_CPU2PCI1_MEM_1_REMAP_LO		0x0118
-#define	MV64x60_CPU2PCI1_MEM_1_REMAP_HI		0x0348
-#define	MV64x60_CPU2PCI1_MEM_2_REMAP_LO		0x0310
-#define	MV64x60_CPU2PCI1_MEM_2_REMAP_HI		0x0350
-#define	MV64x60_CPU2PCI1_MEM_3_REMAP_LO		0x0318
-#define	MV64x60_CPU2PCI1_MEM_3_REMAP_HI		0x0358
-
-/* CPU Control Registers */
-#define MV64x60_CPU_CONFIG			0x0000
-#define MV64x60_CPU_MODE			0x0120
-#define MV64x60_CPU_MASTER_CNTL			0x0160
-#define MV64x60_CPU_XBAR_CNTL_LO		0x0150
-#define MV64x60_CPU_XBAR_CNTL_HI		0x0158
-#define MV64x60_CPU_XBAR_TO			0x0168
-
-#define GT64260_CPU_RR_XBAR_CNTL_LO		0x0170
-#define GT64260_CPU_RR_XBAR_CNTL_HI		0x0178
-
-#define MV64360_CPU_PADS_CALIBRATION		0x03b4
-#define MV64360_CPU_RESET_SAMPLE_LO		0x03c4
-#define MV64360_CPU_RESET_SAMPLE_HI		0x03d4
-
-/* SMP Register Map */
-#define MV64360_WHO_AM_I			0x0200
-#define MV64360_CPU0_DOORBELL			0x0214
-#define MV64360_CPU0_DOORBELL_CLR		0x021c
-#define MV64360_CPU0_DOORBELL_MASK		0x0234
-#define MV64360_CPU1_DOORBELL			0x0224
-#define MV64360_CPU1_DOORBELL_CLR		0x022c
-#define MV64360_CPU1_DOORBELL_MASK		0x023c
-#define MV64360_CPUx_DOORBELL(x)		(0x0214 + ((x)*0x10))
-#define MV64360_CPUx_DOORBELL_CLR(x)		(0x021c + ((x)*0x10))
-#define MV64360_CPUx_DOORBELL_MASK(x)		(0x0234 + ((x)*0x08))
-#define MV64360_SEMAPHORE_0			0x0244
-#define MV64360_SEMAPHORE_1			0x024c
-#define MV64360_SEMAPHORE_2			0x0254
-#define MV64360_SEMAPHORE_3			0x025c
-#define MV64360_SEMAPHORE_4			0x0264
-#define MV64360_SEMAPHORE_5			0x026c
-#define MV64360_SEMAPHORE_6			0x0274
-#define MV64360_SEMAPHORE_7			0x027c
-
-/* CPU Sync Barrier Registers */
-#define GT64260_CPU_SYNC_BARRIER_PCI0		0x00c0
-#define GT64260_CPU_SYNC_BARRIER_PCI1		0x00c8
-
-#define MV64360_CPU0_SYNC_BARRIER_TRIG		0x00c0
-#define MV64360_CPU0_SYNC_BARRIER_VIRT		0x00c8
-#define MV64360_CPU1_SYNC_BARRIER_TRIG		0x00d0
-#define MV64360_CPU1_SYNC_BARRIER_VIRT		0x00d8
-
-/* CPU Deadlock and Ordering registers (Rev B part only) */
-#define GT64260_CPU_DEADLOCK_ORDERING			0x02d0
-#define GT64260_CPU_WB_PRIORITY_BUFFER_DEPTH		0x02d8
-#define GT64260_CPU_COUNTERS_SYNC_BARRIER_ATTRIBUTE	0x02e0
-
-/* CPU Access Protection Registers (gt64260 realy has 8 but don't need) */
-#define	MV64x260_CPU_PROT_WINDOWS		4
-
-#define	GT64260_CPU_PROT_ACCPROTECT		(1<<16)
-#define	GT64260_CPU_PROT_WRPROTECT		(1<<17)
-#define	GT64260_CPU_PROT_CACHEPROTECT		(1<<18)
-
-#define	MV64360_CPU_PROT_ACCPROTECT		(1<<20)
-#define	MV64360_CPU_PROT_WRPROTECT		(1<<21)
-#define	MV64360_CPU_PROT_CACHEPROTECT		(1<<22)
-#define	MV64360_CPU_PROT_WIN_ENABLE		(1<<31)
-
-#define MV64x60_CPU_PROT_BASE_0			0x0180
-#define MV64x60_CPU_PROT_SIZE_0			0x0188
-#define MV64x60_CPU_PROT_BASE_1			0x0190
-#define MV64x60_CPU_PROT_SIZE_1			0x0198
-#define MV64x60_CPU_PROT_BASE_2			0x01a0
-#define MV64x60_CPU_PROT_SIZE_2			0x01a8
-#define MV64x60_CPU_PROT_BASE_3			0x01b0
-#define MV64x60_CPU_PROT_SIZE_3			0x01b8
-
-#define GT64260_CPU_PROT_BASE_4			0x01c0
-#define GT64260_CPU_PROT_SIZE_4			0x01c8
-#define GT64260_CPU_PROT_BASE_5			0x01d0
-#define GT64260_CPU_PROT_SIZE_5			0x01d8
-#define GT64260_CPU_PROT_BASE_6			0x01e0
-#define GT64260_CPU_PROT_SIZE_6			0x01e8
-#define GT64260_CPU_PROT_BASE_7			0x01f0
-#define GT64260_CPU_PROT_SIZE_7			0x01f8
-
-/* CPU Snoop Control Registers (64260 only) */
-#define	GT64260_CPU_SNOOP_WINDOWS		4
-
-#define	GT64260_CPU_SNOOP_NONE			0x00000000
-#define	GT64260_CPU_SNOOP_WT			0x00010000
-#define	GT64260_CPU_SNOOP_WB			0x00020000
-#define	GT64260_CPU_SNOOP_MASK			0x00030000
-#define	GT64260_CPU_SNOOP_ALL_BITS		GT64260_CPU_SNOOP_MASK
-
-#define GT64260_CPU_SNOOP_BASE_0		0x0380
-#define GT64260_CPU_SNOOP_SIZE_0		0x0388
-#define GT64260_CPU_SNOOP_BASE_1		0x0390
-#define GT64260_CPU_SNOOP_SIZE_1		0x0398
-#define GT64260_CPU_SNOOP_BASE_2		0x03a0
-#define GT64260_CPU_SNOOP_SIZE_2		0x03a8
-#define GT64260_CPU_SNOOP_BASE_3		0x03b0
-#define GT64260_CPU_SNOOP_SIZE_3		0x03b8
-
-/* CPU Snoop Control Registers (64360 only) */
-#define	MV64360_CPU_SNOOP_WINDOWS		4
-#define	MV64360_CPU_SNOOP_NONE			0x00000000
-#define	MV64360_CPU_SNOOP_WT			0x00010000
-#define	MV64360_CPU_SNOOP_WB			0x00020000
-#define	MV64360_CPU_SNOOP_MASK			0x00030000
-#define	MV64360_CPU_SNOOP_ALL_BITS		MV64360_CPU_SNOOP_MASK
-
-
-/* CPU Error Report Registers */
-#define MV64x60_CPU_ERR_ADDR_LO			0x0070
-#define MV64x60_CPU_ERR_ADDR_HI			0x0078
-#define MV64x60_CPU_ERR_DATA_LO			0x0128
-#define MV64x60_CPU_ERR_DATA_HI			0x0130
-#define MV64x60_CPU_ERR_PARITY			0x0138
-#define MV64x60_CPU_ERR_CAUSE			0x0140
-#define MV64x60_CPU_ERR_MASK			0x0148
-
-/*
- *****************************************************************************
- *
- *	SRAM Controller Registers
- *
- *****************************************************************************
- */
-
-#define	MV64360_SRAM_CONFIG			0x0380
-#define	MV64360_SRAM_TEST_MODE			0x03f4
-#define	MV64360_SRAM_ERR_CAUSE			0x0388
-#define	MV64360_SRAM_ERR_ADDR_LO		0x0390
-#define	MV64360_SRAM_ERR_ADDR_HI		0x03f8
-#define	MV64360_SRAM_ERR_DATA_LO		0x0398
-#define	MV64360_SRAM_ERR_DATA_HI		0x03a0
-#define	MV64360_SRAM_ERR_PARITY			0x03a8
-
-#define	MV64360_SRAM_SIZE			0x00040000 /* 2Mb/256KB SRAM */
-
-/*
- *****************************************************************************
- *
- *	SDRAM/MEM Controller Registers
- *
- *****************************************************************************
- */
-
-/* SDRAM Config Registers (64260) */
-#define	GT64260_SDRAM_CONFIG			0x0448
-
-/* SDRAM Error Report Registers (64260) */
-#define	GT64260_SDRAM_ERR_DATA_LO		0x0484
-#define	GT64260_SDRAM_ERR_DATA_HI		0x0480
-#define	GT64260_SDRAM_ERR_ADDR			0x0490
-#define	GT64260_SDRAM_ERR_ECC_RCVD		0x0488
-#define	GT64260_SDRAM_ERR_ECC_CALC		0x048c
-#define	GT64260_SDRAM_ERR_ECC_CNTL		0x0494
-#define	GT64260_SDRAM_ERR_ECC_ERR_CNT		0x0498
-
-/* SDRAM Config Registers (64360) */
-#define	MV64360_SDRAM_CONFIG			0x1400
-
-/* SDRAM Control Registers */
-#define MV64360_D_UNIT_CONTROL_LOW		0x1404
-#define MV64360_D_UNIT_CONTROL_HIGH		0x1424
-#define MV64460_D_UNIT_MMASK			0x14b0
-
-/* SDRAM Error Report Registers (64360) */
-#define	MV64360_SDRAM_ERR_DATA_LO		0x1444
-#define	MV64360_SDRAM_ERR_DATA_HI		0x1440
-#define	MV64360_SDRAM_ERR_ADDR			0x1450
-#define	MV64360_SDRAM_ERR_ECC_RCVD		0x1448
-#define	MV64360_SDRAM_ERR_ECC_CALC		0x144c
-#define	MV64360_SDRAM_ERR_ECC_CNTL		0x1454
-#define	MV64360_SDRAM_ERR_ECC_ERR_CNT		0x1458
-
-/*
- *****************************************************************************
- *
- *	Device/BOOT Controller Registers
- *
- *****************************************************************************
- */
-
-/* Device Control Registers */
-#define	MV64x60_DEV_BANK_PARAMS_0		0x045c
-#define	MV64x60_DEV_BANK_PARAMS_1		0x0460
-#define	MV64x60_DEV_BANK_PARAMS_2		0x0464
-#define	MV64x60_DEV_BANK_PARAMS_3		0x0468
-#define	MV64x60_DEV_BOOT_PARAMS			0x046c
-#define	MV64x60_DEV_IF_CNTL			0x04c0
-#define	MV64x60_DEV_IF_XBAR_CNTL_LO		0x04c8
-#define	MV64x60_DEV_IF_XBAR_CNTL_HI		0x04cc
-#define	MV64x60_DEV_IF_XBAR_CNTL_TO		0x04c4
-
-/* Device Interrupt Registers */
-#define	MV64x60_DEV_INTR_CAUSE			0x04d0
-#define	MV64x60_DEV_INTR_MASK			0x04d4
-#define	MV64x60_DEV_INTR_ERR_ADDR		0x04d8
-
-#define	MV64360_DEV_INTR_ERR_DATA		0x04dc
-#define	MV64360_DEV_INTR_ERR_PAR		0x04e0
-
-/*
- *****************************************************************************
- *
- *	PCI Bridge Interface Registers
- *
- *****************************************************************************
- */
-
-/* PCI Configuration Access Registers */
-#define	MV64x60_PCI0_CONFIG_ADDR		0x0cf8
-#define	MV64x60_PCI0_CONFIG_DATA		0x0cfc
-#define	MV64x60_PCI0_IACK			0x0c34
-
-#define	MV64x60_PCI1_CONFIG_ADDR		0x0c78
-#define	MV64x60_PCI1_CONFIG_DATA		0x0c7c
-#define	MV64x60_PCI1_IACK			0x0cb4
-
-/* PCI Control Registers */
-#define	MV64x60_PCI0_CMD			0x0c00
-#define	MV64x60_PCI0_MODE			0x0d00
-#define	MV64x60_PCI0_TO_RETRY			0x0c04
-#define	MV64x60_PCI0_RD_BUF_DISCARD_TIMER	0x0d04
-#define	MV64x60_PCI0_MSI_TRIGGER_TIMER		0x0c38
-#define	MV64x60_PCI0_ARBITER_CNTL		0x1d00
-#define	MV64x60_PCI0_XBAR_CNTL_LO		0x1d08
-#define	MV64x60_PCI0_XBAR_CNTL_HI		0x1d0c
-#define	MV64x60_PCI0_XBAR_CNTL_TO		0x1d04
-#define	MV64x60_PCI0_RD_RESP_XBAR_CNTL_LO	0x1d18
-#define	MV64x60_PCI0_RD_RESP_XBAR_CNTL_HI	0x1d1c
-#define	MV64x60_PCI0_SYNC_BARRIER		0x1d10
-#define	MV64x60_PCI0_P2P_CONFIG			0x1d14
-#define	MV64x60_PCI0_INTR_MASK
-
-#define	GT64260_PCI0_P2P_SWAP_CNTL		0x1d54
-
-#define	MV64x60_PCI1_CMD			0x0c80
-#define	MV64x60_PCI1_MODE			0x0d80
-#define	MV64x60_PCI1_TO_RETRY			0x0c84
-#define	MV64x60_PCI1_RD_BUF_DISCARD_TIMER	0x0d84
-#define	MV64x60_PCI1_MSI_TRIGGER_TIMER		0x0cb8
-#define	MV64x60_PCI1_ARBITER_CNTL		0x1d80
-#define	MV64x60_PCI1_XBAR_CNTL_LO		0x1d88
-#define	MV64x60_PCI1_XBAR_CNTL_HI		0x1d8c
-#define	MV64x60_PCI1_XBAR_CNTL_TO		0x1d84
-#define	MV64x60_PCI1_RD_RESP_XBAR_CNTL_LO	0x1d98
-#define	MV64x60_PCI1_RD_RESP_XBAR_CNTL_HI	0x1d9c
-#define	MV64x60_PCI1_SYNC_BARRIER		0x1d90
-#define	MV64x60_PCI1_P2P_CONFIG			0x1d94
-
-#define	GT64260_PCI1_P2P_SWAP_CNTL		0x1dd4
-
-/* Different modes that the pci hoses can be in (bits 5:4 in PCI Mode reg) */
-#define	MV64x60_PCIMODE_CONVENTIONAL		0
-#define	MV64x60_PCIMODE_PCIX_66			(1 << 4)
-#define	MV64x60_PCIMODE_PCIX_100		(2 << 4)
-#define	MV64x60_PCIMODE_PCIX_133		(3 << 4)
-#define	MV64x60_PCIMODE_MASK			(0x3 << 4)
-
-/* PCI Access Control Regions Registers */
-#define	GT64260_PCI_ACC_CNTL_PREFETCHEN		(1<<12)
-#define	GT64260_PCI_ACC_CNTL_DREADEN		(1<<13)
-#define	GT64260_PCI_ACC_CNTL_RDPREFETCH		(1<<16)
-#define	GT64260_PCI_ACC_CNTL_RDLINEPREFETCH	(1<<17)
-#define	GT64260_PCI_ACC_CNTL_RDMULPREFETCH	(1<<18)
-#define	GT64260_PCI_ACC_CNTL_MBURST_32_BTYES	0x00000000
-#define	GT64260_PCI_ACC_CNTL_MBURST_64_BYTES	0x00100000
-#define	GT64260_PCI_ACC_CNTL_MBURST_128_BYTES	0x00200000
-#define	GT64260_PCI_ACC_CNTL_MBURST_MASK	0x00300000
-#define	GT64260_PCI_ACC_CNTL_SWAP_BYTE		0x00000000
-#define	GT64260_PCI_ACC_CNTL_SWAP_NONE		0x01000000
-#define	GT64260_PCI_ACC_CNTL_SWAP_BYTE_WORD	0x02000000
-#define	GT64260_PCI_ACC_CNTL_SWAP_WORD		0x03000000
-#define	GT64260_PCI_ACC_CNTL_SWAP_MASK		0x03000000
-#define	GT64260_PCI_ACC_CNTL_ACCPROT		(1<<28)
-#define	GT64260_PCI_ACC_CNTL_WRPROT		(1<<29)
-
-#define	GT64260_PCI_ACC_CNTL_ALL_BITS	(GT64260_PCI_ACC_CNTL_PREFETCHEN |    \
-					 GT64260_PCI_ACC_CNTL_DREADEN |       \
-					 GT64260_PCI_ACC_CNTL_RDPREFETCH |    \
-					 GT64260_PCI_ACC_CNTL_RDLINEPREFETCH |\
-					 GT64260_PCI_ACC_CNTL_RDMULPREFETCH | \
-					 GT64260_PCI_ACC_CNTL_MBURST_MASK |   \
-					 GT64260_PCI_ACC_CNTL_SWAP_MASK |     \
-					 GT64260_PCI_ACC_CNTL_ACCPROT|        \
-					 GT64260_PCI_ACC_CNTL_WRPROT)
-
-#define	MV64360_PCI_ACC_CNTL_ENABLE		(1<<0)
-#define	MV64360_PCI_ACC_CNTL_REQ64		(1<<1)
-#define	MV64360_PCI_ACC_CNTL_SNOOP_NONE		0x00000000
-#define	MV64360_PCI_ACC_CNTL_SNOOP_WT		0x00000004
-#define	MV64360_PCI_ACC_CNTL_SNOOP_WB		0x00000008
-#define	MV64360_PCI_ACC_CNTL_SNOOP_MASK		0x0000000c
-#define	MV64360_PCI_ACC_CNTL_ACCPROT		(1<<4)
-#define	MV64360_PCI_ACC_CNTL_WRPROT		(1<<5)
-#define	MV64360_PCI_ACC_CNTL_SWAP_BYTE		0x00000000
-#define	MV64360_PCI_ACC_CNTL_SWAP_NONE		0x00000040
-#define	MV64360_PCI_ACC_CNTL_SWAP_BYTE_WORD	0x00000080
-#define	MV64360_PCI_ACC_CNTL_SWAP_WORD		0x000000c0
-#define	MV64360_PCI_ACC_CNTL_SWAP_MASK		0x000000c0
-#define	MV64360_PCI_ACC_CNTL_MBURST_32_BYTES	0x00000000
-#define	MV64360_PCI_ACC_CNTL_MBURST_64_BYTES	0x00000100
-#define	MV64360_PCI_ACC_CNTL_MBURST_128_BYTES	0x00000200
-#define	MV64360_PCI_ACC_CNTL_MBURST_MASK	0x00000300
-#define	MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES	0x00000000
-#define	MV64360_PCI_ACC_CNTL_RDSIZE_64_BYTES	0x00000400
-#define	MV64360_PCI_ACC_CNTL_RDSIZE_128_BYTES	0x00000800
-#define	MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES	0x00000c00
-#define	MV64360_PCI_ACC_CNTL_RDSIZE_MASK	0x00000c00
-
-#define	MV64360_PCI_ACC_CNTL_ALL_BITS	(MV64360_PCI_ACC_CNTL_ENABLE |	    \
-					 MV64360_PCI_ACC_CNTL_REQ64 |	    \
-					 MV64360_PCI_ACC_CNTL_SNOOP_MASK |  \
-					 MV64360_PCI_ACC_CNTL_ACCPROT |	    \
-					 MV64360_PCI_ACC_CNTL_WRPROT |	    \
-					 MV64360_PCI_ACC_CNTL_SWAP_MASK |   \
-					 MV64360_PCI_ACC_CNTL_MBURST_MASK | \
-					 MV64360_PCI_ACC_CNTL_RDSIZE_MASK)
-
-#define	MV64x60_PCI0_ACC_CNTL_0_BASE_LO		0x1e00
-#define	MV64x60_PCI0_ACC_CNTL_0_BASE_HI		0x1e04
-#define	MV64x60_PCI0_ACC_CNTL_0_SIZE		0x1e08
-#define	MV64x60_PCI0_ACC_CNTL_1_BASE_LO		0x1e10
-#define	MV64x60_PCI0_ACC_CNTL_1_BASE_HI		0x1e14
-#define	MV64x60_PCI0_ACC_CNTL_1_SIZE		0x1e18
-#define	MV64x60_PCI0_ACC_CNTL_2_BASE_LO		0x1e20
-#define	MV64x60_PCI0_ACC_CNTL_2_BASE_HI		0x1e24
-#define	MV64x60_PCI0_ACC_CNTL_2_SIZE		0x1e28
-#define	MV64x60_PCI0_ACC_CNTL_3_BASE_LO		0x1e30
-#define	MV64x60_PCI0_ACC_CNTL_3_BASE_HI		0x1e34
-#define	MV64x60_PCI0_ACC_CNTL_3_SIZE		0x1e38
-#define	MV64x60_PCI0_ACC_CNTL_4_BASE_LO		0x1e40
-#define	MV64x60_PCI0_ACC_CNTL_4_BASE_HI		0x1e44
-#define	MV64x60_PCI0_ACC_CNTL_4_SIZE		0x1e48
-#define	MV64x60_PCI0_ACC_CNTL_5_BASE_LO		0x1e50
-#define	MV64x60_PCI0_ACC_CNTL_5_BASE_HI		0x1e54
-#define	MV64x60_PCI0_ACC_CNTL_5_SIZE		0x1e58
-
-#define	GT64260_PCI0_ACC_CNTL_6_BASE_LO		0x1e60
-#define	GT64260_PCI0_ACC_CNTL_6_BASE_HI		0x1e64
-#define	GT64260_PCI0_ACC_CNTL_6_SIZE		0x1e68
-#define	GT64260_PCI0_ACC_CNTL_7_BASE_LO		0x1e70
-#define	GT64260_PCI0_ACC_CNTL_7_BASE_HI		0x1e74
-#define	GT64260_PCI0_ACC_CNTL_7_SIZE		0x1e78
-
-#define	MV64x60_PCI1_ACC_CNTL_0_BASE_LO		0x1e80
-#define	MV64x60_PCI1_ACC_CNTL_0_BASE_HI		0x1e84
-#define	MV64x60_PCI1_ACC_CNTL_0_SIZE		0x1e88
-#define	MV64x60_PCI1_ACC_CNTL_1_BASE_LO		0x1e90
-#define	MV64x60_PCI1_ACC_CNTL_1_BASE_HI		0x1e94
-#define	MV64x60_PCI1_ACC_CNTL_1_SIZE		0x1e98
-#define	MV64x60_PCI1_ACC_CNTL_2_BASE_LO		0x1ea0
-#define	MV64x60_PCI1_ACC_CNTL_2_BASE_HI		0x1ea4
-#define	MV64x60_PCI1_ACC_CNTL_2_SIZE		0x1ea8
-#define	MV64x60_PCI1_ACC_CNTL_3_BASE_LO		0x1eb0
-#define	MV64x60_PCI1_ACC_CNTL_3_BASE_HI		0x1eb4
-#define	MV64x60_PCI1_ACC_CNTL_3_SIZE		0x1eb8
-#define	MV64x60_PCI1_ACC_CNTL_4_BASE_LO		0x1ec0
-#define	MV64x60_PCI1_ACC_CNTL_4_BASE_HI		0x1ec4
-#define	MV64x60_PCI1_ACC_CNTL_4_SIZE		0x1ec8
-#define	MV64x60_PCI1_ACC_CNTL_5_BASE_LO		0x1ed0
-#define	MV64x60_PCI1_ACC_CNTL_5_BASE_HI		0x1ed4
-#define	MV64x60_PCI1_ACC_CNTL_5_SIZE		0x1ed8
-
-#define	GT64260_PCI1_ACC_CNTL_6_BASE_LO		0x1ee0
-#define	GT64260_PCI1_ACC_CNTL_6_BASE_HI		0x1ee4
-#define	GT64260_PCI1_ACC_CNTL_6_SIZE		0x1ee8
-#define	GT64260_PCI1_ACC_CNTL_7_BASE_LO		0x1ef0
-#define	GT64260_PCI1_ACC_CNTL_7_BASE_HI		0x1ef4
-#define	GT64260_PCI1_ACC_CNTL_7_SIZE		0x1ef8
-
-/* PCI Snoop Control Registers (64260 only) */
-#define	GT64260_PCI_SNOOP_NONE			0x00000000
-#define	GT64260_PCI_SNOOP_WT			0x00001000
-#define	GT64260_PCI_SNOOP_WB			0x00002000
-
-#define	GT64260_PCI0_SNOOP_0_BASE_LO		0x1f00
-#define	GT64260_PCI0_SNOOP_0_BASE_HI		0x1f04
-#define	GT64260_PCI0_SNOOP_0_SIZE		0x1f08
-#define	GT64260_PCI0_SNOOP_1_BASE_LO		0x1f10
-#define	GT64260_PCI0_SNOOP_1_BASE_HI		0x1f14
-#define	GT64260_PCI0_SNOOP_1_SIZE		0x1f18
-#define	GT64260_PCI0_SNOOP_2_BASE_LO		0x1f20
-#define	GT64260_PCI0_SNOOP_2_BASE_HI		0x1f24
-#define	GT64260_PCI0_SNOOP_2_SIZE		0x1f28
-#define	GT64260_PCI0_SNOOP_3_BASE_LO		0x1f30
-#define	GT64260_PCI0_SNOOP_3_BASE_HI		0x1f34
-#define	GT64260_PCI0_SNOOP_3_SIZE		0x1f38
-
-#define	GT64260_PCI1_SNOOP_0_BASE_LO		0x1f80
-#define	GT64260_PCI1_SNOOP_0_BASE_HI		0x1f84
-#define	GT64260_PCI1_SNOOP_0_SIZE		0x1f88
-#define	GT64260_PCI1_SNOOP_1_BASE_LO		0x1f90
-#define	GT64260_PCI1_SNOOP_1_BASE_HI		0x1f94
-#define	GT64260_PCI1_SNOOP_1_SIZE		0x1f98
-#define	GT64260_PCI1_SNOOP_2_BASE_LO		0x1fa0
-#define	GT64260_PCI1_SNOOP_2_BASE_HI		0x1fa4
-#define	GT64260_PCI1_SNOOP_2_SIZE		0x1fa8
-#define	GT64260_PCI1_SNOOP_3_BASE_LO		0x1fb0
-#define	GT64260_PCI1_SNOOP_3_BASE_HI		0x1fb4
-#define	GT64260_PCI1_SNOOP_3_SIZE		0x1fb8
-
-/* PCI Error Report Registers */
-#define MV64x60_PCI0_ERR_SERR_MASK		0x0c28
-#define MV64x60_PCI0_ERR_ADDR_LO		0x1d40
-#define MV64x60_PCI0_ERR_ADDR_HI		0x1d44
-#define MV64x60_PCI0_ERR_DATA_LO		0x1d48
-#define MV64x60_PCI0_ERR_DATA_HI		0x1d4c
-#define MV64x60_PCI0_ERR_CMD			0x1d50
-#define MV64x60_PCI0_ERR_CAUSE			0x1d58
-#define MV64x60_PCI0_ERR_MASK			0x1d5c
-
-#define MV64x60_PCI1_ERR_SERR_MASK		0x0ca8
-#define MV64x60_PCI1_ERR_ADDR_LO		0x1dc0
-#define MV64x60_PCI1_ERR_ADDR_HI		0x1dc4
-#define MV64x60_PCI1_ERR_DATA_LO		0x1dc8
-#define MV64x60_PCI1_ERR_DATA_HI		0x1dcc
-#define MV64x60_PCI1_ERR_CMD			0x1dd0
-#define MV64x60_PCI1_ERR_CAUSE			0x1dd8
-#define MV64x60_PCI1_ERR_MASK			0x1ddc
-
-/* PCI Slave Address Decoding Registers */
-#define	MV64x60_PCI0_MEM_0_SIZE			0x0c08
-#define	MV64x60_PCI0_MEM_1_SIZE			0x0d08
-#define	MV64x60_PCI0_MEM_2_SIZE			0x0c0c
-#define	MV64x60_PCI0_MEM_3_SIZE			0x0d0c
-#define	MV64x60_PCI1_MEM_0_SIZE			0x0c88
-#define	MV64x60_PCI1_MEM_1_SIZE			0x0d88
-#define	MV64x60_PCI1_MEM_2_SIZE			0x0c8c
-#define	MV64x60_PCI1_MEM_3_SIZE			0x0d8c
-
-#define	MV64x60_PCI0_BAR_ENABLE			0x0c3c
-#define	MV64x60_PCI1_BAR_ENABLE			0x0cbc
-
-#define	MV64x60_PCI0_PCI_DECODE_CNTL		0x0d3c
-#define	MV64x60_PCI1_PCI_DECODE_CNTL		0x0dbc
-
-#define	MV64x60_PCI0_SLAVE_MEM_0_REMAP		0x0c48
-#define	MV64x60_PCI0_SLAVE_MEM_1_REMAP		0x0d48
-#define	MV64x60_PCI0_SLAVE_MEM_2_REMAP		0x0c4c
-#define	MV64x60_PCI0_SLAVE_MEM_3_REMAP		0x0d4c
-#define	MV64x60_PCI0_SLAVE_DEV_0_REMAP		0x0c50
-#define	MV64x60_PCI0_SLAVE_DEV_1_REMAP		0x0d50
-#define	MV64x60_PCI0_SLAVE_DEV_2_REMAP		0x0d58
-#define	MV64x60_PCI0_SLAVE_DEV_3_REMAP		0x0c54
-#define	MV64x60_PCI0_SLAVE_BOOT_REMAP		0x0d54
-#define	MV64x60_PCI0_SLAVE_P2P_MEM_0_REMAP_LO	0x0d5c
-#define	MV64x60_PCI0_SLAVE_P2P_MEM_0_REMAP_HI	0x0d60
-#define	MV64x60_PCI0_SLAVE_P2P_MEM_1_REMAP_LO	0x0d64
-#define	MV64x60_PCI0_SLAVE_P2P_MEM_1_REMAP_HI	0x0d68
-#define	MV64x60_PCI0_SLAVE_P2P_IO_REMAP		0x0d6c
-#define	MV64x60_PCI0_SLAVE_CPU_REMAP		0x0d70
-
-#define	MV64x60_PCI1_SLAVE_MEM_0_REMAP		0x0cc8
-#define	MV64x60_PCI1_SLAVE_MEM_1_REMAP		0x0dc8
-#define	MV64x60_PCI1_SLAVE_MEM_2_REMAP		0x0ccc
-#define	MV64x60_PCI1_SLAVE_MEM_3_REMAP		0x0dcc
-#define	MV64x60_PCI1_SLAVE_DEV_0_REMAP		0x0cd0
-#define	MV64x60_PCI1_SLAVE_DEV_1_REMAP		0x0dd0
-#define	MV64x60_PCI1_SLAVE_DEV_2_REMAP		0x0dd8
-#define	MV64x60_PCI1_SLAVE_DEV_3_REMAP		0x0cd4
-#define	MV64x60_PCI1_SLAVE_BOOT_REMAP		0x0dd4
-#define	MV64x60_PCI1_SLAVE_P2P_MEM_0_REMAP_LO	0x0ddc
-#define	MV64x60_PCI1_SLAVE_P2P_MEM_0_REMAP_HI	0x0de0
-#define	MV64x60_PCI1_SLAVE_P2P_MEM_1_REMAP_LO	0x0de4
-#define	MV64x60_PCI1_SLAVE_P2P_MEM_1_REMAP_HI	0x0de8
-#define	MV64x60_PCI1_SLAVE_P2P_IO_REMAP		0x0dec
-#define	MV64x60_PCI1_SLAVE_CPU_REMAP		0x0df0
-
-#define	MV64360_PCICFG_CPCI_HOTSWAP		0x68
-
-/*
- *****************************************************************************
- *
- *	ENET Controller Interface Registers
- *
- *****************************************************************************
- */
-
-/* ENET Controller Window Registers (6 windows) */
-#define	MV64360_ENET2MEM_WINDOWS		6
-
-#define	MV64360_ENET2MEM_0_BASE			0x2200
-#define	MV64360_ENET2MEM_0_SIZE			0x2204
-#define	MV64360_ENET2MEM_1_BASE			0x2208
-#define	MV64360_ENET2MEM_1_SIZE			0x220c
-#define	MV64360_ENET2MEM_2_BASE			0x2210
-#define	MV64360_ENET2MEM_2_SIZE			0x2214
-#define	MV64360_ENET2MEM_3_BASE			0x2218
-#define	MV64360_ENET2MEM_3_SIZE			0x221c
-#define	MV64360_ENET2MEM_4_BASE			0x2220
-#define	MV64360_ENET2MEM_4_SIZE			0x2224
-#define	MV64360_ENET2MEM_5_BASE			0x2228
-#define	MV64360_ENET2MEM_5_SIZE			0x222c
-
-#define	MV64360_ENET2MEM_SNOOP_NONE		0x00000000
-#define	MV64360_ENET2MEM_SNOOP_WT		0x00001000
-#define	MV64360_ENET2MEM_SNOOP_WB		0x00002000
-
-#define	MV64360_ENET2MEM_BAR_ENABLE		0x2290
-
-#define	MV64360_ENET2MEM_ACC_PROT_0		0x2294
-#define	MV64360_ENET2MEM_ACC_PROT_1		0x2298
-#define	MV64360_ENET2MEM_ACC_PROT_2		0x229c
-
-/*
- *****************************************************************************
- *
- *	MPSC Controller Interface Registers
- *
- *****************************************************************************
- */
-
-/* MPSC Controller Window Registers (4 windows) */
-#define	MV64360_MPSC2MEM_WINDOWS		4
-
-#define	MV64360_MPSC2MEM_0_BASE			0xf200
-#define	MV64360_MPSC2MEM_0_SIZE			0xf204
-#define	MV64360_MPSC2MEM_1_BASE			0xf208
-#define	MV64360_MPSC2MEM_1_SIZE			0xf20c
-#define	MV64360_MPSC2MEM_2_BASE			0xf210
-#define	MV64360_MPSC2MEM_2_SIZE			0xf214
-#define	MV64360_MPSC2MEM_3_BASE			0xf218
-#define	MV64360_MPSC2MEM_3_SIZE			0xf21c
-
-#define MV64360_MPSC_0_REMAP			0xf240
-#define MV64360_MPSC_1_REMAP			0xf244
-
-#define	MV64360_MPSC2MEM_SNOOP_NONE		0x00000000
-#define	MV64360_MPSC2MEM_SNOOP_WT		0x00001000
-#define	MV64360_MPSC2MEM_SNOOP_WB		0x00002000
-
-#define	MV64360_MPSC2MEM_BAR_ENABLE		0xf250
-
-#define	MV64360_MPSC2MEM_ACC_PROT_0		0xf254
-#define	MV64360_MPSC2MEM_ACC_PROT_1		0xf258
-
-#define	MV64360_MPSC2REGS_BASE			0xf25c
-
-/*
- *****************************************************************************
- *
- *	Timer/Counter Interface Registers
- *
- *****************************************************************************
- */
-
-#define	MV64x60_TIMR_CNTR_0			0x0850
-#define	MV64x60_TIMR_CNTR_1			0x0854
-#define	MV64x60_TIMR_CNTR_2			0x0858
-#define	MV64x60_TIMR_CNTR_3			0x085c
-#define	MV64x60_TIMR_CNTR_0_3_CNTL		0x0864
-#define	MV64x60_TIMR_CNTR_0_3_INTR_CAUSE	0x0868
-#define	MV64x60_TIMR_CNTR_0_3_INTR_MASK		0x086c
-
-#define	GT64260_TIMR_CNTR_4			0x0950
-#define	GT64260_TIMR_CNTR_5			0x0954
-#define	GT64260_TIMR_CNTR_6			0x0958
-#define	GT64260_TIMR_CNTR_7			0x095c
-#define	GT64260_TIMR_CNTR_4_7_CNTL		0x0964
-#define	GT64260_TIMR_CNTR_4_7_INTR_CAUSE	0x0968
-#define	GT64260_TIMR_CNTR_4_7_INTR_MASK		0x096c
-
-/*
- *****************************************************************************
- *
- *	Communications Controller
- *
- *****************************************************************************
- */
-
-#define	GT64260_SER_INIT_PCI_ADDR_HI		0xf320
-#define	GT64260_SER_INIT_LAST_DATA		0xf324
-#define	GT64260_SER_INIT_CONTROL		0xf328
-#define	GT64260_SER_INIT_STATUS			0xf32c
-
-#define	MV64x60_COMM_ARBITER_CNTL		0xf300
-#define	MV64x60_COMM_CONFIG			0xb40c
-#define	MV64x60_COMM_XBAR_TO			0xf304
-#define	MV64x60_COMM_INTR_CAUSE			0xf310
-#define	MV64x60_COMM_INTR_MASK			0xf314
-#define	MV64x60_COMM_ERR_ADDR			0xf318
-
-#define MV64360_COMM_ARBITER_CNTL		0xf300
-
-/*
- *****************************************************************************
- *
- *	IDMA Controller Interface Registers
- *
- *****************************************************************************
- */
-
-/* IDMA Controller Window Registers (8 windows) */
-#define	MV64360_IDMA2MEM_WINDOWS		8
-
-#define	MV64360_IDMA2MEM_0_BASE			0x0a00
-#define	MV64360_IDMA2MEM_0_SIZE			0x0a04
-#define	MV64360_IDMA2MEM_1_BASE			0x0a08
-#define	MV64360_IDMA2MEM_1_SIZE			0x0a0c
-#define	MV64360_IDMA2MEM_2_BASE			0x0a10
-#define	MV64360_IDMA2MEM_2_SIZE			0x0a14
-#define	MV64360_IDMA2MEM_3_BASE			0x0a18
-#define	MV64360_IDMA2MEM_3_SIZE			0x0a1c
-#define	MV64360_IDMA2MEM_4_BASE			0x0a20
-#define	MV64360_IDMA2MEM_4_SIZE			0x0a24
-#define	MV64360_IDMA2MEM_5_BASE			0x0a28
-#define	MV64360_IDMA2MEM_5_SIZE			0x0a2c
-#define	MV64360_IDMA2MEM_6_BASE			0x0a30
-#define	MV64360_IDMA2MEM_6_SIZE			0x0a34
-#define	MV64360_IDMA2MEM_7_BASE			0x0a38
-#define	MV64360_IDMA2MEM_7_SIZE			0x0a3c
-
-#define	MV64360_IDMA2MEM_SNOOP_NONE		0x00000000
-#define	MV64360_IDMA2MEM_SNOOP_WT		0x00001000
-#define	MV64360_IDMA2MEM_SNOOP_WB		0x00002000
-
-#define	MV64360_IDMA2MEM_BAR_ENABLE		0x0a80
-
-#define	MV64360_IDMA2MEM_ACC_PROT_0		0x0a70
-#define	MV64360_IDMA2MEM_ACC_PROT_1		0x0a74
-#define	MV64360_IDMA2MEM_ACC_PROT_2		0x0a78
-#define	MV64360_IDMA2MEM_ACC_PROT_3		0x0a7c
-
-#define	MV64x60_IDMA_0_OFFSET			0x0800
-#define	MV64x60_IDMA_1_OFFSET			0x0804
-#define	MV64x60_IDMA_2_OFFSET			0x0808
-#define	MV64x60_IDMA_3_OFFSET			0x080c
-#define	MV64x60_IDMA_4_OFFSET			0x0900
-#define	MV64x60_IDMA_5_OFFSET			0x0904
-#define	MV64x60_IDMA_6_OFFSET			0x0908
-#define	MV64x60_IDMA_7_OFFSET			0x090c
-
-#define	MV64x60_IDMA_BYTE_COUNT			(0x0800 - MV64x60_IDMA_0_OFFSET)
-#define	MV64x60_IDMA_SRC_ADDR			(0x0810 - MV64x60_IDMA_0_OFFSET)
-#define	MV64x60_IDMA_DST_ADDR			(0x0820 - MV64x60_IDMA_0_OFFSET)
-#define	MV64x60_IDMA_NEXT_DESC			(0x0830 - MV64x60_IDMA_0_OFFSET)
-#define	MV64x60_IDMA_CUR_DESC			(0x0870 - MV64x60_IDMA_0_OFFSET)
-#define	MV64x60_IDMA_SRC_PCI_ADDR_HI		(0x0890 - MV64x60_IDMA_0_OFFSET)
-#define	MV64x60_IDMA_DST_PCI_ADDR_HI		(0x08a0 - MV64x60_IDMA_0_OFFSET)
-#define	MV64x60_IDMA_NEXT_DESC_PCI_ADDR_HI	(0x08b0 - MV64x60_IDMA_0_OFFSET)
-#define	MV64x60_IDMA_CONTROL_LO			(0x0840 - MV64x60_IDMA_0_OFFSET)
-#define	MV64x60_IDMA_CONTROL_HI			(0x0880 - MV64x60_IDMA_0_OFFSET)
-
-#define	MV64x60_IDMA_0_3_ARBITER_CNTL		0x0860
-#define	MV64x60_IDMA_4_7_ARBITER_CNTL		0x0960
-
-#define	MV64x60_IDMA_0_3_XBAR_TO		0x08d0
-#define	MV64x60_IDMA_4_7_XBAR_TO		0x09d0
-
-#define	MV64x60_IDMA_0_3_INTR_CAUSE		0x08c0
-#define	MV64x60_IDMA_0_3_INTR_MASK		0x08c4
-#define	MV64x60_IDMA_0_3_ERROR_ADDR		0x08c8
-#define	MV64x60_IDMA_0_3_ERROR_SELECT		0x08cc
-#define	MV64x60_IDMA_4_7_INTR_CAUSE		0x09c0
-#define	MV64x60_IDMA_4_7_INTR_MASK		0x09c4
-#define	MV64x60_IDMA_4_7_ERROR_ADDR		0x09c8
-#define	MV64x60_IDMA_4_7_ERROR_SELECT		0x09cc
-
-/*
- *****************************************************************************
- *
- *	Watchdog Timer Interface Registers
- *
- *****************************************************************************
- */
-
-#define	MV64x60_WDT_WDC				0xb410
-#define	MV64x60_WDT_WDV				0xb414
-
-
-/*
- *****************************************************************************
- *
- *	 General Purpose Pins Controller Interface Registers
- *
- *****************************************************************************
- */
-
-#define	MV64x60_GPP_IO_CNTL			0xf100
-#define	MV64x60_GPP_LEVEL_CNTL			0xf110
-#define	MV64x60_GPP_VALUE			0xf104
-#define	MV64x60_GPP_INTR_CAUSE			0xf108
-#define	MV64x60_GPP_INTR_MASK			0xf10c
-#define	MV64x60_GPP_VALUE_SET			0xf118
-#define	MV64x60_GPP_VALUE_CLR			0xf11c
-
-
-/*
- *****************************************************************************
- *
- *	Multi-Purpose Pins Controller Interface Registers
- *
- *****************************************************************************
- */
-
-#define	MV64x60_MPP_CNTL_0			0xf000
-#define	MV64x60_MPP_CNTL_1			0xf004
-#define	MV64x60_MPP_CNTL_2			0xf008
-#define	MV64x60_MPP_CNTL_3			0xf00c
-#define	GT64260_MPP_SERIAL_PORTS_MULTIPLEX	0xf010
-
-#define MV64x60_ETH_BAR_GAP			0x8
-#define MV64x60_ETH_SIZE_REG_GAP		0x8
-#define MV64x60_ETH_HIGH_ADDR_REMAP_REG_GAP	0x4
-#define MV64x60_ETH_PORT_ACCESS_CTRL_GAP	0x4
-
-#define MV64x60_EBAR_ATTR_DRAM_CS0		0x00000E00
-#define MV64x60_EBAR_ATTR_DRAM_CS1		0x00000D00
-#define MV64x60_EBAR_ATTR_DRAM_CS2		0x00000B00
-#define MV64x60_EBAR_ATTR_DRAM_CS3		0x00000700
-
-#define MV64x60_EBAR_ATTR_CBS_SRAM_BLOCK0	0x00000000
-#define MV64x60_EBAR_ATTR_CBS_SRAM_BLOCK1	0x00000100
-#define MV64x60_EBAR_ATTR_CBS_SRAM		0x00000000
-#define MV64x60_EBAR_ATTR_CBS_CPU_BUS		0x00000800
-
-
-/*
- *****************************************************************************
- *
- *	Interrupt Controller Interface Registers
- *
- *****************************************************************************
- */
-
-#define	GT64260_IC_OFFSET			0x0c18
-
-#define	GT64260_IC_MAIN_CAUSE_LO		0x0c18
-#define	GT64260_IC_MAIN_CAUSE_HI		0x0c68
-#define	GT64260_IC_CPU_INTR_MASK_LO		0x0c1c
-#define	GT64260_IC_CPU_INTR_MASK_HI		0x0c6c
-#define	GT64260_IC_CPU_SELECT_CAUSE		0x0c70
-#define	GT64260_IC_PCI0_INTR_MASK_LO		0x0c24
-#define	GT64260_IC_PCI0_INTR_MASK_HI		0x0c64
-#define	GT64260_IC_PCI0_SELECT_CAUSE		0x0c74
-#define	GT64260_IC_PCI1_INTR_MASK_LO		0x0ca4
-#define	GT64260_IC_PCI1_INTR_MASK_HI		0x0ce4
-#define	GT64260_IC_PCI1_SELECT_CAUSE		0x0cf4
-#define	GT64260_IC_CPU_INT_0_MASK		0x0e60
-#define	GT64260_IC_CPU_INT_1_MASK		0x0e64
-#define	GT64260_IC_CPU_INT_2_MASK		0x0e68
-#define	GT64260_IC_CPU_INT_3_MASK		0x0e6c
-
-#define	MV64360_IC_OFFSET			0x0000
-
-#define	MV64360_IC_MAIN_CAUSE_LO		0x0004
-#define	MV64360_IC_MAIN_CAUSE_HI		0x000c
-#define	MV64360_IC_CPU0_INTR_MASK_LO		0x0014
-#define	MV64360_IC_CPU0_INTR_MASK_HI		0x001c
-#define	MV64360_IC_CPU0_SELECT_CAUSE		0x0024
-#define	MV64360_IC_CPU1_INTR_MASK_LO		0x0034
-#define	MV64360_IC_CPU1_INTR_MASK_HI		0x003c
-#define	MV64360_IC_CPU1_SELECT_CAUSE		0x0044
-#define	MV64360_IC_INT0_MASK_LO			0x0054
-#define	MV64360_IC_INT0_MASK_HI			0x005c
-#define	MV64360_IC_INT0_SELECT_CAUSE		0x0064
-#define	MV64360_IC_INT1_MASK_LO			0x0074
-#define	MV64360_IC_INT1_MASK_HI			0x007c
-#define	MV64360_IC_INT1_SELECT_CAUSE		0x0084
-
-#endif /* __ASMPPC_MV64x60_DEFS_H */
diff --git a/include/asm-ppc/ocp.h b/include/asm-ppc/ocp.h
deleted file mode 100644
index 3909a2eec28..00000000000
--- a/include/asm-ppc/ocp.h
+++ /dev/null
@@ -1,204 +0,0 @@
-/*
- * ocp.h
- *
- *      (c) Benjamin Herrenschmidt (benh@kernel.crashing.org)
- *          Mipsys - France
- *
- *          Derived from work (c) Armin Kuster akuster@pacbell.net
- *
- *          Additional support and port to 2.6 LDM/sysfs by
- *          Matt Porter <mporter@kernel.crashing.org>
- *          Copyright 2003-2004 MontaVista Software, Inc.
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- *
- *  TODO: - Add get/put interface & fixup locking to provide same API for
- *          2.4 and 2.5
- *	  - Rework PM callbacks
- */
-
-#ifdef __KERNEL__
-#ifndef __OCP_H__
-#define __OCP_H__
-
-#include <linux/init.h>
-#include <linux/list.h>
-#include <linux/device.h>
-#include <linux/rwsem.h>
-
-#include <asm/mmu.h>
-#include <asm/ocp_ids.h>
-
-#ifdef CONFIG_PPC_OCP
-
-#define OCP_MAX_IRQS	7
-#define MAX_EMACS	4
-#define OCP_IRQ_NA	-1	/* used when ocp device does not have an irq */
-#define OCP_IRQ_MUL	-2	/* used for ocp devices with multiply irqs */
-#define OCP_NULL_TYPE	-1	/* used to mark end of list */
-#define OCP_CPM_NA	0	/* No Clock or Power Management avaliable */
-#define OCP_PADDR_NA	0	/* No MMIO registers */
-
-#define OCP_ANY_ID	(~0)
-#define OCP_ANY_INDEX	-1
-
-extern struct list_head 	ocp_devices;
-extern struct rw_semaphore	ocp_devices_sem;
-
-struct ocp_device_id {
-	unsigned int	vendor, function;	/* Vendor and function ID or OCP_ANY_ID */
-	unsigned long	driver_data;		/* Data private to the driver */
-};
-
-
-/*
- * Static definition of an OCP device.
- *
- * @vendor:    Vendor code. It is _STRONGLY_ discouraged to use
- *             the vendor code as a way to match a unique device,
- *             though I kept that possibility open, you should
- *             really define different function codes for different
- *             device types
- * @function:  This is the function code for this device.
- * @index:     This index is used for mapping the Nth function of a
- *             given core. This is typically used for cross-driver
- *             matching, like looking for a given MAL or ZMII from
- *             an EMAC or for getting to the proper set of DCRs.
- *             Indices are no longer magically calculated based on
- *             structure ordering, they have to be actually coded
- *             into the ocp_def to avoid any possible confusion
- *             I _STRONGLY_ (again ? wow !) encourage anybody relying
- *             on index mapping to encode the "target" index in an
- *             associated structure pointed to by "additions", see
- *             how it's done for the EMAC driver.
- * @paddr:     Device physical address (may not mean anything...)
- * @irq:       Interrupt line for this device (TODO: think about making
- *             an array with this)
- * @pm:        Currently, contains the bitmask in CPMFR DCR for the device
- * @additions: Optionally points to a function specific structure
- *             providing additional informations for a given device
- *             instance. It's currently used by the EMAC driver for MAL
- *             channel & ZMII port mapping among others.
- * @show:      Optionally points to a function specific structure
- *             providing a sysfs show routine for additions fields.
- */
-struct ocp_def {
-	unsigned int	vendor;
-	unsigned int	function;
-	int		index;
-	phys_addr_t	paddr;
-	int	  	irq;
-	unsigned long	pm;
-	void		*additions;
-	void		(*show)(struct device *);
-};
-
-
-/* Struct for a given device instance */
-struct ocp_device {
-	struct list_head	link;
-	char			name[80];	/* device name */
-	struct ocp_def		*def;		/* device definition */
-	void			*drvdata;	/* driver data for this device */
-	struct ocp_driver	*driver;
-	u32			current_state;	/* Current operating state. In ACPI-speak,
-						   this is D0-D3, D0 being fully functional,
-						   and D3 being off. */
-	struct			device dev;
-};
-
-struct ocp_driver {
-	struct list_head node;
-	char *name;
-	const struct ocp_device_id *id_table;	/* NULL if wants all devices */
-	int  (*probe)  (struct ocp_device *dev);	/* New device inserted */
-	void (*remove) (struct ocp_device *dev);	/* Device removed (NULL if not a hot-plug capable driver) */
-	int  (*suspend) (struct ocp_device *dev, pm_message_t state);	/* Device suspended */
-	int  (*resume) (struct ocp_device *dev);	                /* Device woken up */
-	struct device_driver driver;
-};
-
-#define to_ocp_dev(n) container_of(n, struct ocp_device, dev)
-#define to_ocp_drv(n) container_of(n, struct ocp_driver, driver)
-
-/* Similar to the helpers above, these manipulate per-ocp_dev
- * driver-specific data.  Currently stored as ocp_dev::ocpdev,
- * a void pointer, but it is not present on older kernels.
- */
-static inline void *
-ocp_get_drvdata(struct ocp_device *pdev)
-{
-	return pdev->drvdata;
-}
-
-static inline void
-ocp_set_drvdata(struct ocp_device *pdev, void *data)
-{
-	pdev->drvdata = data;
-}
-
-#if defined (CONFIG_PM)
-/*
- * This is right for the IBM 405 and 440 but will need to be
- * generalized if the OCP stuff gets used on other processors.
- */
-static inline void
-ocp_force_power_off(struct ocp_device *odev)
-{
-	mtdcr(DCRN_CPMFR, mfdcr(DCRN_CPMFR) | odev->def->pm);
-}
-
-static inline void
-ocp_force_power_on(struct ocp_device *odev)
-{
-	mtdcr(DCRN_CPMFR, mfdcr(DCRN_CPMFR) & ~odev->def->pm);
-}
-#else
-#define ocp_force_power_off(x)	(void)(x)
-#define ocp_force_power_on(x)	(void)(x)
-#endif
-
-/* Register/Unregister an OCP driver */
-extern int ocp_register_driver(struct ocp_driver *drv);
-extern void ocp_unregister_driver(struct ocp_driver *drv);
-
-/* Build list of devices */
-extern int ocp_early_init(void) __init;
-
-/* Find a device by index */
-extern struct ocp_device *ocp_find_device(unsigned int vendor, unsigned int function, int index);
-
-/* Get a def by index */
-extern struct ocp_def *ocp_get_one_device(unsigned int vendor, unsigned int function, int index);
-
-/* Add a device by index */
-extern int ocp_add_one_device(struct ocp_def *def);
-
-/* Remove a device by index */
-extern int ocp_remove_one_device(unsigned int vendor, unsigned int function, int index);
-
-/* Iterate over devices and execute a routine */
-extern void ocp_for_each_device(void(*callback)(struct ocp_device *, void *arg), void *arg);
-
-/* Sysfs support */
-#define OCP_SYSFS_ADDTL(type, format, name, field)			\
-static ssize_t								\
-show_##name##_##field(struct device *dev, struct device_attribute *attr, char *buf)			\
-{									\
-	struct ocp_device *odev = to_ocp_dev(dev);			\
-	type *add = odev->def->additions;				\
-									\
-	return sprintf(buf, format, add->field);			\
-}									\
-static DEVICE_ATTR(name##_##field, S_IRUGO, show_##name##_##field, NULL);
-
-#ifdef CONFIG_IBM_OCP
-#include <asm/ibm_ocp.h>
-#endif
-
-#endif				/* CONFIG_PPC_OCP */
-#endif				/* __OCP_H__ */
-#endif				/* __KERNEL__ */
diff --git a/include/asm-ppc/ocp_ids.h b/include/asm-ppc/ocp_ids.h
deleted file mode 100644
index 8ae4b311a37..00000000000
--- a/include/asm-ppc/ocp_ids.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * ocp_ids.h
- *
- * OCP device ids based on the ideas from PCI
- *
- * The numbers below are almost completely arbitrary, and in fact
- * strings might work better.  -- paulus
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-
-/*
- * Vender  device
- * [xxxx]  [xxxx]
- *
- *  Keep in order, please
- */
-
-/* Vendor IDs 0x0001 - 0xFFFF copied from pci_ids.h */
-
-#define	OCP_VENDOR_INVALID	0x0000
-#define	OCP_VENDOR_ARM		0x0004
-#define OCP_VENDOR_FREESCALE	0x1057
-#define OCP_VENDOR_IBM		0x1014
-#define OCP_VENDOR_MOTOROLA	OCP_VENDOR_FREESCALE
-#define	OCP_VENDOR_XILINX	0x10ee
-#define	OCP_VENDOR_UNKNOWN	0xFFFF
-
-/* device identification */
-
-/* define type */
-#define OCP_FUNC_INVALID	0x0000
-
-/* system 0x0001 - 0x001F */
-
-/* Timers 0x0020 - 0x002F */
-
-/* Serial 0x0030 - 0x006F*/
-#define OCP_FUNC_16550		0x0031
-#define OCP_FUNC_IIC		0x0032
-#define OCP_FUNC_USB		0x0033
-#define OCP_FUNC_PSC_UART	0x0034
-
-/* Memory devices 0x0090 - 0x009F */
-#define OCP_FUNC_MAL		0x0090
-#define OCP_FUNC_DMA		0x0091
-
-/* Display 0x00A0 - 0x00AF */
-
-/* Sound 0x00B0 - 0x00BF */
-
-/* Mass Storage 0x00C0 - 0xxCF */
-#define OCP_FUNC_IDE		0x00C0
-
-/* Misc 0x00D0 - 0x00DF*/
-#define OCP_FUNC_GPIO		0x00D0
-#define OCP_FUNC_ZMII		0x00D1
-#define OCP_FUNC_PERFMON	0x00D2	/* Performance Monitor */
-#define OCP_FUNC_RGMII		0x00D3
-#define OCP_FUNC_TAH		0x00D4
-#define OCP_FUNC_SEC2		0x00D5	/* Crypto/Security 2.0 */
-
-/* Network 0x0200 - 0x02FF */
-#define OCP_FUNC_EMAC		0x0200
-#define OCP_FUNC_GFAR		0x0201	/* TSEC & FEC */
-
-/* Bridge devices 0xE00 - 0xEFF */
-#define OCP_FUNC_OPB		0x0E00
-
-#define OCP_FUNC_UNKNOWN	0xFFFF
diff --git a/include/asm-ppc/open_pic.h b/include/asm-ppc/open_pic.h
deleted file mode 100644
index 778d5726212..00000000000
--- a/include/asm-ppc/open_pic.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- *  include/asm-ppc/open_pic.h -- OpenPIC Interrupt Handling
- *
- *  Copyright (C) 1997 Geert Uytterhoeven
- *
- *  This file is subject to the terms and conditions of the GNU General Public
- *  License.  See the file COPYING in the main directory of this archive
- *  for more details.
- *
- */
-
-#ifndef _PPC_KERNEL_OPEN_PIC_H
-#define _PPC_KERNEL_OPEN_PIC_H
-
-#include <linux/irq.h>
-
-#define OPENPIC_SIZE	0x40000
-
-/*
- *  Non-offset'ed vector numbers
- */
-
-#define OPENPIC_VEC_TIMER	110	/* and up */
-#define OPENPIC_VEC_IPI		118	/* and up */
-#define OPENPIC_VEC_SPURIOUS	255
-
-/* Priorities */
-#define OPENPIC_PRIORITY_IPI_BASE	10
-#define OPENPIC_PRIORITY_DEFAULT	4
-#define OPENPIC_PRIORITY_NMI		9
-
-/* OpenPIC IRQ controller structure */
-extern struct hw_interrupt_type open_pic;
-
-/* OpenPIC IPI controller structure */
-#ifdef CONFIG_SMP
-extern struct hw_interrupt_type open_pic_ipi;
-#endif /* CONFIG_SMP */
-
-extern u_int OpenPIC_NumInitSenses;
-extern u_char *OpenPIC_InitSenses;
-extern void __iomem * OpenPIC_Addr;
-extern int epic_serial_mode;
-
-/* Exported functions */
-extern void openpic_set_sources(int first_irq, int num_irqs, void __iomem *isr);
-extern void openpic_init(int linux_irq_offset);
-extern void openpic_init_nmi_irq(u_int irq);
-extern void openpic_set_irq_priority(u_int irq, u_int pri);
-extern void openpic_hookup_cascade(u_int irq, char *name,
-				   int (*cascade_fn)(void));
-extern u_int openpic_irq(void);
-extern void openpic_eoi(void);
-extern void openpic_request_IPIs(void);
-extern void do_openpic_setup_cpu(void);
-extern int openpic_get_irq(void);
-extern void openpic_reset_processor_phys(u_int cpumask);
-extern void openpic_setup_ISU(int isu_num, unsigned long addr);
-extern void openpic_cause_IPI(u_int ipi, cpumask_t cpumask);
-extern void smp_openpic_message_pass(int target, int msg);
-extern void openpic_set_k2_cascade(int irq);
-extern void openpic_set_priority(u_int pri);
-extern u_int openpic_get_priority(void);
-
-extern inline int openpic_to_irq(int irq)
-{
-	/* IRQ 0 usually means 'disabled'.. don't mess with it
-	 * exceptions to this (sandpoint maybe?)
-	 * shouldn't use openpic_to_irq
-	 */
-	if (irq != 0){
-		return irq += NUM_8259_INTERRUPTS;
-	} else {
-		return 0;
-	}
-}
-/* Support for second openpic on G5 macs */
-
-// FIXME: To be replaced by sane cascaded controller management */
-
-#define PMAC_OPENPIC2_OFFSET	128
-
-#define OPENPIC2_VEC_TIMER	110	/* and up */
-#define OPENPIC2_VEC_IPI	118	/* and up */
-#define OPENPIC2_VEC_SPURIOUS	127
-
-
-extern void* OpenPIC2_Addr;
-
-/* Exported functions */
-extern void openpic2_set_sources(int first_irq, int num_irqs, void *isr);
-extern void openpic2_init(int linux_irq_offset);
-extern void openpic2_init_nmi_irq(u_int irq);
-extern u_int openpic2_irq(void);
-extern void openpic2_eoi(void);
-extern int openpic2_get_irq(void);
-extern void openpic2_setup_ISU(int isu_num, unsigned long addr);
-#endif /* _PPC_KERNEL_OPEN_PIC_H */
diff --git a/include/asm-ppc/page.h b/include/asm-ppc/page.h
deleted file mode 100644
index 37e4756b6b2..00000000000
--- a/include/asm-ppc/page.h
+++ /dev/null
@@ -1,140 +0,0 @@
-#ifndef _PPC_PAGE_H
-#define _PPC_PAGE_H
-
-#include <asm/asm-compat.h>
-
-/* PAGE_SHIFT determines the page size */
-#define PAGE_SHIFT	12
-#define PAGE_SIZE	(ASM_CONST(1) << PAGE_SHIFT)
-
-/*
- * Subtle: this is an int (not an unsigned long) and so it
- * gets extended to 64 bits the way want (i.e. with 1s).  -- paulus
- */
-#define PAGE_MASK	(~((1 << PAGE_SHIFT) - 1))
-
-#ifdef __KERNEL__
-
-/* This must match what is in arch/ppc/Makefile */
-#define PAGE_OFFSET	CONFIG_KERNEL_START
-#define KERNELBASE	PAGE_OFFSET
-#define is_kernel_addr(x)	((x) >= PAGE_OFFSET)
-
-#ifndef __ASSEMBLY__
-
-/*
- * The basic type of a PTE - 64 bits for those CPUs with > 32 bit
- * physical addressing.  For now this just the IBM PPC440.
- */
-#ifdef CONFIG_PTE_64BIT
-typedef unsigned long long pte_basic_t;
-#define PTE_SHIFT	(PAGE_SHIFT - 3)	/* 512 ptes per page */
-#define PTE_FMT		"%16Lx"
-#else
-typedef unsigned long pte_basic_t;
-#define PTE_SHIFT	(PAGE_SHIFT - 2)	/* 1024 ptes per page */
-#define PTE_FMT		"%.8lx"
-#endif
-
-/* align addr on a size boundary - adjust address up/down if needed */
-#define _ALIGN_UP(addr,size)	(((addr)+((size)-1))&(~((size)-1)))
-#define _ALIGN_DOWN(addr,size)	((addr)&(~((size)-1)))
-
-/* align addr on a size boundary - adjust address up if needed */
-#define _ALIGN(addr,size)     _ALIGN_UP(addr,size)
-
-/* to align the pointer to the (next) page boundary */
-#define PAGE_ALIGN(addr)	_ALIGN(addr, PAGE_SIZE)
-
-
-#undef STRICT_MM_TYPECHECKS
-
-#ifdef STRICT_MM_TYPECHECKS
-/*
- * These are used to make use of C type-checking..
- */
-typedef struct { pte_basic_t pte; } pte_t;
-typedef struct { unsigned long pmd; } pmd_t;
-typedef struct { unsigned long pgd; } pgd_t;
-typedef struct { unsigned long pgprot; } pgprot_t;
-
-#define pte_val(x)	((x).pte)
-#define pmd_val(x)	((x).pmd)
-#define pgd_val(x)	((x).pgd)
-#define pgprot_val(x)	((x).pgprot)
-
-#define __pte(x)	((pte_t) { (x) } )
-#define __pmd(x)	((pmd_t) { (x) } )
-#define __pgd(x)	((pgd_t) { (x) } )
-#define __pgprot(x)	((pgprot_t) { (x) } )
-
-#else
-/*
- * .. while these make it easier on the compiler
- */
-typedef pte_basic_t pte_t;
-typedef unsigned long pmd_t;
-typedef unsigned long pgd_t;
-typedef unsigned long pgprot_t;
-
-#define pte_val(x)	(x)
-#define pmd_val(x)	(x)
-#define pgd_val(x)	(x)
-#define pgprot_val(x)	(x)
-
-#define __pte(x)	(x)
-#define __pmd(x)	(x)
-#define __pgd(x)	(x)
-#define __pgprot(x)	(x)
-
-#endif
-
-struct page;
-extern void clear_pages(void *page, int order);
-static inline void clear_page(void *page) { clear_pages(page, 0); }
-extern void copy_page(void *to, void *from);
-extern void clear_user_page(void *page, unsigned long vaddr, struct page *pg);
-extern void copy_user_page(void *to, void *from, unsigned long vaddr,
-			   struct page *pg);
-
-#define PPC_MEMSTART	0
-#define PPC_MEMOFFSET	PAGE_OFFSET
-
-#define ___pa(vaddr) ((vaddr)-PPC_MEMOFFSET)
-#define ___va(paddr) ((paddr)+PPC_MEMOFFSET)
-
-extern int page_is_ram(unsigned long pfn);
-
-#define __pa(x) ___pa((unsigned long)(x))
-#define __va(x) ((void *)(___va((unsigned long)(x))))
-
-#define ARCH_PFN_OFFSET		0
-#define virt_to_page(kaddr)	pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
-#define page_to_virt(page)	__va(page_to_pfn(page) << PAGE_SHIFT)
-
-#define pfn_valid(pfn)		((pfn) < max_mapnr)
-#define virt_addr_valid(kaddr)	pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
-
-/* Pure 2^n version of get_order */
-extern __inline__ int get_order(unsigned long size)
-{
-	int lz;
-
-	size = (size-1) >> PAGE_SHIFT;
-	asm ("cntlzw %0,%1" : "=r" (lz) : "r" (size));
-	return 32 - lz;
-}
-
-typedef struct page *pgtable_t;
-
-#endif /* __ASSEMBLY__ */
-
-#define VM_DATA_DEFAULT_FLAGS	(VM_READ | VM_WRITE | VM_EXEC | \
-				 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
-
-/* We do define AT_SYSINFO_EHDR but don't use the gate mechanism */
-#define __HAVE_ARCH_GATE_AREA		1
-
-#include <asm-generic/memory_model.h>
-#endif /* __KERNEL__ */
-#endif /* _PPC_PAGE_H */
diff --git a/include/asm-ppc/pc_serial.h b/include/asm-ppc/pc_serial.h
deleted file mode 100644
index 81a2d0fdaf0..00000000000
--- a/include/asm-ppc/pc_serial.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * include/asm-ppc/pc_serial.h
- *
- * This is basically a copy of include/asm-i386/serial.h.
- * It is used on platforms which have an ISA bus and thus are likely
- * to have PC-style serial ports at the legacy I/O port addresses.
- * It also includes the definitions for the fourport, accent, boca
- * and hub6 multiport serial cards, although I have never heard of
- * anyone using any of those on a PPC platform.  -- paulus
- */
-
-
-/*
- * This assumes you have a 1.8432 MHz clock for your UART.
- *
- * It'd be nice if someone built a serial card with a 24.576 MHz
- * clock, since the 16550A is capable of handling a top speed of 1.5
- * megabits/second; but this requires the faster clock.
- */
-#define BASE_BAUD ( 1843200 / 16 )
-
-#ifdef CONFIG_SERIAL_MANY_PORTS
-#define RS_TABLE_SIZE  64
-#else
-#define RS_TABLE_SIZE  4
-#endif
-
-/* Standard COM flags (except for COM4, because of the 8514 problem) */
-#ifdef CONFIG_SERIAL_DETECT_IRQ
-#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST | ASYNC_AUTO_IRQ)
-#define STD_COM4_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_AUTO_IRQ)
-#else
-#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
-#define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF
-#endif
-
-#define SERIAL_PORT_DFNS			\
-	/* UART CLK   PORT IRQ     FLAGS        */			\
-	{ 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS },	/* ttyS0 */	\
-	{ 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS },	/* ttyS1 */	\
-	{ 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS },	/* ttyS2 */	\
-	{ 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS },	/* ttyS3 */
diff --git a/include/asm-ppc/pci-bridge.h b/include/asm-ppc/pci-bridge.h
deleted file mode 100644
index 4d35b844bc5..00000000000
--- a/include/asm-ppc/pci-bridge.h
+++ /dev/null
@@ -1,151 +0,0 @@
-#ifdef __KERNEL__
-#ifndef _ASM_PCI_BRIDGE_H
-#define _ASM_PCI_BRIDGE_H
-
-#include <linux/ioport.h>
-#include <linux/pci.h>
-
-struct device_node;
-struct pci_controller;
-
-/*
- * pci_io_base returns the memory address at which you can access
- * the I/O space for PCI bus number `bus' (or NULL on error).
- */
-extern void __iomem *pci_bus_io_base(unsigned int bus);
-extern unsigned long pci_bus_io_base_phys(unsigned int bus);
-extern unsigned long pci_bus_mem_base_phys(unsigned int bus);
-
-/* Allocate a new PCI host bridge structure */
-extern struct pci_controller* pcibios_alloc_controller(void);
-
-/* Helper function for setting up resources */
-extern void pci_init_resource(struct resource *res, resource_size_t start,
-			      resource_size_t end, int flags, char *name);
-
-/* Get the PCI host controller for a bus */
-extern struct pci_controller* pci_bus_to_hose(int bus);
-
-/* Get the PCI host controller for an OF device */
-extern struct pci_controller*
-pci_find_hose_for_OF_device(struct device_node* node);
-
-/* Fill up host controller resources from the OF node */
-extern void
-pci_process_bridge_OF_ranges(struct pci_controller *hose,
-			   struct device_node *dev, int primary);
-
-/*
- * Structure of a PCI controller (host bridge)
- */
-struct pci_controller {
-	int index;			/* PCI domain number */
-	struct pci_controller *next;
-        struct pci_bus *bus;
-	void *arch_data;
-	struct device *parent;
-
-	int first_busno;
-	int last_busno;
-	int bus_offset;
-
-	void __iomem *io_base_virt;
-	resource_size_t io_base_phys;
-
-	/* Some machines (PReP) have a non 1:1 mapping of
-	 * the PCI memory space in the CPU bus space
-	 */
-	resource_size_t pci_mem_offset;
-
-	struct pci_ops *ops;
-	volatile unsigned int __iomem *cfg_addr;
-	volatile void __iomem *cfg_data;
-	/*
-	 * If set, indirect method will set the cfg_type bit as
-	 * needed to generate type 1 configuration transactions.
-	 */
-	int set_cfg_type;
-
-	/* Currently, we limit ourselves to 1 IO range and 3 mem
-	 * ranges since the common pci_bus structure can't handle more
-	 */
-	struct resource	io_resource;
-	struct resource mem_resources[3];
-	int mem_resource_count;
-
-	/* Host bridge I/O and Memory space
-	 * Used for BAR placement algorithms
-	 */
-	struct resource io_space;
-	struct resource mem_space;
-};
-
-static inline struct pci_controller *pci_bus_to_host(struct pci_bus *bus)
-{
-	return bus->sysdata;
-}
-
-/* These are used for config access before all the PCI probing
-   has been done. */
-int early_read_config_byte(struct pci_controller *hose, int bus, int dev_fn,
-			   int where, u8 *val);
-int early_read_config_word(struct pci_controller *hose, int bus, int dev_fn,
-			   int where, u16 *val);
-int early_read_config_dword(struct pci_controller *hose, int bus, int dev_fn,
-			    int where, u32 *val);
-int early_write_config_byte(struct pci_controller *hose, int bus, int dev_fn,
-			    int where, u8 val);
-int early_write_config_word(struct pci_controller *hose, int bus, int dev_fn,
-			    int where, u16 val);
-int early_write_config_dword(struct pci_controller *hose, int bus, int dev_fn,
-			     int where, u32 val);
-
-extern void setup_indirect_pci_nomap(struct pci_controller* hose,
-			       void __iomem *cfg_addr, void __iomem *cfg_data);
-extern void setup_indirect_pci(struct pci_controller* hose,
-			       u32 cfg_addr, u32 cfg_data);
-extern void setup_grackle(struct pci_controller *hose);
-
-extern unsigned char common_swizzle(struct pci_dev *, unsigned char *);
-
-/*
- *   The following code swizzles for exactly one bridge.  The routine
- *   common_swizzle below handles multiple bridges.  But there are a
- *   some boards that don't follow the PCI spec's suggestion so we
- *   break this piece out separately.
- */
-static inline unsigned char bridge_swizzle(unsigned char pin,
-		unsigned char idsel)
-{
-	return (((pin-1) + idsel) % 4) + 1;
-}
-
-/*
- * The following macro is used to lookup irqs in a standard table
- * format for those PPC systems that do not already have PCI
- * interrupts properly routed.
- */
-/* FIXME - double check this */
-#define PCI_IRQ_TABLE_LOOKUP						    \
-({ long _ctl_ = -1; 							    \
-   if (idsel >= min_idsel && idsel <= max_idsel && pin <= irqs_per_slot)    \
-     _ctl_ = pci_irq_table[idsel - min_idsel][pin-1];			    \
-   _ctl_; })
-
-/*
- * Scan the buses below a given PCI host bridge and assign suitable
- * resources to all devices found.
- */
-extern int pciauto_bus_scan(struct pci_controller *, int);
-
-#ifdef CONFIG_PCI
-extern unsigned long pci_address_to_pio(phys_addr_t address);
-#else
-static inline unsigned long pci_address_to_pio(phys_addr_t address)
-{
-	return (unsigned long)-1;
-}
-#endif
-
-#endif
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/pci.h b/include/asm-ppc/pci.h
deleted file mode 100644
index d2442cd72a5..00000000000
--- a/include/asm-ppc/pci.h
+++ /dev/null
@@ -1,156 +0,0 @@
-#ifndef __PPC_PCI_H
-#define __PPC_PCI_H
-#ifdef __KERNEL__
-
-#include <linux/types.h>
-#include <linux/slab.h>
-#include <linux/string.h>
-#include <linux/mm.h>
-#include <asm/scatterlist.h>
-#include <asm/io.h>
-#include <asm/pci-bridge.h>
-#include <asm-generic/pci-dma-compat.h>
-
-struct pci_dev;
-
-/* Values for the `which' argument to sys_pciconfig_iobase syscall.  */
-#define IOBASE_BRIDGE_NUMBER	0
-#define IOBASE_MEMORY		1
-#define IOBASE_IO		2
-#define IOBASE_ISA_IO		3
-#define IOBASE_ISA_MEM		4
-
-/*
- * Set this to 1 if you want the kernel to re-assign all PCI
- * bus numbers
- */
-extern int pci_assign_all_buses;
-
-#define pcibios_assign_all_busses()	(pci_assign_all_buses)
-#define pcibios_scan_all_fns(a, b)	0
-
-#define PCIBIOS_MIN_IO		0x1000
-#define PCIBIOS_MIN_MEM		0x10000000
-
-extern inline void pcibios_set_master(struct pci_dev *dev)
-{
-	/* No special bus mastering setup handling */
-}
-
-extern inline void pcibios_penalize_isa_irq(int irq, int active)
-{
-	/* We don't do dynamic PCI IRQ allocation */
-}
-
-extern unsigned long pci_resource_to_bus(struct pci_dev *pdev, struct resource *res);
-
-/*
- * The PCI bus bridge can translate addresses issued by the processor(s)
- * into a different address on the PCI bus.  On 32-bit cpus, we assume
- * this mapping is 1-1, but on 64-bit systems it often isn't.
- *
- * Obsolete ! Drivers should now use pci_resource_to_bus
- */
-extern unsigned long phys_to_bus(unsigned long pa);
-extern unsigned long pci_phys_to_bus(unsigned long pa, int busnr);
-extern unsigned long pci_bus_to_phys(unsigned int ba, int busnr);
-
-/* The PCI address space does equal the physical memory
- * address space.  The networking and block device layers use
- * this boolean for bounce buffer decisions.
- */
-#define PCI_DMA_BUS_IS_PHYS     (1)
-
-#ifdef CONFIG_NOT_COHERENT_CACHE
-/*
- * pci_unmap_{page,single} are NOPs but pci_dma_sync_single_for_cpu()
- * and so on are not, so...
- */
-
-#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)	\
-	dma_addr_t ADDR_NAME;
-#define DECLARE_PCI_UNMAP_LEN(LEN_NAME)		\
-	__u32 LEN_NAME;
-#define pci_unmap_addr(PTR, ADDR_NAME)			\
-	((PTR)->ADDR_NAME)
-#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL)		\
-	(((PTR)->ADDR_NAME) = (VAL))
-#define pci_unmap_len(PTR, LEN_NAME)			\
-	((PTR)->LEN_NAME)
-#define pci_unmap_len_set(PTR, LEN_NAME, VAL)		\
-	(((PTR)->LEN_NAME) = (VAL))
-
-#else /* coherent */
-
-/* pci_unmap_{page,single} is a nop so... */
-#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)
-#define DECLARE_PCI_UNMAP_LEN(LEN_NAME)
-#define pci_unmap_addr(PTR, ADDR_NAME)		(0)
-#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL)	do { } while (0)
-#define pci_unmap_len(PTR, LEN_NAME)		(0)
-#define pci_unmap_len_set(PTR, LEN_NAME, VAL)	do { } while (0)
-
-#endif /* CONFIG_NOT_COHERENT_CACHE */
-
-#ifdef CONFIG_PCI
-static inline void pci_dma_burst_advice(struct pci_dev *pdev,
-					enum pci_dma_burst_strategy *strat,
-					unsigned long *strategy_parameter)
-{
-	*strat = PCI_DMA_BURST_INFINITY;
-	*strategy_parameter = ~0UL;
-}
-#endif
-
-/* Return the index of the PCI controller for device PDEV. */
-#define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index
-
-/* Set the name of the bus as it appears in /proc/bus/pci */
-static inline int pci_proc_domain(struct pci_bus *bus)
-{
-	return 0;
-}
-
-/* Map a range of PCI memory or I/O space for a device into user space */
-int pci_mmap_page_range(struct pci_dev *pdev, struct vm_area_struct *vma,
-			enum pci_mmap_state mmap_state, int write_combine);
-
-/* Tell drivers/pci/proc.c that we have pci_mmap_page_range() */
-#define HAVE_PCI_MMAP	1
-
-extern void
-pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
-			struct resource *res);
-
-extern void
-pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
-			struct pci_bus_region *region);
-
-static inline struct resource *
-pcibios_select_root(struct pci_dev *pdev, struct resource *res)
-{
-	struct resource *root = NULL;
-
-	if (res->flags & IORESOURCE_IO)
-		root = &ioport_resource;
-	if (res->flags & IORESOURCE_MEM)
-		root = &iomem_resource;
-
-	return root;
-}
-
-struct file;
-extern pgprot_t	pci_phys_mem_access_prot(struct file *file,
-					 unsigned long pfn,
-					 unsigned long size,
-					 pgprot_t prot);
-
-#define HAVE_ARCH_PCI_RESOURCE_TO_USER
-extern void pci_resource_to_user(const struct pci_dev *dev, int bar,
-				 const struct resource *rsrc,
-				 resource_size_t *start, resource_size_t *end);
-
-
-#endif	/* __KERNEL__ */
-
-#endif /* __PPC_PCI_H */
diff --git a/include/asm-ppc/pgalloc.h b/include/asm-ppc/pgalloc.h
deleted file mode 100644
index fd4d1d74cfb..00000000000
--- a/include/asm-ppc/pgalloc.h
+++ /dev/null
@@ -1,45 +0,0 @@
-#ifdef __KERNEL__
-#ifndef _PPC_PGALLOC_H
-#define _PPC_PGALLOC_H
-
-#include <linux/threads.h>
-
-extern void __bad_pte(pmd_t *pmd);
-
-extern pgd_t *pgd_alloc(struct mm_struct *mm);
-extern void pgd_free(struct mm_struct *mm, pgd_t *pgd);
-
-/*
- * We don't have any real pmd's, and this code never triggers because
- * the pgd will always be present..
- */
-#define pmd_alloc_one(mm,address)       ({ BUG(); ((pmd_t *)2); })
-#define pmd_free(mm, x) 		do { } while (0)
-#define __pmd_free_tlb(tlb,x)		do { } while (0)
-#define pgd_populate(mm, pmd, pte)      BUG()
-
-#ifndef CONFIG_BOOKE
-#define pmd_populate_kernel(mm, pmd, pte)	\
-		(pmd_val(*(pmd)) = __pa(pte) | _PMD_PRESENT)
-#define pmd_populate(mm, pmd, pte)	\
-		(pmd_val(*(pmd)) = (page_to_pfn(pte) << PAGE_SHIFT) | _PMD_PRESENT)
-#define pmd_pgtable(pmd) pmd_page(pmd)
-#else
-#define pmd_populate_kernel(mm, pmd, pte)	\
-		(pmd_val(*(pmd)) = (unsigned long)pte | _PMD_PRESENT)
-#define pmd_populate(mm, pmd, pte)	\
-		(pmd_val(*(pmd)) = (unsigned long)lowmem_page_address(pte) | _PMD_PRESENT)
-#define pmd_pgtable(pmd) pmd_page(pmd)
-#endif
-
-extern pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long addr);
-extern pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long addr);
-extern void pte_free_kernel(struct mm_struct *mm, pte_t *pte);
-extern void pte_free(struct mm_struct *mm, pgtable_t pte);
-
-#define __pte_free_tlb(tlb, pte)	pte_free((tlb)->mm, (pte))
-
-#define check_pgt_cache()	do { } while (0)
-
-#endif /* _PPC_PGALLOC_H */
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/pgtable.h b/include/asm-ppc/pgtable.h
deleted file mode 100644
index 55f9d38e3bf..00000000000
--- a/include/asm-ppc/pgtable.h
+++ /dev/null
@@ -1,771 +0,0 @@
-#ifdef __KERNEL__
-#ifndef _PPC_PGTABLE_H
-#define _PPC_PGTABLE_H
-
-#include <asm-generic/4level-fixup.h>
-
-
-#ifndef __ASSEMBLY__
-#include <linux/sched.h>
-#include <linux/threads.h>
-#include <asm/processor.h>		/* For TASK_SIZE */
-#include <asm/mmu.h>
-#include <asm/page.h>
-#include <asm/io.h>			/* For sub-arch specific PPC_PIN_SIZE */
-struct mm_struct;
-
-extern unsigned long va_to_phys(unsigned long address);
-extern pte_t *va_to_pte(unsigned long address);
-extern unsigned long ioremap_bot, ioremap_base;
-#endif /* __ASSEMBLY__ */
-
-/*
- * The PowerPC MMU uses a hash table containing PTEs, together with
- * a set of 16 segment registers (on 32-bit implementations), to define
- * the virtual to physical address mapping.
- *
- * We use the hash table as an extended TLB, i.e. a cache of currently
- * active mappings.  We maintain a two-level page table tree, much
- * like that used by the i386, for the sake of the Linux memory
- * management code.  Low-level assembler code in hashtable.S
- * (procedure hash_page) is responsible for extracting ptes from the
- * tree and putting them into the hash table when necessary, and
- * updating the accessed and modified bits in the page table tree.
- */
-
-/*
- * The PowerPC MPC8xx uses a TLB with hardware assisted, software tablewalk.
- * We also use the two level tables, but we can put the real bits in them
- * needed for the TLB and tablewalk.  These definitions require Mx_CTR.PPM = 0,
- * Mx_CTR.PPCS = 0, and MD_CTR.TWAM = 1.  The level 2 descriptor has
- * additional page protection (when Mx_CTR.PPCS = 1) that allows TLB hit
- * based upon user/super access.  The TLB does not have accessed nor write
- * protect.  We assume that if the TLB get loaded with an entry it is
- * accessed, and overload the changed bit for write protect.  We use
- * two bits in the software pte that are supposed to be set to zero in
- * the TLB entry (24 and 25) for these indicators.  Although the level 1
- * descriptor contains the guarded and writethrough/copyback bits, we can
- * set these at the page level since they get copied from the Mx_TWC
- * register when the TLB entry is loaded.  We will use bit 27 for guard, since
- * that is where it exists in the MD_TWC, and bit 26 for writethrough.
- * These will get masked from the level 2 descriptor at TLB load time, and
- * copied to the MD_TWC before it gets loaded.
- * Large page sizes added.  We currently support two sizes, 4K and 8M.
- * This also allows a TLB hander optimization because we can directly
- * load the PMD into MD_TWC.  The 8M pages are only used for kernel
- * mapping of well known areas.  The PMD (PGD) entries contain control
- * flags in addition to the address, so care must be taken that the
- * software no longer assumes these are only pointers.
- */
-
-/*
- * At present, all PowerPC 400-class processors share a similar TLB
- * architecture. The instruction and data sides share a unified,
- * 64-entry, fully-associative TLB which is maintained totally under
- * software control. In addition, the instruction side has a
- * hardware-managed, 4-entry, fully-associative TLB which serves as a
- * first level to the shared TLB. These two TLBs are known as the UTLB
- * and ITLB, respectively (see "mmu.h" for definitions).
- */
-
-/*
- * The normal case is that PTEs are 32-bits and we have a 1-page
- * 1024-entry pgdir pointing to 1-page 1024-entry PTE pages.  -- paulus
- *
- * For any >32-bit physical address platform, we can use the following
- * two level page table layout where the pgdir is 8KB and the MS 13 bits
- * are an index to the second level table.  The combined pgdir/pmd first
- * level has 2048 entries and the second level has 512 64-bit PTE entries.
- * -Matt
- */
-/* PMD_SHIFT determines the size of the area mapped by the PTE pages */
-#define PMD_SHIFT	(PAGE_SHIFT + PTE_SHIFT)
-#define PMD_SIZE	(1UL << PMD_SHIFT)
-#define PMD_MASK	(~(PMD_SIZE-1))
-
-/* PGDIR_SHIFT determines what a top-level page table entry can map */
-#define PGDIR_SHIFT	PMD_SHIFT
-#define PGDIR_SIZE	(1UL << PGDIR_SHIFT)
-#define PGDIR_MASK	(~(PGDIR_SIZE-1))
-
-/*
- * entries per page directory level: our page-table tree is two-level, so
- * we don't really have any PMD directory.
- */
-#define PTRS_PER_PTE	(1 << PTE_SHIFT)
-#define PTRS_PER_PMD	1
-#define PTRS_PER_PGD	(1 << (32 - PGDIR_SHIFT))
-
-#define USER_PTRS_PER_PGD	(TASK_SIZE / PGDIR_SIZE)
-#define FIRST_USER_ADDRESS	0
-
-#define USER_PGD_PTRS (PAGE_OFFSET >> PGDIR_SHIFT)
-#define KERNEL_PGD_PTRS (PTRS_PER_PGD-USER_PGD_PTRS)
-
-#define pte_ERROR(e) \
-	printk("%s:%d: bad pte "PTE_FMT".\n", __FILE__, __LINE__, pte_val(e))
-#define pmd_ERROR(e) \
-	printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
-#define pgd_ERROR(e) \
-	printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
-
-/*
- * Just any arbitrary offset to the start of the vmalloc VM area: the
- * current 64MB value just means that there will be a 64MB "hole" after the
- * physical memory until the kernel virtual memory starts.  That means that
- * any out-of-bounds memory accesses will hopefully be caught.
- * The vmalloc() routines leaves a hole of 4kB between each vmalloced
- * area for the same reason. ;)
- *
- * We no longer map larger than phys RAM with the BATs so we don't have
- * to worry about the VMALLOC_OFFSET causing problems.  We do have to worry
- * about clashes between our early calls to ioremap() that start growing down
- * from ioremap_base being run into the VM area allocations (growing upwards
- * from VMALLOC_START).  For this reason we have ioremap_bot to check when
- * we actually run into our mappings setup in the early boot with the VM
- * system.  This really does become a problem for machines with good amounts
- * of RAM.  -- Cort
- */
-#define VMALLOC_OFFSET (0x1000000) /* 16M */
-#ifdef PPC_PIN_SIZE
-#define VMALLOC_START (((_ALIGN((long)high_memory, PPC_PIN_SIZE) + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
-#else
-#define VMALLOC_START ((((long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
-#endif
-#define VMALLOC_END	ioremap_bot
-
-/*
- * Bits in a linux-style PTE.  These match the bits in the
- * (hardware-defined) PowerPC PTE as closely as possible.
- */
-
-#if defined(CONFIG_40x)
-
-/* There are several potential gotchas here.  The 40x hardware TLBLO
-   field looks like this:
-
-   0  1  2  3  4  ... 18 19 20 21 22 23 24 25 26 27 28 29 30 31
-   RPN.....................  0  0 EX WR ZSEL.......  W  I  M  G
-
-   Where possible we make the Linux PTE bits match up with this
-
-   - bits 20 and 21 must be cleared, because we use 4k pages (40x can
-     support down to 1k pages), this is done in the TLBMiss exception
-     handler.
-   - We use only zones 0 (for kernel pages) and 1 (for user pages)
-     of the 16 available.  Bit 24-26 of the TLB are cleared in the TLB
-     miss handler.  Bit 27 is PAGE_USER, thus selecting the correct
-     zone.
-   - PRESENT *must* be in the bottom two bits because swap cache
-     entries use the top 30 bits.  Because 40x doesn't support SMP
-     anyway, M is irrelevant so we borrow it for PAGE_PRESENT.  Bit 30
-     is cleared in the TLB miss handler before the TLB entry is loaded.
-   - All other bits of the PTE are loaded into TLBLO without
-     modification, leaving us only the bits 20, 21, 24, 25, 26, 30 for
-     software PTE bits.  We actually use use bits 21, 24, 25, and
-     30 respectively for the software bits: ACCESSED, DIRTY, RW, and
-     PRESENT.
-*/
-
-/* Definitions for 40x embedded chips. */
-#define	_PAGE_GUARDED	0x001	/* G: page is guarded from prefetch */
-#define _PAGE_FILE	0x001	/* when !present: nonlinear file mapping */
-#define _PAGE_PRESENT	0x002	/* software: PTE contains a translation */
-#define	_PAGE_NO_CACHE	0x004	/* I: caching is inhibited */
-#define	_PAGE_WRITETHRU	0x008	/* W: caching is write-through */
-#define	_PAGE_USER	0x010	/* matches one of the zone permission bits */
-#define	_PAGE_RW	0x040	/* software: Writes permitted */
-#define	_PAGE_DIRTY	0x080	/* software: dirty page */
-#define _PAGE_HWWRITE	0x100	/* hardware: Dirty & RW, set in exception */
-#define _PAGE_HWEXEC	0x200	/* hardware: EX permission */
-#define _PAGE_ACCESSED	0x400	/* software: R: page referenced */
-
-#define _PMD_PRESENT	0x400	/* PMD points to page of PTEs */
-#define _PMD_BAD	0x802
-#define _PMD_SIZE	0x0e0	/* size field, != 0 for large-page PMD entry */
-#define _PMD_SIZE_4M	0x0c0
-#define _PMD_SIZE_16M	0x0e0
-#define PMD_PAGE_SIZE(pmdval)	(1024 << (((pmdval) & _PMD_SIZE) >> 4))
-
-#elif defined(CONFIG_44x)
-/*
- * Definitions for PPC440
- *
- * Because of the 3 word TLB entries to support 36-bit addressing,
- * the attribute are difficult to map in such a fashion that they
- * are easily loaded during exception processing.  I decided to
- * organize the entry so the ERPN is the only portion in the
- * upper word of the PTE and the attribute bits below are packed
- * in as sensibly as they can be in the area below a 4KB page size
- * oriented RPN.  This at least makes it easy to load the RPN and
- * ERPN fields in the TLB. -Matt
- *
- * Note that these bits preclude future use of a page size
- * less than 4KB.
- *
- *
- * PPC 440 core has following TLB attribute fields;
- *
- *   TLB1:
- *   0  1  2  3  4  ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
- *   RPN.................................  -  -  -  -  -  - ERPN.......
- *
- *   TLB2:
- *   0  1  2  3  4  ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
- *   -  -  -  -  -    - U0 U1 U2 U3 W  I  M  G  E   - UX UW UR SX SW SR
- *
- * There are some constrains and options, to decide mapping software bits
- * into TLB entry.
- *
- *   - PRESENT *must* be in the bottom three bits because swap cache
- *     entries use the top 29 bits for TLB2.
- *
- *   - FILE *must* be in the bottom three bits because swap cache
- *     entries use the top 29 bits for TLB2.
- *
- *   - CACHE COHERENT bit (M) has no effect on PPC440 core, because it
- *     doesn't support SMP. So we can use this as software bit, like
- *     DIRTY.
- *
- * With the PPC 44x Linux implementation, the 0-11th LSBs of the PTE are used
- * for memory protection related functions (see PTE structure in
- * include/asm-ppc/mmu.h).  The _PAGE_XXX definitions in this file map to the
- * above bits.  Note that the bit values are CPU specific, not architecture
- * specific.
- *
- * The kernel PTE entry holds an arch-dependent swp_entry structure under
- * certain situations. In other words, in such situations some portion of
- * the PTE bits are used as a swp_entry. In the PPC implementation, the
- * 3-24th LSB are shared with swp_entry, however the 0-2nd three LSB still
- * hold protection values. That means the three protection bits are
- * reserved for both PTE and SWAP entry at the most significant three
- * LSBs.
- *
- * There are three protection bits available for SWAP entry:
- *	_PAGE_PRESENT
- *	_PAGE_FILE
- *	_PAGE_HASHPTE (if HW has)
- *
- * So those three bits have to be inside of 0-2nd LSB of PTE.
- *
- */
-
-#define _PAGE_PRESENT	0x00000001		/* S: PTE valid */
-#define	_PAGE_RW	0x00000002		/* S: Write permission */
-#define _PAGE_FILE	0x00000004		/* S: nonlinear file mapping */
-#define _PAGE_ACCESSED	0x00000008		/* S: Page referenced */
-#define _PAGE_HWWRITE	0x00000010		/* H: Dirty & RW */
-#define _PAGE_HWEXEC	0x00000020		/* H: Execute permission */
-#define	_PAGE_USER	0x00000040		/* S: User page */
-#define	_PAGE_ENDIAN	0x00000080		/* H: E bit */
-#define	_PAGE_GUARDED	0x00000100		/* H: G bit */
-#define	_PAGE_DIRTY	0x00000200		/* S: Page dirty */
-#define	_PAGE_NO_CACHE	0x00000400		/* H: I bit */
-#define	_PAGE_WRITETHRU	0x00000800		/* H: W bit */
-
-/* TODO: Add large page lowmem mapping support */
-#define _PMD_PRESENT	0
-#define _PMD_PRESENT_MASK (PAGE_MASK)
-#define _PMD_BAD	(~PAGE_MASK)
-
-/* ERPN in a PTE never gets cleared, ignore it */
-#define _PTE_NONE_MASK	0xffffffff00000000ULL
-
-#elif defined(CONFIG_8xx)
-/* Definitions for 8xx embedded chips. */
-#define _PAGE_PRESENT	0x0001	/* Page is valid */
-#define _PAGE_FILE	0x0002	/* when !present: nonlinear file mapping */
-#define _PAGE_NO_CACHE	0x0002	/* I: cache inhibit */
-#define _PAGE_SHARED	0x0004	/* No ASID (context) compare */
-
-/* These five software bits must be masked out when the entry is loaded
- * into the TLB.
- */
-#define _PAGE_EXEC	0x0008	/* software: i-cache coherency required */
-#define _PAGE_GUARDED	0x0010	/* software: guarded access */
-#define _PAGE_DIRTY	0x0020	/* software: page changed */
-#define _PAGE_RW	0x0040	/* software: user write access allowed */
-#define _PAGE_ACCESSED	0x0080	/* software: page referenced */
-
-/* Setting any bits in the nibble with the follow two controls will
- * require a TLB exception handler change.  It is assumed unused bits
- * are always zero.
- */
-#define _PAGE_HWWRITE	0x0100	/* h/w write enable: never set in Linux PTE */
-#define _PAGE_USER	0x0800	/* One of the PP bits, the other is USER&~RW */
-
-#define _PMD_PRESENT	0x0001
-#define _PMD_BAD	0x0ff0
-#define _PMD_PAGE_MASK	0x000c
-#define _PMD_PAGE_8M	0x000c
-
-#define _PTE_NONE_MASK _PAGE_ACCESSED
-
-#else /* CONFIG_6xx */
-/* Definitions for 60x, 740/750, etc. */
-#define _PAGE_PRESENT	0x001	/* software: pte contains a translation */
-#define _PAGE_HASHPTE	0x002	/* hash_page has made an HPTE for this pte */
-#define _PAGE_FILE	0x004	/* when !present: nonlinear file mapping */
-#define _PAGE_USER	0x004	/* usermode access allowed */
-#define _PAGE_GUARDED	0x008	/* G: prohibit speculative access */
-#define _PAGE_COHERENT	0x010	/* M: enforce memory coherence (SMP systems) */
-#define _PAGE_NO_CACHE	0x020	/* I: cache inhibit */
-#define _PAGE_WRITETHRU	0x040	/* W: cache write-through */
-#define _PAGE_DIRTY	0x080	/* C: page changed */
-#define _PAGE_ACCESSED	0x100	/* R: page referenced */
-#define _PAGE_EXEC	0x200	/* software: i-cache coherency required */
-#define _PAGE_RW	0x400	/* software: user write access allowed */
-
-#define _PTE_NONE_MASK	_PAGE_HASHPTE
-
-#define _PMD_PRESENT	0
-#define _PMD_PRESENT_MASK (PAGE_MASK)
-#define _PMD_BAD	(~PAGE_MASK)
-#endif
-
-/*
- * Some bits are only used on some cpu families...
- */
-#ifndef _PAGE_HASHPTE
-#define _PAGE_HASHPTE	0
-#endif
-#ifndef _PTE_NONE_MASK
-#define _PTE_NONE_MASK 0
-#endif
-#ifndef _PAGE_SHARED
-#define _PAGE_SHARED	0
-#endif
-#ifndef _PAGE_HWWRITE
-#define _PAGE_HWWRITE	0
-#endif
-#ifndef _PAGE_HWEXEC
-#define _PAGE_HWEXEC	0
-#endif
-#ifndef _PAGE_EXEC
-#define _PAGE_EXEC	0
-#endif
-#ifndef _PMD_PRESENT_MASK
-#define _PMD_PRESENT_MASK	_PMD_PRESENT
-#endif
-#ifndef _PMD_SIZE
-#define _PMD_SIZE	0
-#define PMD_PAGE_SIZE(pmd)	bad_call_to_PMD_PAGE_SIZE()
-#endif
-
-#define _PAGE_CHG_MASK	(PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
-
-/*
- * Note: the _PAGE_COHERENT bit automatically gets set in the hardware
- * PTE if CONFIG_SMP is defined (hash_page does this); there is no need
- * to have it in the Linux PTE, and in fact the bit could be reused for
- * another purpose.  -- paulus.
- */
-
-#ifdef CONFIG_44x
-#define _PAGE_BASE	(_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_GUARDED)
-#else
-#define _PAGE_BASE	(_PAGE_PRESENT | _PAGE_ACCESSED)
-#endif
-#define _PAGE_WRENABLE	(_PAGE_RW | _PAGE_DIRTY | _PAGE_HWWRITE)
-#define _PAGE_KERNEL	(_PAGE_BASE | _PAGE_SHARED | _PAGE_WRENABLE)
-
-#ifdef CONFIG_PPC_STD_MMU
-/* On standard PPC MMU, no user access implies kernel read/write access,
- * so to write-protect kernel memory we must turn on user access */
-#define _PAGE_KERNEL_RO	(_PAGE_BASE | _PAGE_SHARED | _PAGE_USER)
-#else
-#define _PAGE_KERNEL_RO	(_PAGE_BASE | _PAGE_SHARED)
-#endif
-
-#define _PAGE_IO	(_PAGE_KERNEL | _PAGE_NO_CACHE | _PAGE_GUARDED)
-#define _PAGE_RAM	(_PAGE_KERNEL | _PAGE_HWEXEC)
-
-#if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH)
-/* We want the debuggers to be able to set breakpoints anywhere, so
- * don't write protect the kernel text */
-#define _PAGE_RAM_TEXT	_PAGE_RAM
-#else
-#define _PAGE_RAM_TEXT	(_PAGE_KERNEL_RO | _PAGE_HWEXEC)
-#endif
-
-#define PAGE_NONE	__pgprot(_PAGE_BASE)
-#define PAGE_READONLY	__pgprot(_PAGE_BASE | _PAGE_USER)
-#define PAGE_READONLY_X	__pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
-#define PAGE_SHARED	__pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW)
-#define PAGE_SHARED_X	__pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW | _PAGE_EXEC)
-#define PAGE_COPY	__pgprot(_PAGE_BASE | _PAGE_USER)
-#define PAGE_COPY_X	__pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
-
-#define PAGE_KERNEL		__pgprot(_PAGE_RAM)
-#define PAGE_KERNEL_NOCACHE	__pgprot(_PAGE_IO)
-
-/*
- * The PowerPC can only do execute protection on a segment (256MB) basis,
- * not on a page basis.  So we consider execute permission the same as read.
- * Also, write permissions imply read permissions.
- * This is the closest we can get..
- */
-#define __P000	PAGE_NONE
-#define __P001	PAGE_READONLY_X
-#define __P010	PAGE_COPY
-#define __P011	PAGE_COPY_X
-#define __P100	PAGE_READONLY
-#define __P101	PAGE_READONLY_X
-#define __P110	PAGE_COPY
-#define __P111	PAGE_COPY_X
-
-#define __S000	PAGE_NONE
-#define __S001	PAGE_READONLY_X
-#define __S010	PAGE_SHARED
-#define __S011	PAGE_SHARED_X
-#define __S100	PAGE_READONLY
-#define __S101	PAGE_READONLY_X
-#define __S110	PAGE_SHARED
-#define __S111	PAGE_SHARED_X
-
-#ifndef __ASSEMBLY__
-/* Make sure we get a link error if PMD_PAGE_SIZE is ever called on a
- * kernel without large page PMD support */
-extern unsigned long bad_call_to_PMD_PAGE_SIZE(void);
-
-/*
- * Conversions between PTE values and page frame numbers.
- */
-
-/* in some case we want to additionaly adjust where the pfn is in the pte to
- * allow room for more flags */
-#define PFN_SHIFT_OFFSET	(PAGE_SHIFT)
-
-#define pte_pfn(x)		(pte_val(x) >> PFN_SHIFT_OFFSET)
-#define pte_page(x)		pfn_to_page(pte_pfn(x))
-
-#define pfn_pte(pfn, prot)	__pte(((pte_basic_t)(pfn) << PFN_SHIFT_OFFSET) |\
-					pgprot_val(prot))
-#define mk_pte(page, prot)	pfn_pte(page_to_pfn(page), prot)
-
-/*
- * ZERO_PAGE is a global shared page that is always zero: used
- * for zero-mapped memory areas etc..
- */
-extern unsigned long empty_zero_page[1024];
-#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
-
-#endif /* __ASSEMBLY__ */
-
-#define pte_none(pte)		((pte_val(pte) & ~_PTE_NONE_MASK) == 0)
-#define pte_present(pte)	(pte_val(pte) & _PAGE_PRESENT)
-#define pte_clear(mm,addr,ptep)	do { set_pte_at((mm), (addr), (ptep), __pte(0)); } while (0)
-
-#define pmd_none(pmd)		(!pmd_val(pmd))
-#define	pmd_bad(pmd)		(pmd_val(pmd) & _PMD_BAD)
-#define	pmd_present(pmd)	(pmd_val(pmd) & _PMD_PRESENT_MASK)
-#define	pmd_clear(pmdp)		do { pmd_val(*(pmdp)) = 0; } while (0)
-
-#ifndef __ASSEMBLY__
-/*
- * The "pgd_xxx()" functions here are trivial for a folded two-level
- * setup: the pgd is never bad, and a pmd always exists (as it's folded
- * into the pgd entry)
- */
-static inline int pgd_none(pgd_t pgd)		{ return 0; }
-static inline int pgd_bad(pgd_t pgd)		{ return 0; }
-static inline int pgd_present(pgd_t pgd)	{ return 1; }
-#define pgd_clear(xp)				do { } while (0)
-
-#define pgd_page_vaddr(pgd) \
-	((unsigned long) __va(pgd_val(pgd) & PAGE_MASK))
-
-/*
- * The following only work if pte_present() is true.
- * Undefined behaviour if not..
- */
-static inline int pte_write(pte_t pte)		{ return pte_val(pte) & _PAGE_RW; }
-static inline int pte_dirty(pte_t pte)		{ return pte_val(pte) & _PAGE_DIRTY; }
-static inline int pte_young(pte_t pte)		{ return pte_val(pte) & _PAGE_ACCESSED; }
-static inline int pte_file(pte_t pte)		{ return pte_val(pte) & _PAGE_FILE; }
-static inline int pte_special(pte_t pte)	{ return 0; }
-
-static inline void pte_uncache(pte_t pte)       { pte_val(pte) |= _PAGE_NO_CACHE; }
-static inline void pte_cache(pte_t pte)         { pte_val(pte) &= ~_PAGE_NO_CACHE; }
-
-static inline pte_t pte_wrprotect(pte_t pte) {
-	pte_val(pte) &= ~(_PAGE_RW | _PAGE_HWWRITE); return pte; }
-static inline pte_t pte_mkclean(pte_t pte) {
-	pte_val(pte) &= ~(_PAGE_DIRTY | _PAGE_HWWRITE); return pte; }
-static inline pte_t pte_mkold(pte_t pte) {
-	pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
-
-static inline pte_t pte_mkwrite(pte_t pte) {
-	pte_val(pte) |= _PAGE_RW; return pte; }
-static inline pte_t pte_mkdirty(pte_t pte) {
-	pte_val(pte) |= _PAGE_DIRTY; return pte; }
-static inline pte_t pte_mkyoung(pte_t pte) {
-	pte_val(pte) |= _PAGE_ACCESSED; return pte; }
-static inline pte_t pte_mkspecial(pte_t pte) {
-	return pte; }
-
-static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
-{
-	pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot);
-	return pte;
-}
-
-/*
- * When flushing the tlb entry for a page, we also need to flush the hash
- * table entry.  flush_hash_pages is assembler (for speed) in hashtable.S.
- */
-extern int flush_hash_pages(unsigned context, unsigned long va,
-			    unsigned long pmdval, int count);
-
-/* Add an HPTE to the hash table */
-extern void add_hash_page(unsigned context, unsigned long va,
-			  unsigned long pmdval);
-
-/*
- * Atomic PTE updates.
- *
- * pte_update clears and sets bit atomically, and returns
- * the old pte value.  In the 64-bit PTE case we lock around the
- * low PTE word since we expect ALL flag bits to be there
- */
-#ifndef CONFIG_PTE_64BIT
-static inline unsigned long pte_update(pte_t *p, unsigned long clr,
-				       unsigned long set)
-{
-	unsigned long old, tmp;
-
-	__asm__ __volatile__("\
-1:	lwarx	%0,0,%3\n\
-	andc	%1,%0,%4\n\
-	or	%1,%1,%5\n"
-	PPC405_ERR77(0,%3)
-"	stwcx.	%1,0,%3\n\
-	bne-	1b"
-	: "=&r" (old), "=&r" (tmp), "=m" (*p)
-	: "r" (p), "r" (clr), "r" (set), "m" (*p)
-	: "cc" );
-	return old;
-}
-#else
-static inline unsigned long long pte_update(pte_t *p, unsigned long clr,
-				       unsigned long set)
-{
-	unsigned long long old;
-	unsigned long tmp;
-
-	__asm__ __volatile__("\
-1:	lwarx	%L0,0,%4\n\
-	lwzx	%0,0,%3\n\
-	andc	%1,%L0,%5\n\
-	or	%1,%1,%6\n"
-	PPC405_ERR77(0,%3)
-"	stwcx.	%1,0,%4\n\
-	bne-	1b"
-	: "=&r" (old), "=&r" (tmp), "=m" (*p)
-	: "r" (p), "r" ((unsigned long)(p) + 4), "r" (clr), "r" (set), "m" (*p)
-	: "cc" );
-	return old;
-}
-#endif
-
-/*
- * set_pte stores a linux PTE into the linux page table.
- * On machines which use an MMU hash table we avoid changing the
- * _PAGE_HASHPTE bit.
- */
-static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
-			      pte_t *ptep, pte_t pte)
-{
-#if _PAGE_HASHPTE != 0
-	pte_update(ptep, ~_PAGE_HASHPTE, pte_val(pte) & ~_PAGE_HASHPTE);
-#else
-	*ptep = pte;
-#endif
-}
-
-/*
- * 2.6 calles this without flushing the TLB entry, this is wrong
- * for our hash-based implementation, we fix that up here
- */
-#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
-static inline int __ptep_test_and_clear_young(unsigned int context, unsigned long addr, pte_t *ptep)
-{
-	unsigned long old;
-	old = pte_update(ptep, _PAGE_ACCESSED, 0);
-#if _PAGE_HASHPTE != 0
-	if (old & _PAGE_HASHPTE) {
-		unsigned long ptephys = __pa(ptep) & PAGE_MASK;
-		flush_hash_pages(context, addr, ptephys, 1);
-	}
-#endif
-	return (old & _PAGE_ACCESSED) != 0;
-}
-#define ptep_test_and_clear_young(__vma, __addr, __ptep) \
-	__ptep_test_and_clear_young((__vma)->vm_mm->context.id, __addr, __ptep)
-
-#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
-static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr,
-				       pte_t *ptep)
-{
-	return __pte(pte_update(ptep, ~_PAGE_HASHPTE, 0));
-}
-
-#define __HAVE_ARCH_PTEP_SET_WRPROTECT
-static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
-				      pte_t *ptep)
-{
-	pte_update(ptep, (_PAGE_RW | _PAGE_HWWRITE), 0);
-}
-
-#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
-static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry, int dirty)
-{
-	unsigned long bits = pte_val(entry) &
-		(_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW);
-	pte_update(ptep, 0, bits);
-}
-
-#define  ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
-({									   \
-	int __changed = !pte_same(*(__ptep), __entry);			   \
-	if (__changed) {						   \
-		__ptep_set_access_flags(__ptep, __entry, __dirty);    	   \
-		flush_tlb_page_nohash(__vma, __address);		   \
-	}								   \
-	__changed;							   \
-})
-
-/*
- * Macro to mark a page protection value as "uncacheable".
- */
-#define pgprot_noncached(prot)	(__pgprot(pgprot_val(prot) | _PAGE_NO_CACHE | _PAGE_GUARDED))
-
-struct file;
-extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
-				     unsigned long size, pgprot_t vma_prot);
-#define __HAVE_PHYS_MEM_ACCESS_PROT
-
-#define __HAVE_ARCH_PTE_SAME
-#define pte_same(A,B)	(((pte_val(A) ^ pte_val(B)) & ~_PAGE_HASHPTE) == 0)
-
-/*
- * Note that on Book E processors, the pmd contains the kernel virtual
- * (lowmem) address of the pte page.  The physical address is less useful
- * because everything runs with translation enabled (even the TLB miss
- * handler).  On everything else the pmd contains the physical address
- * of the pte page.  -- paulus
- */
-#ifndef CONFIG_BOOKE
-#define pmd_page_vaddr(pmd)	\
-	((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
-#define pmd_page(pmd)		\
-	(mem_map + (pmd_val(pmd) >> PAGE_SHIFT))
-#else
-#define pmd_page_vaddr(pmd)	\
-	((unsigned long) (pmd_val(pmd) & PAGE_MASK))
-#define pmd_page(pmd)		\
-	(mem_map + (__pa(pmd_val(pmd)) >> PAGE_SHIFT))
-#endif
-
-/* to find an entry in a kernel page-table-directory */
-#define pgd_offset_k(address) pgd_offset(&init_mm, address)
-
-/* to find an entry in a page-table-directory */
-#define pgd_index(address)	 ((address) >> PGDIR_SHIFT)
-#define pgd_offset(mm, address)	 ((mm)->pgd + pgd_index(address))
-
-/* Find an entry in the second-level page table.. */
-static inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address)
-{
-	return (pmd_t *) dir;
-}
-
-/* Find an entry in the third-level page table.. */
-#define pte_index(address)		\
-	(((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
-#define pte_offset_kernel(dir, addr)	\
-	((pte_t *) pmd_page_vaddr(*(dir)) + pte_index(addr))
-#define pte_offset_map(dir, addr)		\
-	((pte_t *) kmap_atomic(pmd_page(*(dir)), KM_PTE0) + pte_index(addr))
-#define pte_offset_map_nested(dir, addr)	\
-	((pte_t *) kmap_atomic(pmd_page(*(dir)), KM_PTE1) + pte_index(addr))
-
-#define pte_unmap(pte)		kunmap_atomic(pte, KM_PTE0)
-#define pte_unmap_nested(pte)	kunmap_atomic(pte, KM_PTE1)
-
-extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
-
-extern void paging_init(void);
-
-/*
- * Encode and decode a swap entry.
- * Note that the bits we use in a PTE for representing a swap entry
- * must not include the _PAGE_PRESENT bit, the _PAGE_FILE bit, or the
- *_PAGE_HASHPTE bit (if used).  -- paulus
- */
-#define __swp_type(entry)		((entry).val & 0x1f)
-#define __swp_offset(entry)		((entry).val >> 5)
-#define __swp_entry(type, offset)	((swp_entry_t) { (type) | ((offset) << 5) })
-#define __pte_to_swp_entry(pte)		((swp_entry_t) { pte_val(pte) >> 3 })
-#define __swp_entry_to_pte(x)		((pte_t) { (x).val << 3 })
-
-/* Encode and decode a nonlinear file mapping entry */
-#define PTE_FILE_MAX_BITS	29
-#define pte_to_pgoff(pte)	(pte_val(pte) >> 3)
-#define pgoff_to_pte(off)	((pte_t) { ((off) << 3) | _PAGE_FILE })
-
-/* Values for nocacheflag and cmode */
-/* These are not used by the APUS kernel_map, but prevents
-   compilation errors. */
-#define	KERNELMAP_FULL_CACHING		0
-#define	KERNELMAP_NOCACHE_SER		1
-#define	KERNELMAP_NOCACHE_NONSER	2
-#define	KERNELMAP_NO_COPYBACK		3
-
-/*
- * Map some physical address range into the kernel address space.
- */
-extern unsigned long kernel_map(unsigned long paddr, unsigned long size,
-				int nocacheflag, unsigned long *memavailp );
-
-/*
- * Set cache mode of (kernel space) address range.
- */
-extern void kernel_set_cachemode (unsigned long address, unsigned long size,
-                                 unsigned int cmode);
-
-/* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
-#define kern_addr_valid(addr)	(1)
-
-#ifdef CONFIG_PHYS_64BIT
-extern int remap_pfn_range(struct vm_area_struct *vma, unsigned long from,
-			unsigned long paddr, unsigned long size, pgprot_t prot);
-
-static inline int io_remap_pfn_range(struct vm_area_struct *vma,
-					unsigned long vaddr,
-					unsigned long pfn,
-					unsigned long size,
-					pgprot_t prot)
-{
-	phys_addr_t paddr64 = fixup_bigphys_addr(pfn << PAGE_SHIFT, size);
-	return remap_pfn_range(vma, vaddr, paddr64 >> PAGE_SHIFT, size, prot);
-}
-#else
-#define io_remap_pfn_range(vma, vaddr, pfn, size, prot)		\
-		remap_pfn_range(vma, vaddr, pfn, size, prot)
-#endif
-
-/*
- * No page table caches to initialise
- */
-#define pgtable_cache_init()	do { } while (0)
-
-extern int get_pteptr(struct mm_struct *mm, unsigned long addr, pte_t **ptep,
-		      pmd_t **pmdp);
-
-#include <asm-generic/pgtable.h>
-
-#endif /* !__ASSEMBLY__ */
-
-#endif /* _PPC_PGTABLE_H */
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/pnp.h b/include/asm-ppc/pnp.h
deleted file mode 100644
index 6f6760b30dd..00000000000
--- a/include/asm-ppc/pnp.h
+++ /dev/null
@@ -1,645 +0,0 @@
-#ifdef __KERNEL__
-/* 11/02/95                                                                   */
-/*----------------------------------------------------------------------------*/
-/*      Plug and Play header definitions                                      */
-/*----------------------------------------------------------------------------*/
-
-/* Structure map for PnP on PowerPC Reference Platform                        */
-/* See Plug and Play ISA Specification, Version 1.0, May 28, 1993.  It        */
-/* (or later versions) is available on Compuserve in the PLUGPLAY area.       */
-/* This code has extensions to that specification, namely new short and       */
-/* long tag types for platform dependent information                          */
-
-/* Warning: LE notation used throughout this file                             */
-
-/* For enum's: if given in hex then they are bit significant, i.e.            */
-/* only one bit is on for each enum                                           */
-
-#ifndef _PNP_
-#define _PNP_
-
-#ifndef __ASSEMBLY__
-#define MAX_MEM_REGISTERS 9
-#define MAX_IO_PORTS 20
-#define MAX_IRQS 7
-/*#define MAX_DMA_CHANNELS 7*/
-
-/* Interrupt controllers */
-
-#define PNPinterrupt0 "PNP0000"      /* AT Interrupt Controller               */
-#define PNPinterrupt1 "PNP0001"      /* EISA Interrupt Controller             */
-#define PNPinterrupt2 "PNP0002"      /* MCA Interrupt Controller              */
-#define PNPinterrupt3 "PNP0003"      /* APIC                                  */
-#define PNPExtInt     "IBM000D"      /* PowerPC Extended Interrupt Controller */
-
-/* Timers */
-
-#define PNPtimer0     "PNP0100"      /* AT Timer                              */
-#define PNPtimer1     "PNP0101"      /* EISA Timer                            */
-#define PNPtimer2     "PNP0102"      /* MCA Timer                             */
-
-/* DMA controllers */
-
-#define PNPdma0       "PNP0200"      /* AT DMA Controller                     */
-#define PNPdma1       "PNP0201"      /* EISA DMA Controller                   */
-#define PNPdma2       "PNP0202"      /* MCA DMA Controller                    */
-
-/* start of August 15, 1994 additions */
-/* CMOS */
-#define PNPCMOS       "IBM0009"      /* CMOS                                  */
-
-/* L2 Cache */
-#define PNPL2         "IBM0007"      /* L2 Cache                              */
-
-/* NVRAM */
-#define PNPNVRAM      "IBM0008"      /* NVRAM                                 */
-
-/* Power Management */
-#define PNPPM         "IBM0005"      /* Power Management                      */
-/* end of August 15, 1994 additions */
-
-/* Keyboards */
-
-#define PNPkeyboard0  "PNP0300"      /* IBM PC/XT KB Cntlr (83 key, no mouse) */
-#define PNPkeyboard1  "PNP0301"      /* Olivetti ICO (102 key)                */
-#define PNPkeyboard2  "PNP0302"      /* IBM PC/AT KB Cntlr (84 key)           */
-#define PNPkeyboard3  "PNP0303"      /* IBM Enhanced (101/2 key, PS/2 mouse)  */
-#define PNPkeyboard4  "PNP0304"      /* Nokia 1050 KB Cntlr                   */
-#define PNPkeyboard5  "PNP0305"      /* Nokia 9140 KB Cntlr                   */
-#define PNPkeyboard6  "PNP0306"      /* Standard Japanese KB Cntlr            */
-#define PNPkeyboard7  "PNP0307"      /* Microsoft Windows (R) KB Cntlr        */
-
-/* Parallel port controllers */
-
-#define PNPparallel0 "PNP0400"       /* Standard LPT Parallel Port            */
-#define PNPparallel1 "PNP0401"       /* ECP Parallel Port                     */
-#define PNPepp       "IBM001C"       /* EPP Parallel Port                     */
-
-/* Serial port controllers */
-
-#define PNPserial0   "PNP0500"       /* Standard PC Serial port               */
-#define PNPSerial1   "PNP0501"       /* 16550A Compatible Serial port         */
-
-/* Disk controllers */
-
-#define PNPdisk0     "PNP0600"       /* Generic ESDI/IDE/ATA Compat HD Cntlr  */
-#define PNPdisk1     "PNP0601"       /* Plus Hardcard II                      */
-#define PNPdisk2     "PNP0602"       /* Plus Hardcard IIXL/EZ                 */
-
-/* Diskette controllers */
-
-#define PNPdiskette0 "PNP0700"       /* PC Standard Floppy Disk Controller    */
-
-/* Display controllers */
-
-#define PNPdisplay0  "PNP0900"       /* VGA Compatible                        */
-#define PNPdisplay1  "PNP0901"       /* Video Seven VGA                       */
-#define PNPdisplay2  "PNP0902"       /* 8514/A Compatible                     */
-#define PNPdisplay3  "PNP0903"       /* Trident VGA                           */
-#define PNPdisplay4  "PNP0904"       /* Cirrus Logic Laptop VGA               */
-#define PNPdisplay5  "PNP0905"       /* Cirrus Logic VGA                      */
-#define PNPdisplay6  "PNP0906"       /* Tseng ET4000 or ET4000/W32            */
-#define PNPdisplay7  "PNP0907"       /* Western Digital VGA                   */
-#define PNPdisplay8  "PNP0908"       /* Western Digital Laptop VGA            */
-#define PNPdisplay9  "PNP0909"       /* S3                                    */
-#define PNPdisplayA  "PNP090A"       /* ATI Ultra Pro/Plus (Mach 32)          */
-#define PNPdisplayB  "PNP090B"       /* ATI Ultra (Mach 8)                    */
-#define PNPdisplayC  "PNP090C"       /* XGA Compatible                        */
-#define PNPdisplayD  "PNP090D"       /* ATI VGA Wonder                        */
-#define PNPdisplayE  "PNP090E"       /* Weitek P9000 Graphics Adapter         */
-#define PNPdisplayF  "PNP090F"       /* Oak Technology VGA                    */
-
-/* Peripheral busses */
-
-#define PNPbuses0    "PNP0A00"       /* ISA Bus                               */
-#define PNPbuses1    "PNP0A01"       /* EISA Bus                              */
-#define PNPbuses2    "PNP0A02"       /* MCA Bus                               */
-#define PNPbuses3    "PNP0A03"       /* PCI Bus                               */
-#define PNPbuses4    "PNP0A04"       /* VESA/VL Bus                           */
-
-/* RTC, BIOS, planar devices */
-
-#define PNPspeaker0  "PNP0800"       /* AT Style Speaker Sound                */
-#define PNPrtc0      "PNP0B00"       /* AT RTC                                */
-#define PNPpnpbios0  "PNP0C00"       /* PNP BIOS (only created by root enum)  */
-#define PNPpnpbios1  "PNP0C01"       /* System Board Memory Device            */
-#define PNPpnpbios2  "PNP0C02"       /* Math Coprocessor                      */
-#define PNPpnpbios3  "PNP0C03"       /* PNP BIOS Event Notification Interrupt */
-
-/* PCMCIA controller */
-
-#define PNPpcmcia0   "PNP0E00"       /* Intel 82365 Compatible PCMCIA Cntlr   */
-
-/* Mice */
-
-#define PNPmouse0    "PNP0F00"       /* Microsoft Bus Mouse                   */
-#define PNPmouse1    "PNP0F01"       /* Microsoft Serial Mouse                */
-#define PNPmouse2    "PNP0F02"       /* Microsoft Inport Mouse                */
-#define PNPmouse3    "PNP0F03"       /* Microsoft PS/2 Mouse                  */
-#define PNPmouse4    "PNP0F04"       /* Mousesystems Mouse                    */
-#define PNPmouse5    "PNP0F05"       /* Mousesystems 3 Button Mouse - COM2    */
-#define PNPmouse6    "PNP0F06"       /* Genius Mouse - COM1                   */
-#define PNPmouse7    "PNP0F07"       /* Genius Mouse - COM2                   */
-#define PNPmouse8    "PNP0F08"       /* Logitech Serial Mouse                 */
-#define PNPmouse9    "PNP0F09"       /* Microsoft Ballpoint Serial Mouse      */
-#define PNPmouseA    "PNP0F0A"       /* Microsoft PNP Mouse                   */
-#define PNPmouseB    "PNP0F0B"       /* Microsoft PNP Ballpoint Mouse         */
-
-/* Modems */
-
-#define PNPmodem0    "PNP9000"       /* Specific IDs TBD                      */
-
-/* Network controllers */
-
-#define PNPnetworkC9 "PNP80C9"       /* IBM Token Ring                        */
-#define PNPnetworkCA "PNP80CA"       /* IBM Token Ring II                     */
-#define PNPnetworkCB "PNP80CB"       /* IBM Token Ring II/Short               */
-#define PNPnetworkCC "PNP80CC"       /* IBM Token Ring 4/16Mbs                */
-#define PNPnetwork27 "PNP8327"       /* IBM Token Ring (All types)            */
-#define PNPnetworket "IBM0010"       /* IBM Ethernet used by Power PC         */
-#define PNPneteisaet "IBM2001"       /* IBM Ethernet EISA adapter             */
-#define PNPAMD79C970 "IBM0016"       /* AMD 79C970 (PCI Ethernet)             */
-
-/* SCSI controllers */
-
-#define PNPscsi0     "PNPA000"       /* Adaptec 154x Compatible SCSI Cntlr    */
-#define PNPscsi1     "PNPA001"       /* Adaptec 174x Compatible SCSI Cntlr    */
-#define PNPscsi2     "PNPA002"       /* Future Domain 16-700 Compat SCSI Cntlr*/
-#define PNPscsi3     "PNPA003"       /* Panasonic CDROM Adapter (SBPro/SB16)  */
-#define PNPscsiF     "IBM000F"       /* NCR 810 SCSI Controller               */
-#define PNPscsi825   "IBM001B"       /* NCR 825 SCSI Controller               */
-#define PNPscsi875   "IBM0018"       /* NCR 875 SCSI Controller               */
-
-/* Sound/Video, Multimedia */
-
-#define PNPmm0       "PNPB000"       /* Sound Blaster Compatible Sound Device */
-#define PNPmm1       "PNPB001"       /* MS Windows Sound System Compat Device */
-#define PNPmmF       "IBM000E"       /* Crystal CS4231 Audio Device           */
-#define PNPv7310     "IBM0015"       /* ASCII V7310 Video Capture Device      */
-#define PNPmm4232    "IBM0017"       /* Crystal CS4232 Audio Device           */
-#define PNPpmsyn     "IBM001D"       /* YMF 289B chip (Yamaha)                */
-#define PNPgp4232    "IBM0012"       /* Crystal CS4232 Game Port              */
-#define PNPmidi4232  "IBM0013"       /* Crystal CS4232 MIDI                   */
-
-/* Operator Panel */
-#define PNPopctl     "IBM000B"       /* Operator's panel                      */
-
-/* Service Processor */
-#define PNPsp        "IBM0011"       /* IBM Service Processor                 */
-#define PNPLTsp      "IBM001E"       /* Lightning/Terlingua Support Processor */
-#define PNPLTmsp     "IBM001F"       /* Lightning/Terlingua Mini-SP           */
-
-/* Memory Controller */
-#define PNPmemctl    "IBM000A"       /* Memory controller                     */
-
-/* Graphics Assist */
-#define PNPg_assist  "IBM0014"       /* Graphics Assist                       */
-
-/* Miscellaneous Device Controllers */
-#define PNPtablet    "IBM0019"       /* IBM Tablet Controller                 */
-
-/* PNP Packet Handles */
-
-#define S1_Packet                0x0A   /* Version resource                   */
-#define S2_Packet                0x15   /* Logical DEVID (without flags)      */
-#define S2_Packet_flags          0x16   /* Logical DEVID (with flags)         */
-#define S3_Packet                0x1C   /* Compatible device ID               */
-#define S4_Packet                0x22   /* IRQ resource (without flags)       */
-#define S4_Packet_flags          0x23   /* IRQ resource (with flags)          */
-#define S5_Packet                0x2A   /* DMA resource                       */
-#define S6_Packet                0x30   /* Depend funct start (w/o priority)  */
-#define S6_Packet_priority       0x31   /* Depend funct start (w/ priority)   */
-#define S7_Packet                0x38   /* Depend funct end                   */
-#define S8_Packet                0x47   /* I/O port resource (w/o fixed loc)  */
-#define S9_Packet_fixed          0x4B   /* I/O port resource (w/ fixed loc)   */
-#define S14_Packet               0x71   /* Vendor defined                     */
-#define S15_Packet               0x78   /* End of resource (w/o checksum)     */
-#define S15_Packet_checksum      0x79   /* End of resource (w/ checksum)      */
-#define L1_Packet                0x81   /* Memory range                       */
-#define L1_Shadow                0x20   /* Memory is shadowable               */
-#define L1_32bit_mem             0x18   /* 32-bit memory only                 */
-#define L1_8_16bit_mem           0x10   /* 8- and 16-bit supported            */
-#define L1_Decode_Hi             0x04   /* decode supports high address       */
-#define L1_Cache                 0x02   /* read cacheable, write-through      */
-#define L1_Writeable             0x01   /* Memory is writeable                */
-#define L2_Packet                0x82   /* ANSI ID string                     */
-#define L3_Packet                0x83   /* Unicode ID string                  */
-#define L4_Packet                0x84   /* Vendor defined                     */
-#define L5_Packet                0x85   /* Large I/O                          */
-#define L6_Packet                0x86   /* 32-bit Fixed Loc Mem Range Desc    */
-#define END_TAG                  0x78   /* End of resource                    */
-#define DF_START_TAG             0x30   /* Dependent function start           */
-#define DF_START_TAG_priority    0x31   /* Dependent function start           */
-#define DF_END_TAG               0x38   /* Dependent function end             */
-#define SUBOPTIMAL_CONFIGURATION 0x2    /* Priority byte sub optimal config   */
-
-/* Device Base Type Codes */
-
-typedef enum _PnP_BASE_TYPE {
-  Reserved = 0,
-  MassStorageDevice = 1,
-  NetworkInterfaceController = 2,
-  DisplayController = 3,
-  MultimediaController = 4,
-  MemoryController = 5,
-  BridgeController = 6,
-  CommunicationsDevice = 7,
-  SystemPeripheral = 8,
-  InputDevice = 9,
-  ServiceProcessor = 0x0A,              /* 11/2/95                            */
-  } PnP_BASE_TYPE;
-
-/* Device Sub Type Codes */
-
-typedef enum _PnP_SUB_TYPE {
-  SCSIController = 0,
-  IDEController = 1,
-  FloppyController = 2,
-  IPIController = 3,
-  OtherMassStorageController = 0x80,
-
-  EthernetController = 0,
-  TokenRingController = 1,
-  FDDIController = 2,
-  OtherNetworkController = 0x80,
-
-  VGAController= 0,
-  SVGAController= 1,
-  XGAController= 2,
-  OtherDisplayController = 0x80,
-
-  VideoController = 0,
-  AudioController = 1,
-  OtherMultimediaController = 0x80,
-
-  RAM = 0,
-  FLASH = 1,
-  OtherMemoryDevice = 0x80,
-
-  HostProcessorBridge = 0,
-  ISABridge = 1,
-  EISABridge = 2,
-  MicroChannelBridge = 3,
-  PCIBridge = 4,
-  PCMCIABridge = 5,
-  VMEBridge = 6,
-  OtherBridgeDevice = 0x80,
-
-  RS232Device = 0,
-  ATCompatibleParallelPort = 1,
-  OtherCommunicationsDevice = 0x80,
-
-  ProgrammableInterruptController = 0,
-  DMAController = 1,
-  SystemTimer = 2,
-  RealTimeClock = 3,
-  L2Cache = 4,
-  NVRAM = 5,
-  PowerManagement = 6,
-  CMOS = 7,
-  OperatorPanel = 8,
-  ServiceProcessorClass1 = 9,
-  ServiceProcessorClass2 = 0xA,
-  ServiceProcessorClass3 = 0xB,
-  GraphicAssist = 0xC,
-  SystemPlanar = 0xF,                   /* 10/5/95                            */
-  OtherSystemPeripheral = 0x80,
-
-  KeyboardController = 0,
-  Digitizer = 1,
-  MouseController = 2,
-  TabletController = 3,                 /* 10/27/95                           */
-  OtherInputController = 0x80,
-
-  GeneralMemoryController = 0,
-  } PnP_SUB_TYPE;
-
-/* Device Interface Type Codes */
-
-typedef enum _PnP_INTERFACE {
-  General = 0,
-  GeneralSCSI = 0,
-  GeneralIDE = 0,
-  ATACompatible = 1,
-
-  GeneralFloppy = 0,
-  Compatible765 = 1,
-  NS398_Floppy = 2,                     /* NS Super I/O wired to use index
-                                           register at port 398 and data
-                                           register at port 399               */
-  NS26E_Floppy = 3,                     /* Ports 26E and 26F                  */
-  NS15C_Floppy = 4,                     /* Ports 15C and 15D                  */
-  NS2E_Floppy = 5,                      /* Ports 2E and 2F                    */
-  CHRP_Floppy = 6,                      /* CHRP Floppy in PR*P system         */
-
-  GeneralIPI = 0,
-
-  GeneralEther = 0,
-  GeneralToken = 0,
-  GeneralFDDI = 0,
-
-  GeneralVGA = 0,
-  GeneralSVGA = 0,
-  GeneralXGA = 0,
-
-  GeneralVideo = 0,
-  GeneralAudio = 0,
-  CS4232Audio = 1,                      /* CS 4232 Plug 'n Play Configured    */
-
-  GeneralRAM = 0,
-  GeneralFLASH = 0,
-  PCIMemoryController = 0,              /* PCI Config Method                  */
-  RS6KMemoryController = 1,             /* RS6K Config Method                 */
-
-  GeneralHostBridge = 0,
-  GeneralISABridge = 0,
-  GeneralEISABridge = 0,
-  GeneralMCABridge = 0,
-  GeneralPCIBridge = 0,
-  PCIBridgeDirect = 0,
-  PCIBridgeIndirect = 1,
-  PCIBridgeRS6K = 2,
-  GeneralPCMCIABridge = 0,
-  GeneralVMEBridge = 0,
-
-  GeneralRS232 = 0,
-  COMx = 1,
-  Compatible16450 = 2,
-  Compatible16550 = 3,
-  NS398SerPort = 4,                     /* NS Super I/O wired to use index
-                                           register at port 398 and data
-                                           register at port 399               */
-  NS26ESerPort = 5,                     /* Ports 26E and 26F                  */
-  NS15CSerPort = 6,                     /* Ports 15C and 15D                  */
-  NS2ESerPort = 7,                      /* Ports 2E and 2F                    */
-
-  GeneralParPort = 0,
-  LPTx = 1,
-  NS398ParPort = 2,                     /* NS Super I/O wired to use index
-                                           register at port 398 and data
-                                           register at port 399               */
-  NS26EParPort = 3,                     /* Ports 26E and 26F                  */
-  NS15CParPort = 4,                     /* Ports 15C and 15D                  */
-  NS2EParPort = 5,                      /* Ports 2E and 2F                    */
-
-  GeneralPIC = 0,
-  ISA_PIC = 1,
-  EISA_PIC = 2,
-  MPIC = 3,
-  RS6K_PIC = 4,
-
-  GeneralDMA = 0,
-  ISA_DMA = 1,
-  EISA_DMA = 2,
-
-  GeneralTimer = 0,
-  ISA_Timer = 1,
-  EISA_Timer = 2,
-  GeneralRTC = 0,
-  ISA_RTC = 1,
-
-  StoreThruOnly = 1,
-  StoreInEnabled = 2,
-  RS6KL2Cache = 3,
-
-  IndirectNVRAM = 0,                    /* Indirectly addressed               */
-  DirectNVRAM = 1,                      /* Memory Mapped                      */
-  IndirectNVRAM24 = 2,                  /* Indirectly addressed - 24 bit      */
-
-  GeneralPowerManagement = 0,
-  EPOWPowerManagement = 1,
-  PowerControl = 2,                    // d1378
-
-  GeneralCMOS = 0,
-
-  GeneralOPPanel = 0,
-  HarddiskLight = 1,
-  CDROMLight = 2,
-  PowerLight = 3,
-  KeyLock = 4,
-  ANDisplay = 5,                        /* AlphaNumeric Display               */
-  SystemStatusLED = 6,                  /* 3 digit 7 segment LED              */
-  CHRP_SystemStatusLED = 7,             /* CHRP LEDs in PR*P system           */
-
-  GeneralServiceProcessor = 0,
-
-  TransferData = 1,
-  IGMC32 = 2,
-  IGMC64 = 3,
-
-  GeneralSystemPlanar = 0,              /* 10/5/95                            */
-
-  } PnP_INTERFACE;
-
-/* PnP resources */
-
-/* Compressed ASCII is 5 bits per char; 00001=A ... 11010=Z */
-
-typedef struct _SERIAL_ID {
-  unsigned char VendorID0;              /*    Bit(7)=0                        */
-                                        /*    Bits(6:2)=1st character in      */
-                                        /*       compressed ASCII             */
-                                        /*    Bits(1:0)=2nd character in      */
-                                        /*       compressed ASCII bits(4:3)   */
-  unsigned char VendorID1;              /*    Bits(7:5)=2nd character in      */
-                                        /*       compressed ASCII bits(2:0)   */
-                                        /*    Bits(4:0)=3rd character in      */
-                                        /*       compressed ASCII             */
-  unsigned char VendorID2;              /* Product number - vendor assigned   */
-  unsigned char VendorID3;              /* Product number - vendor assigned   */
-
-/* Serial number is to provide uniqueness if more than one board of same      */
-/* type is in system.  Must be "FFFFFFFF" if feature not supported.           */
-
-  unsigned char Serial0;                /* Unique serial number bits (7:0)    */
-  unsigned char Serial1;                /* Unique serial number bits (15:8)   */
-  unsigned char Serial2;                /* Unique serial number bits (23:16)  */
-  unsigned char Serial3;                /* Unique serial number bits (31:24)  */
-  unsigned char Checksum;
-  } SERIAL_ID;
-
-typedef enum _PnPItemName {
-  Unused = 0,
-  PnPVersion = 1,
-  LogicalDevice = 2,
-  CompatibleDevice = 3,
-  IRQFormat = 4,
-  DMAFormat = 5,
-  StartDepFunc = 6,
-  EndDepFunc = 7,
-  IOPort = 8,
-  FixedIOPort = 9,
-  Res1 = 10,
-  Res2 = 11,
-  Res3 = 12,
-  SmallVendorItem = 14,
-  EndTag = 15,
-  MemoryRange = 1,
-  ANSIIdentifier = 2,
-  UnicodeIdentifier = 3,
-  LargeVendorItem = 4,
-  MemoryRange32 = 5,
-  MemoryRangeFixed32 = 6,
-  } PnPItemName;
-
-/* Define a bunch of access functions for the bits in the tag field */
-
-/* Tag type - 0 = small; 1 = large */
-#define tag_type(t) (((t) & 0x80)>>7)
-#define set_tag_type(t,v) (t = (t & 0x7f) | ((v)<<7))
-
-/* Small item name is 4 bits - one of PnPItemName enum above */
-#define tag_small_item_name(t) (((t) & 0x78)>>3)
-#define set_tag_small_item_name(t,v) (t = (t & 0x07) | ((v)<<3))
-
-/* Small item count is 3 bits - count of further bytes in packet */
-#define tag_small_count(t) ((t) & 0x07)
-#define set_tag_count(t,v) (t = (t & 0x78) | (v))
-
-/* Large item name is 7 bits - one of PnPItemName enum above */
-#define tag_large_item_name(t) ((t) & 0x7f)
-#define set_tag_large_item_name(t,v) (t = (t | 0x80) | (v))
-
-/* a PnP resource is a bunch of contiguous TAG packets ending with an end tag */
-
-typedef union _PnP_TAG_PACKET {
-  struct _S1_Pack{                      /* VERSION PACKET                     */
-    unsigned char Tag;                  /* small tag = 0x0a                   */
-    unsigned char Version[2];           /* PnP version, Vendor version        */
-    } S1_Pack;
-
-  struct _S2_Pack{                      /* LOGICAL DEVICE ID PACKET           */
-    unsigned char Tag;                  /* small tag = 0x15 or 0x16           */
-    unsigned char DevId[4];             /* Logical device id                  */
-    unsigned char Flags[2];             /* bit(0) boot device;                */
-                                        /* bit(7:1) cmd in range x31-x37      */
-                                        /* bit(7:0) cmd in range x28-x3f (opt)*/
-    } S2_Pack;
-
-  struct _S3_Pack{                      /* COMPATIBLE DEVICE ID PACKET        */
-    unsigned char Tag;                  /* small tag = 0x1c                   */
-    unsigned char CompatId[4];          /* Compatible device id               */
-    } S3_Pack;
-
-  struct _S4_Pack{                      /* IRQ PACKET                         */
-    unsigned char Tag;                  /* small tag = 0x22 or 0x23           */
-    unsigned char IRQMask[2];           /* bit(0) is IRQ0, ...;               */
-                                        /* bit(0) is IRQ8 ...                 */
-    unsigned char IRQInfo;              /* optional; assume bit(0)=1; else    */
-                                        /*  bit(0) - high true edge sensitive */
-                                        /*  bit(1) - low true edge sensitive  */
-                                        /*  bit(2) - high true level sensitive*/
-                                        /*  bit(3) - low true level sensitive */
-                                        /*  bit(7:4) - must be 0              */
-    } S4_Pack;
-
-  struct _S5_Pack{                      /* DMA PACKET                         */
-    unsigned char Tag;                  /* small tag = 0x2a                   */
-    unsigned char DMAMask;              /* bit(0) is channel 0 ...            */
-    unsigned char DMAInfo;
-    } S5_Pack;
-
-  struct _S6_Pack{                      /* START DEPENDENT FUNCTION PACKET    */
-    unsigned char Tag;                  /* small tag = 0x30 or 0x31           */
-    unsigned char Priority;             /* Optional; if missing then x01; else*/
-                                        /*  x00 = best possible               */
-                                        /*  x01 = acceptible                  */
-                                        /*  x02 = sub-optimal but functional  */
-    } S6_Pack;
-
-  struct _S7_Pack{                      /* END DEPENDENT FUNCTION PACKET      */
-    unsigned char Tag;                  /* small tag = 0x38                   */
-    } S7_Pack;
-
-  struct _S8_Pack{                      /* VARIABLE I/O PORT PACKET           */
-    unsigned char Tag;                  /* small tag x47                      */
-    unsigned char IOInfo;               /* x0  = decode only bits(9:0);       */
-#define  ISAAddr16bit         0x01      /* x01 = decode bits(15:0)            */
-    unsigned char RangeMin[2];          /* Min base address                   */
-    unsigned char RangeMax[2];          /* Max base address                   */
-    unsigned char IOAlign;              /* base alignmt, incr in 1B blocks    */
-    unsigned char IONum;                /* number of contiguous I/O ports     */
-    } S8_Pack;
-
-  struct _S9_Pack{                      /* FIXED I/O PORT PACKET              */
-    unsigned char Tag;                  /* small tag = 0x4b                   */
-    unsigned char Range[2];             /* base address 10 bits               */
-    unsigned char IONum;                /* number of contiguous I/O ports     */
-    } S9_Pack;
-
-  struct _S14_Pack{                     /* VENDOR DEFINED PACKET              */
-    unsigned char Tag;                  /* small tag = 0x7m m = 1-7           */
-    union _S14_Data{
-      unsigned char Data[7];            /* Vendor defined                     */
-      struct _S14_PPCPack{              /* Pr*p s14 pack                      */
-         unsigned char Type;            /* 00=non-IBM                         */
-         unsigned char PPCData[6];      /* Vendor defined                     */
-        } S14_PPCPack;
-      } S14_Data;
-    } S14_Pack;
-
-  struct _S15_Pack{                     /* END PACKET                         */
-    unsigned char Tag;                  /* small tag = 0x78 or 0x79           */
-    unsigned char Check;                /* optional - checksum                */
-    } S15_Pack;
-
-  struct _L1_Pack{                      /* MEMORY RANGE PACKET                */
-    unsigned char Tag;                  /* large tag = 0x81                   */
-    unsigned char Count0;               /* x09                                */
-    unsigned char Count1;               /* x00                                */
-    unsigned char Data[9];              /* a variable array of bytes,         */
-                                        /* count in tag                       */
-    } L1_Pack;
-
-  struct _L2_Pack{                      /* ANSI ID STRING PACKET              */
-    unsigned char Tag;                  /* large tag = 0x82                   */
-    unsigned char Count0;               /* Length of string                   */
-    unsigned char Count1;
-    unsigned char Identifier[1];        /* a variable array of bytes,         */
-                                        /* count in tag                       */
-    } L2_Pack;
-
-  struct _L3_Pack{                      /* UNICODE ID STRING PACKET           */
-    unsigned char Tag;                  /* large tag = 0x83                   */
-    unsigned char Count0;               /* Length + 2 of string               */
-    unsigned char Count1;
-    unsigned char Country0;             /* TBD                                */
-    unsigned char Country1;             /* TBD                                */
-    unsigned char Identifier[1];        /* a variable array of bytes,         */
-                                        /* count in tag                       */
-    } L3_Pack;
-
-  struct _L4_Pack{                      /* VENDOR DEFINED PACKET              */
-    unsigned char Tag;                  /* large tag = 0x84                   */
-    unsigned char Count0;
-    unsigned char Count1;
-    union _L4_Data{
-      unsigned char Data[1];            /* a variable array of bytes,         */
-                                        /* count in tag                       */
-      struct _L4_PPCPack{               /* Pr*p L4 packet                     */
-         unsigned char Type;            /* 00=non-IBM                         */
-         unsigned char PPCData[1];      /* a variable array of bytes,         */
-                                        /* count in tag                       */
-        } L4_PPCPack;
-      } L4_Data;
-    } L4_Pack;
-
-  struct _L5_Pack{
-    unsigned char Tag;                  /* large tag = 0x85                   */
-    unsigned char Count0;               /* Count = 17                         */
-    unsigned char Count1;
-    unsigned char Data[17];
-    } L5_Pack;
-
-  struct _L6_Pack{
-    unsigned char Tag;                  /* large tag = 0x86                   */
-    unsigned char Count0;               /* Count = 9                          */
-    unsigned char Count1;
-    unsigned char Data[9];
-    } L6_Pack;
-
-  } PnP_TAG_PACKET;
-
-#endif /* __ASSEMBLY__ */
-#endif  /* ndef _PNP_ */
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/ppc4xx_dma.h b/include/asm-ppc/ppc4xx_dma.h
deleted file mode 100644
index 935d1e05366..00000000000
--- a/include/asm-ppc/ppc4xx_dma.h
+++ /dev/null
@@ -1,579 +0,0 @@
-/*
- * include/asm-ppc/ppc4xx_dma.h
- *
- * IBM PPC4xx DMA engine library
- *
- * Copyright 2000-2004 MontaVista Software Inc.
- *
- * Cleaned up a bit more, Matt Porter <mporter@kernel.crashing.org>
- *
- * Original code by Armin Kuster <akuster@mvista.com>
- * and Pete Popov <ppopov@mvista.com>
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- *
- * You should have received a copy of the  GNU General Public License along
- * with this program; if not, write  to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifdef __KERNEL__
-#ifndef __ASMPPC_PPC4xx_DMA_H
-#define __ASMPPC_PPC4xx_DMA_H
-
-#include <linux/types.h>
-#include <asm/mmu.h>
-#include <asm/ibm4xx.h>
-
-#undef DEBUG_4xxDMA
-
-#define MAX_PPC4xx_DMA_CHANNELS		4
-
-/*
- * Function return status codes
- * These values are used to indicate whether or not the function
- * call was successful, or a bad/invalid parameter was passed.
- */
-#define DMA_STATUS_GOOD			0
-#define DMA_STATUS_BAD_CHANNEL		1
-#define DMA_STATUS_BAD_HANDLE		2
-#define DMA_STATUS_BAD_MODE		3
-#define DMA_STATUS_NULL_POINTER		4
-#define DMA_STATUS_OUT_OF_MEMORY	5
-#define DMA_STATUS_SGL_LIST_EMPTY	6
-#define DMA_STATUS_GENERAL_ERROR	7
-#define DMA_STATUS_CHANNEL_NOTFREE	8
-
-#define DMA_CHANNEL_BUSY		0x80000000
-
-/*
- * These indicate status as returned from the DMA Status Register.
- */
-#define DMA_STATUS_NO_ERROR	0
-#define DMA_STATUS_CS		1	/* Count Status        */
-#define DMA_STATUS_TS		2	/* Transfer Status     */
-#define DMA_STATUS_DMA_ERROR	3	/* DMA Error Occurred  */
-#define DMA_STATUS_DMA_BUSY	4	/* The channel is busy */
-
-
-/*
- * DMA Channel Control Registers
- */
-
-#ifdef CONFIG_44x
-#define	PPC4xx_DMA_64BIT
-#define DMA_CR_OFFSET 1
-#else
-#define DMA_CR_OFFSET 0
-#endif
-
-#define DMA_CE_ENABLE        (1<<31)	/* DMA Channel Enable */
-#define SET_DMA_CE_ENABLE(x) (((x)&0x1)<<31)
-#define GET_DMA_CE_ENABLE(x) (((x)&DMA_CE_ENABLE)>>31)
-
-#define DMA_CIE_ENABLE        (1<<30)	/* DMA Channel Interrupt Enable */
-#define SET_DMA_CIE_ENABLE(x) (((x)&0x1)<<30)
-#define GET_DMA_CIE_ENABLE(x) (((x)&DMA_CIE_ENABLE)>>30)
-
-#define DMA_TD                (1<<29)
-#define SET_DMA_TD(x)         (((x)&0x1)<<29)
-#define GET_DMA_TD(x)         (((x)&DMA_TD)>>29)
-
-#define DMA_PL                (1<<28)	/* Peripheral Location */
-#define SET_DMA_PL(x)         (((x)&0x1)<<28)
-#define GET_DMA_PL(x)         (((x)&DMA_PL)>>28)
-
-#define EXTERNAL_PERIPHERAL    0
-#define INTERNAL_PERIPHERAL    1
-
-#define SET_DMA_PW(x)     (((x)&0x3)<<(26-DMA_CR_OFFSET))	/* Peripheral Width */
-#define DMA_PW_MASK       SET_DMA_PW(3)
-#define   PW_8                 0
-#define   PW_16                1
-#define   PW_32                2
-#define   PW_64                3
-/* FIXME: Add PW_128 support for 440GP DMA block */
-#define GET_DMA_PW(x)     (((x)&DMA_PW_MASK)>>(26-DMA_CR_OFFSET))
-
-#define DMA_DAI           (1<<(25-DMA_CR_OFFSET))	/* Destination Address Increment */
-#define SET_DMA_DAI(x)    (((x)&0x1)<<(25-DMA_CR_OFFSET))
-
-#define DMA_SAI           (1<<(24-DMA_CR_OFFSET))	/* Source Address Increment */
-#define SET_DMA_SAI(x)    (((x)&0x1)<<(24-DMA_CR_OFFSET))
-
-#define DMA_BEN           (1<<(23-DMA_CR_OFFSET))	/* Buffer Enable */
-#define SET_DMA_BEN(x)    (((x)&0x1)<<(23-DMA_CR_OFFSET))
-
-#define SET_DMA_TM(x)     (((x)&0x3)<<(21-DMA_CR_OFFSET))	/* Transfer Mode */
-#define DMA_TM_MASK       SET_DMA_TM(3)
-#define   TM_PERIPHERAL        0	/* Peripheral */
-#define   TM_RESERVED          1	/* Reserved */
-#define   TM_S_MM              2	/* Memory to Memory */
-#define   TM_D_MM              3	/* Device Paced Memory to Memory */
-#define GET_DMA_TM(x)     (((x)&DMA_TM_MASK)>>(21-DMA_CR_OFFSET))
-
-#define SET_DMA_PSC(x)    (((x)&0x3)<<(19-DMA_CR_OFFSET))	/* Peripheral Setup Cycles */
-#define DMA_PSC_MASK      SET_DMA_PSC(3)
-#define GET_DMA_PSC(x)    (((x)&DMA_PSC_MASK)>>(19-DMA_CR_OFFSET))
-
-#define SET_DMA_PWC(x)    (((x)&0x3F)<<(13-DMA_CR_OFFSET))	/* Peripheral Wait Cycles */
-#define DMA_PWC_MASK      SET_DMA_PWC(0x3F)
-#define GET_DMA_PWC(x)    (((x)&DMA_PWC_MASK)>>(13-DMA_CR_OFFSET))
-
-#define SET_DMA_PHC(x)    (((x)&0x7)<<(10-DMA_CR_OFFSET))	/* Peripheral Hold Cycles */
-#define DMA_PHC_MASK      SET_DMA_PHC(0x7)
-#define GET_DMA_PHC(x)    (((x)&DMA_PHC_MASK)>>(10-DMA_CR_OFFSET))
-
-#define DMA_ETD_OUTPUT     (1<<(9-DMA_CR_OFFSET))	/* EOT pin is a TC output */
-#define SET_DMA_ETD(x)     (((x)&0x1)<<(9-DMA_CR_OFFSET))
-
-#define DMA_TCE_ENABLE     (1<<(8-DMA_CR_OFFSET))
-#define SET_DMA_TCE(x)     (((x)&0x1)<<(8-DMA_CR_OFFSET))
-
-#define DMA_DEC            (1<<(2))	/* Address Decrement */
-#define SET_DMA_DEC(x)     (((x)&0x1)<<2)
-#define GET_DMA_DEC(x)     (((x)&DMA_DEC)>>2)
-
-
-/*
- * Transfer Modes
- * These modes are defined in a way that makes it possible to
- * simply "or" in the value in the control register.
- */
-
-#define DMA_MODE_MM		(SET_DMA_TM(TM_S_MM))	/* memory to memory */
-
-				/* Device-paced memory to memory, */
-				/* device is at source address    */
-#define DMA_MODE_MM_DEVATSRC	(DMA_TD | SET_DMA_TM(TM_D_MM))
-
-				/* Device-paced memory to memory,      */
-				/* device is at destination address    */
-#define DMA_MODE_MM_DEVATDST	(SET_DMA_TM(TM_D_MM))
-
-/* 405gp/440gp */
-#define SET_DMA_PREFETCH(x)   (((x)&0x3)<<(4-DMA_CR_OFFSET))	/* Memory Read Prefetch */
-#define DMA_PREFETCH_MASK      SET_DMA_PREFETCH(3)
-#define   PREFETCH_1           0	/* Prefetch 1 Double Word */
-#define   PREFETCH_2           1
-#define   PREFETCH_4           2
-#define GET_DMA_PREFETCH(x) (((x)&DMA_PREFETCH_MASK)>>(4-DMA_CR_OFFSET))
-
-#define DMA_PCE            (1<<(3-DMA_CR_OFFSET))	/* Parity Check Enable */
-#define SET_DMA_PCE(x)     (((x)&0x1)<<(3-DMA_CR_OFFSET))
-#define GET_DMA_PCE(x)     (((x)&DMA_PCE)>>(3-DMA_CR_OFFSET))
-
-/* stb3x */
-
-#define DMA_ECE_ENABLE (1<<5)
-#define SET_DMA_ECE(x) (((x)&0x1)<<5)
-#define GET_DMA_ECE(x) (((x)&DMA_ECE_ENABLE)>>5)
-
-#define DMA_TCD_DISABLE	(1<<4)
-#define SET_DMA_TCD(x) (((x)&0x1)<<4)
-#define GET_DMA_TCD(x) (((x)&DMA_TCD_DISABLE)>>4)
-
-typedef uint32_t sgl_handle_t;
-
-#ifdef CONFIG_PPC4xx_EDMA
-
-#define SGL_LIST_SIZE 4096
-#define DMA_PPC4xx_SIZE SGL_LIST_SIZE
-
-#define SET_DMA_PRIORITY(x)   (((x)&0x3)<<(6-DMA_CR_OFFSET))	/* DMA Channel Priority */
-#define DMA_PRIORITY_MASK SET_DMA_PRIORITY(3)
-#define PRIORITY_LOW           0
-#define PRIORITY_MID_LOW       1
-#define PRIORITY_MID_HIGH      2
-#define PRIORITY_HIGH          3
-#define GET_DMA_PRIORITY(x) (((x)&DMA_PRIORITY_MASK)>>(6-DMA_CR_OFFSET))
-
-/*
- * DMA Polarity Configuration Register
- */
-#define DMAReq_ActiveLow(chan) (1<<(31-(chan*3)))
-#define DMAAck_ActiveLow(chan) (1<<(30-(chan*3)))
-#define EOT_ActiveLow(chan)    (1<<(29-(chan*3)))	/* End of Transfer */
-
-/*
- * DMA Sleep Mode Register
- */
-#define SLEEP_MODE_ENABLE (1<<21)
-
-/*
- * DMA Status Register
- */
-#define DMA_CS0           (1<<31)	/* Terminal Count has been reached */
-#define DMA_CS1           (1<<30)
-#define DMA_CS2           (1<<29)
-#define DMA_CS3           (1<<28)
-
-#define DMA_TS0           (1<<27)	/* End of Transfer has been requested */
-#define DMA_TS1           (1<<26)
-#define DMA_TS2           (1<<25)
-#define DMA_TS3           (1<<24)
-
-#define DMA_CH0_ERR       (1<<23)	/* DMA Chanel 0 Error */
-#define DMA_CH1_ERR       (1<<22)
-#define DMA_CH2_ERR       (1<<21)
-#define DMA_CH3_ERR       (1<<20)
-
-#define DMA_IN_DMA_REQ0   (1<<19)	/* Internal DMA Request is pending */
-#define DMA_IN_DMA_REQ1   (1<<18)
-#define DMA_IN_DMA_REQ2   (1<<17)
-#define DMA_IN_DMA_REQ3   (1<<16)
-
-#define DMA_EXT_DMA_REQ0  (1<<15)	/* External DMA Request is pending */
-#define DMA_EXT_DMA_REQ1  (1<<14)
-#define DMA_EXT_DMA_REQ2  (1<<13)
-#define DMA_EXT_DMA_REQ3  (1<<12)
-
-#define DMA_CH0_BUSY      (1<<11)	/* DMA Channel 0 Busy */
-#define DMA_CH1_BUSY      (1<<10)
-#define DMA_CH2_BUSY       (1<<9)
-#define DMA_CH3_BUSY       (1<<8)
-
-#define DMA_SG0            (1<<7)	/* DMA Channel 0 Scatter/Gather in progress */
-#define DMA_SG1            (1<<6)
-#define DMA_SG2            (1<<5)
-#define DMA_SG3            (1<<4)
-
-/* DMA Channel Count Register */
-#define DMA_CTC_BTEN     (1<<23)    /* Burst Enable/Disable bit */
-#define DMA_CTC_BSIZ_MSK (3<<21)    /* Mask of the Burst size bits */
-#define DMA_CTC_BSIZ_2   (0)
-#define DMA_CTC_BSIZ_4   (1<<21)
-#define DMA_CTC_BSIZ_8   (2<<21)
-#define DMA_CTC_BSIZ_16  (3<<21)
-
-/*
- * DMA SG Command Register
- */
-#define SSG_ENABLE(chan)   	(1<<(31-chan))	/* Start Scatter Gather */
-#define SSG_MASK_ENABLE(chan)	(1<<(15-chan))	/* Enable writing to SSG0 bit */
-
-/*
- * DMA Scatter/Gather Descriptor Bit fields
- */
-#define SG_LINK            (1<<31)	/* Link */
-#define SG_TCI_ENABLE      (1<<29)	/* Enable Terminal Count Interrupt */
-#define SG_ETI_ENABLE      (1<<28)	/* Enable End of Transfer Interrupt */
-#define SG_ERI_ENABLE      (1<<27)	/* Enable Error Interrupt */
-#define SG_COUNT_MASK       0xFFFF	/* Count Field */
-
-#define SET_DMA_CONTROL \
- 		(SET_DMA_CIE_ENABLE(p_init->int_enable) | /* interrupt enable         */ \
- 		SET_DMA_BEN(p_init->buffer_enable)     | /* buffer enable            */\
-		SET_DMA_ETD(p_init->etd_output)        | /* end of transfer pin      */ \
-	       	SET_DMA_TCE(p_init->tce_enable)        | /* terminal count enable    */ \
-                SET_DMA_PL(p_init->pl)                 | /* peripheral location      */ \
-                SET_DMA_DAI(p_init->dai)               | /* dest addr increment      */ \
-                SET_DMA_SAI(p_init->sai)               | /* src addr increment       */ \
-                SET_DMA_PRIORITY(p_init->cp)           |  /* channel priority        */ \
-                SET_DMA_PW(p_init->pwidth)             |  /* peripheral/bus width    */ \
-                SET_DMA_PSC(p_init->psc)               |  /* peripheral setup cycles */ \
-                SET_DMA_PWC(p_init->pwc)               |  /* peripheral wait cycles  */ \
-                SET_DMA_PHC(p_init->phc)               |  /* peripheral hold cycles  */ \
-                SET_DMA_PREFETCH(p_init->pf)              /* read prefetch           */)
-
-#define GET_DMA_POLARITY(chan) (DMAReq_ActiveLow(chan) | DMAAck_ActiveLow(chan) | EOT_ActiveLow(chan))
-
-#elif defined(CONFIG_STB03xxx)		/* stb03xxx */
-
-#define DMA_PPC4xx_SIZE	4096
-
-/*
- * DMA Status Register
- */
-
-#define SET_DMA_PRIORITY(x)   (((x)&0x00800001))	/* DMA Channel Priority */
-#define DMA_PRIORITY_MASK	0x00800001
-#define   PRIORITY_LOW         	0x00000000
-#define   PRIORITY_MID_LOW     	0x00000001
-#define   PRIORITY_MID_HIGH    	0x00800000
-#define   PRIORITY_HIGH        	0x00800001
-#define GET_DMA_PRIORITY(x) (((((x)&DMA_PRIORITY_MASK) &0x00800000) >> 22 ) | (((x)&DMA_PRIORITY_MASK) &0x00000001))
-
-#define DMA_CS0           (1<<31)	/* Terminal Count has been reached */
-#define DMA_CS1           (1<<30)
-#define DMA_CS2           (1<<29)
-#define DMA_CS3           (1<<28)
-
-#define DMA_TS0           (1<<27)	/* End of Transfer has been requested */
-#define DMA_TS1           (1<<26)
-#define DMA_TS2           (1<<25)
-#define DMA_TS3           (1<<24)
-
-#define DMA_CH0_ERR       (1<<23)	/* DMA Chanel 0 Error */
-#define DMA_CH1_ERR       (1<<22)
-#define DMA_CH2_ERR       (1<<21)
-#define DMA_CH3_ERR       (1<<20)
-
-#define DMA_CT0		  (1<<19)	/* Chained transfere */
-
-#define DMA_IN_DMA_REQ0   (1<<18)	/* Internal DMA Request is pending */
-#define DMA_IN_DMA_REQ1   (1<<17)
-#define DMA_IN_DMA_REQ2   (1<<16)
-#define DMA_IN_DMA_REQ3   (1<<15)
-
-#define DMA_EXT_DMA_REQ0  (1<<14)	/* External DMA Request is pending */
-#define DMA_EXT_DMA_REQ1  (1<<13)
-#define DMA_EXT_DMA_REQ2  (1<<12)
-#define DMA_EXT_DMA_REQ3  (1<<11)
-
-#define DMA_CH0_BUSY      (1<<10)	/* DMA Channel 0 Busy */
-#define DMA_CH1_BUSY      (1<<9)
-#define DMA_CH2_BUSY       (1<<8)
-#define DMA_CH3_BUSY       (1<<7)
-
-#define DMA_CT1            (1<<6)	/* Chained transfere */
-#define DMA_CT2            (1<<5)
-#define DMA_CT3            (1<<4)
-
-#define DMA_CH_ENABLE (1<<7)
-#define SET_DMA_CH(x) (((x)&0x1)<<7)
-#define GET_DMA_CH(x) (((x)&DMA_CH_ENABLE)>>7)
-
-/* STBx25xxx dma unique */
-/* enable device port on a dma channel
- * example ext 0 on dma 1
- */
-
-#define	SSP0_RECV	15
-#define	SSP0_XMIT	14
-#define EXT_DMA_0	12
-#define	SC1_XMIT	11
-#define SC1_RECV	10
-#define EXT_DMA_2	9
-#define	EXT_DMA_3	8
-#define SERIAL2_XMIT	7
-#define SERIAL2_RECV	6
-#define SC0_XMIT 	5
-#define	SC0_RECV	4
-#define	SERIAL1_XMIT	3
-#define SERIAL1_RECV	2
-#define	SERIAL0_XMIT	1
-#define SERIAL0_RECV	0
-
-#define DMA_CHAN_0	1
-#define DMA_CHAN_1	2
-#define DMA_CHAN_2	3
-#define DMA_CHAN_3	4
-
-/* end STBx25xx */
-
-/*
- * Bit 30 must be one for Redwoods, otherwise transfers may receive errors.
- */
-#define DMA_CR_MB0 0x2
-
-#define SET_DMA_CONTROL \
-       		(SET_DMA_CIE_ENABLE(p_init->int_enable) |  /* interrupt enable         */ \
-		SET_DMA_ETD(p_init->etd_output)        |  /* end of transfer pin      */ \
-		SET_DMA_TCE(p_init->tce_enable)        |  /* terminal count enable    */ \
-		SET_DMA_PL(p_init->pl)                 |  /* peripheral location      */ \
-		SET_DMA_DAI(p_init->dai)               |  /* dest addr increment      */ \
-		SET_DMA_SAI(p_init->sai)               |  /* src addr increment       */ \
-		SET_DMA_PRIORITY(p_init->cp)           |  /* channel priority        */  \
-		SET_DMA_PW(p_init->pwidth)             |  /* peripheral/bus width    */ \
-		SET_DMA_PSC(p_init->psc)               |  /* peripheral setup cycles */ \
-		SET_DMA_PWC(p_init->pwc)               |  /* peripheral wait cycles  */ \
-		SET_DMA_PHC(p_init->phc)               |  /* peripheral hold cycles  */ \
-		SET_DMA_TCD(p_init->tcd_disable)	  |  /* TC chain mode disable   */ \
-		SET_DMA_ECE(p_init->ece_enable)	  |  /* ECE chanin mode enable  */ \
-		SET_DMA_CH(p_init->ch_enable)	|    /* Chain enable 	        */ \
-		DMA_CR_MB0				/* must be one */)
-
-#define GET_DMA_POLARITY(chan) chan
-
-#endif
-
-typedef struct {
-	unsigned short in_use;	/* set when channel is being used, clr when
-				 * available.
-				 */
-	/*
-	 * Valid polarity settings:
-	 *   DMAReq_ActiveLow(n)
-	 *   DMAAck_ActiveLow(n)
-	 *   EOT_ActiveLow(n)
-	 *
-	 *   n is 0 to max dma chans
-	 */
-	unsigned int polarity;
-
-	char buffer_enable;	/* Boolean: buffer enable            */
-	char tce_enable;	/* Boolean: terminal count enable    */
-	char etd_output;	/* Boolean: eot pin is a tc output   */
-	char pce;		/* Boolean: parity check enable      */
-
-	/*
-	 * Peripheral location:
-	 * INTERNAL_PERIPHERAL (UART0 on the 405GP)
-	 * EXTERNAL_PERIPHERAL
-	 */
-	char pl;		/* internal/external peripheral      */
-
-	/*
-	 * Valid pwidth settings:
-	 *   PW_8
-	 *   PW_16
-	 *   PW_32
-	 *   PW_64
-	 */
-	unsigned int pwidth;
-
-	char dai;		/* Boolean: dst address increment   */
-	char sai;		/* Boolean: src address increment   */
-
-	/*
-	 * Valid psc settings: 0-3
-	 */
-	unsigned int psc;	/* Peripheral Setup Cycles         */
-
-	/*
-	 * Valid pwc settings:
-	 * 0-63
-	 */
-	unsigned int pwc;	/* Peripheral Wait Cycles          */
-
-	/*
-	 * Valid phc settings:
-	 * 0-7
-	 */
-	unsigned int phc;	/* Peripheral Hold Cycles          */
-
-	/*
-	 * Valid cp (channel priority) settings:
-	 *   PRIORITY_LOW
-	 *   PRIORITY_MID_LOW
-	 *   PRIORITY_MID_HIGH
-	 *   PRIORITY_HIGH
-	 */
-	unsigned int cp;	/* channel priority                */
-
-	/*
-	 * Valid pf (memory read prefetch) settings:
-	 *
-	 *   PREFETCH_1
-	 *   PREFETCH_2
-	 *   PREFETCH_4
-	 */
-	unsigned int pf;	/* memory read prefetch            */
-
-	/*
-	 * Boolean: channel interrupt enable
-	 * NOTE: for sgl transfers, only the last descriptor will be setup to
-	 * interrupt.
-	 */
-	char int_enable;
-
-	char shift;		/* easy access to byte_count shift, based on */
-	/* the width of the channel                  */
-
-	uint32_t control;	/* channel control word                      */
-
-	/* These variabled are used ONLY in single dma transfers              */
-	unsigned int mode;	/* transfer mode                     */
-	phys_addr_t addr;
-	char ce;		/* channel enable */
-#ifdef CONFIG_STB03xxx
-	char ch_enable;
-	char tcd_disable;
-	char ece_enable;
-	char td;		/* transfer direction */
-#endif
-
-	char int_on_final_sg;/* for scatter/gather - only interrupt on last sg */
-} ppc_dma_ch_t;
-
-/*
- * PPC44x DMA implementations have a slightly different
- * descriptor layout.  Probably moved about due to the
- * change to 64-bit addresses and link pointer. I don't
- * know why they didn't just leave control_count after
- * the dst_addr.
- */
-#ifdef PPC4xx_DMA_64BIT
-typedef struct {
-	uint32_t control;
-	uint32_t control_count;
-	phys_addr_t src_addr;
-	phys_addr_t dst_addr;
-	phys_addr_t next;
-} ppc_sgl_t;
-#else
-typedef struct {
-	uint32_t control;
-	phys_addr_t src_addr;
-	phys_addr_t dst_addr;
-	uint32_t control_count;
-	uint32_t next;
-} ppc_sgl_t;
-#endif
-
-typedef struct {
-	unsigned int dmanr;
-	uint32_t control;	/* channel ctrl word; loaded from each descrptr */
-	uint32_t sgl_control;	/* LK, TCI, ETI, and ERI bits in sgl descriptor */
-	dma_addr_t dma_addr;	/* dma (physical) address of this list          */
-	ppc_sgl_t *phead;
-	dma_addr_t phead_dma;
-	ppc_sgl_t *ptail;
-	dma_addr_t ptail_dma;
-} sgl_list_info_t;
-
-typedef struct {
-	phys_addr_t *src_addr;
-	phys_addr_t *dst_addr;
-	phys_addr_t dma_src_addr;
-	phys_addr_t dma_dst_addr;
-} pci_alloc_desc_t;
-
-extern ppc_dma_ch_t dma_channels[];
-
-/*
- * The DMA API are in ppc4xx_dma.c and ppc4xx_sgdma.c
- */
-extern int ppc4xx_init_dma_channel(unsigned int, ppc_dma_ch_t *);
-extern int ppc4xx_get_channel_config(unsigned int, ppc_dma_ch_t *);
-extern int ppc4xx_set_channel_priority(unsigned int, unsigned int);
-extern unsigned int ppc4xx_get_peripheral_width(unsigned int);
-extern void ppc4xx_set_sg_addr(int, phys_addr_t);
-extern int ppc4xx_add_dma_sgl(sgl_handle_t, phys_addr_t, phys_addr_t, unsigned int);
-extern void ppc4xx_enable_dma_sgl(sgl_handle_t);
-extern void ppc4xx_disable_dma_sgl(sgl_handle_t);
-extern int ppc4xx_get_dma_sgl_residue(sgl_handle_t, phys_addr_t *, phys_addr_t *);
-extern int ppc4xx_delete_dma_sgl_element(sgl_handle_t, phys_addr_t *, phys_addr_t *);
-extern int ppc4xx_alloc_dma_handle(sgl_handle_t *, unsigned int, unsigned int);
-extern void ppc4xx_free_dma_handle(sgl_handle_t);
-extern int ppc4xx_get_dma_status(void);
-extern int ppc4xx_enable_burst(unsigned int);
-extern int ppc4xx_disable_burst(unsigned int);
-extern int ppc4xx_set_burst_size(unsigned int, unsigned int);
-extern void ppc4xx_set_src_addr(int dmanr, phys_addr_t src_addr);
-extern void ppc4xx_set_dst_addr(int dmanr, phys_addr_t dst_addr);
-extern void ppc4xx_enable_dma(unsigned int dmanr);
-extern void ppc4xx_disable_dma(unsigned int dmanr);
-extern void ppc4xx_set_dma_count(unsigned int dmanr, unsigned int count);
-extern int ppc4xx_get_dma_residue(unsigned int dmanr);
-extern void ppc4xx_set_dma_addr2(unsigned int dmanr, phys_addr_t src_dma_addr,
-				 phys_addr_t dst_dma_addr);
-extern int ppc4xx_enable_dma_interrupt(unsigned int dmanr);
-extern int ppc4xx_disable_dma_interrupt(unsigned int dmanr);
-extern int ppc4xx_clr_dma_status(unsigned int dmanr);
-extern int ppc4xx_map_dma_port(unsigned int dmanr, unsigned int ocp_dma,short dma_chan);
-extern int ppc4xx_disable_dma_port(unsigned int dmanr, unsigned int ocp_dma,short dma_chan);
-extern int ppc4xx_set_dma_mode(unsigned int dmanr, unsigned int mode);
-
-/* These are in kernel/dma.c: */
-
-/* reserve a DMA channel */
-extern int request_dma(unsigned int dmanr, const char *device_id);
-/* release it again */
-extern void free_dma(unsigned int dmanr);
-#endif
-#endif				/* __KERNEL__ */
diff --git a/include/asm-ppc/ppc4xx_pic.h b/include/asm-ppc/ppc4xx_pic.h
deleted file mode 100644
index e44261206f8..00000000000
--- a/include/asm-ppc/ppc4xx_pic.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * include/asm-ppc/ppc4xx_pic.h
- *
- * Interrupt controller driver for PowerPC 4xx-based processors.
- *
- * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
- *
- * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
- * Copyright (c) 2004 Zultys Technologies
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-
-#ifndef	__PPC4XX_PIC_H__
-#define	__PPC4XX_PIC_H__
-
-#include <linux/types.h>
-#include <linux/irq.h>
-
-/* "Fixed" UIC settings (they are chip, not board specific),
- * e.g. polarity/triggerring for internal interrupt sources.
- *
- * Platform port should provide NR_UICS-sized array named ppc4xx_core_uic_cfg
- * with these "fixed" settings: .polarity contains exact value which will
- * be written (masked with "ext_irq_mask") into UICx_PR register,
- * .triggering - to UICx_TR.
- *
- * Settings for external IRQs can be specified separately by the
- * board support code. In this case properly sized array of unsigned
- * char named ppc4xx_uic_ext_irq_cfg should be filled with correct
- * values using IRQ_SENSE_XXXXX and IRQ_POLARITY_XXXXXXX defines.
- *
- * If these arrays aren't provided, UIC initialization code keeps firmware
- * configuration. Also, ppc4xx_uic_ext_irq_cfg implies ppc4xx_core_uic_cfg
- * is defined.
- *
- * Both ppc4xx_core_uic_cfg and ppc4xx_uic_ext_irq_cfg are declared as
- * "weak" symbols in ppc4xx_pic.c
- *
- */
-struct ppc4xx_uic_settings {
-	u32 polarity;
-	u32 triggering;
-	u32 ext_irq_mask;
-};
-
-extern void ppc4xx_pic_init(void);
-
-#endif				/* __PPC4XX_PIC_H__ */
diff --git a/include/asm-ppc/ppc_sys.h b/include/asm-ppc/ppc_sys.h
deleted file mode 100644
index d2fee41d600..00000000000
--- a/include/asm-ppc/ppc_sys.h
+++ /dev/null
@@ -1,106 +0,0 @@
-/*
- * include/asm-ppc/ppc_sys.h
- *
- * PPC system definitions and library functions
- *
- * Maintainer: Kumar Gala <galak@kernel.crashing.org>
- *
- * Copyright 2005 Freescale Semiconductor, Inc
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-
-#ifdef __KERNEL__
-#ifndef __ASM_PPC_SYS_H
-#define __ASM_PPC_SYS_H
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/types.h>
-
-#if defined(CONFIG_8260)
-#include <asm/mpc8260.h>
-#elif defined(CONFIG_8xx)
-#include <asm/mpc8xx.h>
-#elif defined(CONFIG_PPC_MPC52xx)
-#include <asm/mpc52xx.h>
-#elif defined(CONFIG_MPC10X_BRIDGE)
-#include <asm/mpc10x.h>
-#else
-#error "need definition of ppc_sys_devices"
-#endif
-
-#define PPC_SYS_IORESOURCE_FIXUPPED	0x00000001	
-
-struct ppc_sys_spec {
-	/* PPC sys is matched via (ID & mask) == value, id could be
-	 * PVR, SVR, IMMR, * etc. */
-	u32 			mask;
-	u32 			value;
-	u32 			num_devices;
-	char 			*ppc_sys_name;
-	u8			config[NUM_PPC_SYS_DEVS];
-	enum ppc_sys_devices 	*device_list;
-};
-
-struct platform_notify_dev_map {
-	const char *bus_id;
-	void (*rtn)(struct platform_device * pdev, int idx);
-};
-
-enum platform_device_func {
-	PPC_SYS_FUNC_DUMMY = 0,
-	PPC_SYS_FUNC_ETH = 1,
-	PPC_SYS_FUNC_UART = 2,
-	PPC_SYS_FUNC_HLDC = 3,
-	PPC_SYS_FUNC_USB = 4,
-	PPC_SYS_FUNC_IRDA = 5,
-};
-
-#define PPC_SYS_CONFIG_DISABLED		1
-
-/* describes all specific chips and which devices they have on them */
-extern struct ppc_sys_spec ppc_sys_specs[];
-extern struct ppc_sys_spec *cur_ppc_sys_spec;
-
-/* determine which specific SOC we are */
-extern void identify_ppc_sys_by_id(u32 id) __init;
-extern void identify_ppc_sys_by_name(char *name) __init;
-extern void identify_ppc_sys_by_name_and_id(char *name, u32 id) __init;
-
-/* describes all devices that may exist in a given family of processors */
-extern struct platform_device ppc_sys_platform_devices[];
-
-/* allow any platform_device fixup to occur before device is registered */
-extern int (*ppc_sys_device_fixup) (struct platform_device * pdev);
-
-/* Update all memory resources by paddr, call before platform_device_register */
-extern void ppc_sys_fixup_mem_resource(struct platform_device *pdev,
-				       phys_addr_t paddr) __init;
-
-/* Get platform_data pointer out of platform device, call before platform_device_register */
-extern void *ppc_sys_get_pdata(enum ppc_sys_devices dev) __init;
-
-/* remove a device from the system */
-extern void ppc_sys_device_remove(enum ppc_sys_devices dev);
-
-/* Function assignment stuff */
-void ppc_sys_device_initfunc(void);
-void ppc_sys_device_setfunc(enum ppc_sys_devices dev,
-			    enum platform_device_func func);
-void ppc_sys_device_set_func_all(enum platform_device_func func);
-
-void platform_notify_map(const struct platform_notify_dev_map *map,
-			 struct device *dev);
-
-/* Enable / disable stuff */
-void ppc_sys_device_disable(enum ppc_sys_devices dev);
-void ppc_sys_device_enable(enum ppc_sys_devices dev);
-void ppc_sys_device_enable_all(void);
-void ppc_sys_device_disable_all(void);
-
-#endif				/* __ASM_PPC_SYS_H */
-#endif				/* __KERNEL__ */
diff --git a/include/asm-ppc/ppcboot.h b/include/asm-ppc/ppcboot.h
deleted file mode 100644
index 3819e17cd7b..00000000000
--- a/include/asm-ppc/ppcboot.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * (C) Copyright 2000, 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ASM_PPCBOOT_H__
-#define __ASM_PPCBOOT_H__
-
-/*
- * Board information passed to kernel from PPCBoot
- *
- * include/asm-ppc/ppcboot.h
- */
-
-#ifndef __ASSEMBLY__
-#include <linux/types.h>
-
-typedef struct bd_info {
-	unsigned long	bi_memstart;	/* start of DRAM memory */
-	unsigned long	bi_memsize;	/* size	 of DRAM memory in bytes */
-	unsigned long	bi_flashstart;	/* start of FLASH memory */
-	unsigned long	bi_flashsize;	/* size	 of FLASH memory */
-	unsigned long	bi_flashoffset; /* reserved area for startup monitor */
-	unsigned long	bi_sramstart;	/* start of SRAM memory */
-	unsigned long	bi_sramsize;	/* size	 of SRAM memory */
-#if defined(CONFIG_8xx) || defined(CONFIG_CPM2)
-	unsigned long	bi_immr_base;	/* base of IMMR register */
-#endif
-#if defined(CONFIG_PPC_MPC52xx)
-	unsigned long   bi_mbar_base;   /* base of internal registers */
-#endif
-	unsigned long	bi_bootflags;	/* boot / reboot flag (for LynxOS) */
-	unsigned long	bi_ip_addr;	/* IP Address */
-	unsigned char	bi_enetaddr[6];	/* Ethernet address */
-	unsigned short	bi_ethspeed;	/* Ethernet speed in Mbps */
-	unsigned long	bi_intfreq;	/* Internal Freq, in MHz */
-	unsigned long	bi_busfreq;	/* Bus Freq, in MHz */
-#if defined(CONFIG_CPM2)
-	unsigned long	bi_cpmfreq;	/* CPM_CLK Freq, in MHz */
-	unsigned long	bi_brgfreq;	/* BRG_CLK Freq, in MHz */
-	unsigned long	bi_sccfreq;	/* SCC_CLK Freq, in MHz */
-	unsigned long	bi_vco;		/* VCO Out from PLL, in MHz */
-#endif
-#if defined(CONFIG_PPC_MPC52xx)
-	unsigned long   bi_ipbfreq;     /* IPB Bus Freq, in MHz */
-	unsigned long   bi_pcifreq;     /* PCI Bus Freq, in MHz */
-#endif
-	unsigned long	bi_baudrate;	/* Console Baudrate */
-#if defined(CONFIG_4xx)
-	unsigned char	bi_s_version[4];	/* Version of this structure */
-	unsigned char	bi_r_version[32];	/* Version of the ROM (IBM) */
-	unsigned int	bi_procfreq;	/* CPU (Internal) Freq, in Hz */
-	unsigned int	bi_plb_busfreq;	/* PLB Bus speed, in Hz */
-	unsigned int	bi_pci_busfreq;	/* PCI Bus speed, in Hz */
-	unsigned char	bi_pci_enetaddr[6];	/* PCI Ethernet MAC address */
-#endif
-#if defined(CONFIG_HYMOD)
-	hymod_conf_t	bi_hymod_conf;	/* hymod configuration information */
-#endif
-#if defined(CONFIG_EVB64260) || defined(CONFIG_405EP) || defined(CONFIG_44x)
-	/* second onboard ethernet port */
-	unsigned char	bi_enet1addr[6];
-#endif
-#if defined(CONFIG_EVB64260) || defined(CONFIG_440GX)
-	/* third onboard ethernet ports */
-	unsigned char	bi_enet2addr[6];
-#endif
-#if defined(CONFIG_440GX)
-	/* fourth onboard ethernet ports */
-	unsigned char	bi_enet3addr[6];
-#endif
-#if defined(CONFIG_4xx)
-	unsigned int	bi_opbfreq;		/* OB clock in Hz */
-	int		bi_iic_fast[2];		/* Use fast i2c mode */
-#endif
-#if defined(CONFIG_440GX)
-	int		bi_phynum[4];		/* phy mapping */
-	int		bi_phymode[4];		/* phy mode */
-#endif
-} bd_t;
-
-#define bi_tbfreq	bi_intfreq
-
-#endif /* __ASSEMBLY__ */
-#endif	/* __ASM_PPCBOOT_H__ */
diff --git a/include/asm-ppc/prep_nvram.h b/include/asm-ppc/prep_nvram.h
deleted file mode 100644
index 6dbc36a84df..00000000000
--- a/include/asm-ppc/prep_nvram.h
+++ /dev/null
@@ -1,153 +0,0 @@
-/*
- * PreP compliant NVRAM access
- */
-
-/* Corey Minyard (minyard@acm.org) - Stolen from PReP book.   Per the
-   license I must say:
-     (C) Copyright (Corey Minyard), (1998).  All rights reserved
- */
-
-/* Structure map for NVRAM on PowerPC Reference Platform */
-/* All fields are either character/byte strings which are valid either
-  endian or they are big-endian numbers.
-
-  There are a number of Date and Time fields which are in RTC format,
-  big-endian. These are stored in UT (GMT).
-
-  For enum's: if given in hex then they are bit significant, i.e. only
-  one bit is on for each enum.
-*/
-#ifdef __KERNEL__
-#ifndef _PPC_PREP_NVRAM_H
-#define _PPC_PREP_NVRAM_H
-
-#define MAX_PREP_NVRAM 0x8000
-#define PREP_NVRAM_AS0	0x74
-#define PREP_NVRAM_AS1	0x75
-#define PREP_NVRAM_DATA	0x77
-
-#define NVSIZE 4096	/* size of NVRAM */
-#define OSAREASIZE 512	/* size of OSArea space */
-#define CONFSIZE 1024	/* guess at size of Configuration space */
-
-typedef struct _SECURITY {
-  unsigned long BootErrCnt;	    /* Count of boot password errors */
-  unsigned long ConfigErrCnt;	    /* Count of config password errors */
-  unsigned long BootErrorDT[2];	    /* Date&Time from RTC of last error in pw */
-  unsigned long ConfigErrorDT[2];   /* Date&Time from RTC of last error in pw */
-  unsigned long BootCorrectDT[2];   /* Date&Time from RTC of last correct pw */
-  unsigned long ConfigCorrectDT[2]; /* Date&Time from RTC of last correct pw */
-  unsigned long BootSetDT[2];	    /* Date&Time from RTC of last set of pw */
-  unsigned long ConfigSetDT[2];	    /* Date&Time from RTC of last set of pw */
-  unsigned char Serial[16];	    /* Box serial number */
-} SECURITY;
-
-typedef enum _OS_ID {
-  Unknown = 0,
-  Firmware = 1,
-  AIX = 2,
-  NT = 3,
-  MKOS2 = 4,
-  MKAIX = 5,
-  Taligent = 6,
-  Solaris = 7,
-  MK = 12
-} OS_ID;
-
-typedef struct _ERROR_LOG {
-  unsigned char ErrorLogEntry[40]; /* To be architected */
-} ERROR_LOG;
-
-typedef enum _BOOT_STATUS {
-  BootStarted = 0x01,
-  BootFinished = 0x02,
-  RestartStarted = 0x04,
-  RestartFinished = 0x08,
-  PowerFailStarted = 0x10,
-  PowerFailFinished = 0x20,
-  ProcessorReady = 0x40,
-  ProcessorRunning = 0x80,
-  ProcessorStart = 0x0100
-} BOOT_STATUS;
-
-typedef struct _RESTART_BLOCK {
-  unsigned short Version;
-  unsigned short Revision;
-  unsigned long ResumeReserve1[2];
-  volatile unsigned long BootStatus;
-  unsigned long CheckSum; /* Checksum of RESTART_BLOCK */
-  void * RestartAddress;
-  void * SaveAreaAddr;
-  unsigned long SaveAreaLength;
-} RESTART_BLOCK;
-
-typedef enum _OSAREA_USAGE {
-  Empty = 0,
-  Used = 1
-} OSAREA_USAGE;
-
-typedef enum _PM_MODE {
-  Suspend = 0x80, /* Part of state is in memory */
-  Normal = 0x00   /* No power management in effect */
-} PMMODE;
-
-typedef struct _HEADER {
-  unsigned short Size;       /* NVRAM size in K(1024) */
-  unsigned char Version;     /* Structure map different */
-  unsigned char Revision;    /* Structure map the same -may
-                                be new values in old fields
-                                in other words old code still works */
-  unsigned short Crc1;       /* check sum from beginning of nvram to OSArea */
-  unsigned short Crc2;       /* check sum of config */
-  unsigned char LastOS;      /* OS_ID */
-  unsigned char Endian;      /* B if big endian, L if little endian */
-  unsigned char OSAreaUsage; /* OSAREA_USAGE */
-  unsigned char PMMode;      /* Shutdown mode */
-  RESTART_BLOCK RestartBlock;
-  SECURITY Security;
-  ERROR_LOG ErrorLog[2];
-
-  /* Global Environment information */
-  void * GEAddress;
-  unsigned long GELength;
-
-  /* Date&Time from RTC of last change to Global Environment */
-  unsigned long GELastWriteDT[2];
-
-  /* Configuration information */
-  void * ConfigAddress;
-  unsigned long ConfigLength;
-
-  /* Date&Time from RTC of last change to Configuration */
-  unsigned long ConfigLastWriteDT[2];
-  unsigned long ConfigCount; /* Count of entries in Configuration */
-
-  /* OS dependent temp area */
-  void * OSAreaAddress;
-  unsigned long OSAreaLength;
-
-  /* Date&Time from RTC of last change to OSAreaArea */
-  unsigned long OSAreaLastWriteDT[2];
-} HEADER;
-
-/* Here is the whole map of the NVRAM */
-typedef struct _NVRAM_MAP {
-  HEADER Header;
-  unsigned char GEArea[NVSIZE-CONFSIZE-OSAREASIZE-sizeof(HEADER)];
-  unsigned char OSArea[OSAREASIZE];
-  unsigned char ConfigArea[CONFSIZE];
-} NVRAM_MAP;
-
-/* Routines to manipulate the NVRAM */
-void init_prep_nvram(void);
-char *prep_nvram_get_var(const char *name);
-char *prep_nvram_first_var(void);
-char *prep_nvram_next_var(char *name);
-
-/* Routines to read and write directly to the NVRAM */
-unsigned char prep_nvram_read_val(int addr);
-void prep_nvram_write_val(int           addr,
-			  unsigned char val);
-
-#endif /* _PPC_PREP_NVRAM_H */
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/prom.h b/include/asm-ppc/prom.h
deleted file mode 100644
index 71f4c996fe7..00000000000
--- a/include/asm-ppc/prom.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * Definitions for talking to the Open Firmware PROM on
- * Power Macintosh computers.
- *
- * Copyright (C) 1996 Paul Mackerras.
- */
-#ifdef __KERNEL__
-#ifndef _PPC_PROM_H
-#define _PPC_PROM_H
-
-/* This is used in arch/ppc/mm/mem_pieces.h */
-struct reg_property {
-	unsigned int address;
-	unsigned int size;
-};
-
-/*
- * These macros assist in performing the address calculations that we
- * need to do to access data when the kernel is running at an address
- * that is different from the address that the kernel is linked at.
- * The reloc_offset() function returns the difference between these
- * two addresses and the macros simplify the process of adding or
- * subtracting this offset to/from pointer values.
- */
-extern unsigned long reloc_offset(void);
-extern unsigned long add_reloc_offset(unsigned long);
-extern unsigned long sub_reloc_offset(unsigned long);
-
-#define PTRRELOC(x)	((typeof(x))add_reloc_offset((unsigned long)(x)))
-#define PTRUNRELOC(x)	((typeof(x))sub_reloc_offset((unsigned long)(x)))
-
-/*
- * Fallback definitions since we don't support OF in arch/ppc any more.
- */
-#define machine_is_compatible(x)		0
-#define of_find_compatible_node(f, t, c)	NULL
-#define of_get_property(p, n, l)		NULL
-
-#endif /* _PPC_PROM_H */
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/raven.h b/include/asm-ppc/raven.h
deleted file mode 100644
index 66f52cc0a03..00000000000
--- a/include/asm-ppc/raven.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- *  include/asm-ppc/raven.h -- Raven MPIC chip.
- *
- *  Copyright (C) 1998 Johnnie Peters
- *
- *  This file is subject to the terms and conditions of the GNU General Public
- *  License.  See the file COPYING in the main directory of this archive
- *  for more details.
- */
-
-#ifdef __KERNEL__
-#ifndef _ASMPPC_RAVEN_H
-#define _ASMPPC_RAVEN_H
-
-#define MVME2600_INT_SIO		0
-#define MVME2600_INT_FALCN_ECC_ERR	1
-#define MVME2600_INT_PCI_ETHERNET	2
-#define MVME2600_INT_PCI_SCSI		3
-#define MVME2600_INT_PCI_GRAPHICS	4
-#define MVME2600_INT_PCI_VME0		5
-#define MVME2600_INT_PCI_VME1		6
-#define MVME2600_INT_PCI_VME2		7
-#define MVME2600_INT_PCI_VME3		8
-#define MVME2600_INT_PCI_INTA		9
-#define MVME2600_INT_PCI_INTB		10
-#define MVME2600_INT_PCI_INTC 		11
-#define MVME2600_INT_PCI_INTD 		12
-#define MVME2600_INT_LM_SIG0		13
-#define MVME2600_INT_LM_SIG1		14
-
-extern struct hw_interrupt_type raven_pic;
-
-extern int raven_init(void);
-#endif /* _ASMPPC_RAVEN_H */
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/reg_booke.h b/include/asm-ppc/reg_booke.h
deleted file mode 100644
index 91e96af88bd..00000000000
--- a/include/asm-ppc/reg_booke.h
+++ /dev/null
@@ -1,443 +0,0 @@
-/*
- * Contains register definitions common to the Book E PowerPC
- * specification.  Notice that while the IBM-40x series of CPUs
- * are not true Book E PowerPCs, they borrowed a number of features
- * before Book E was finalized, and are included here as well.  Unfortunatly,
- * they sometimes used different locations than true Book E CPUs did.
- */
-#ifdef __KERNEL__
-#ifndef __ASM_PPC_REG_BOOKE_H__
-#define __ASM_PPC_REG_BOOKE_H__
-
-#ifndef __ASSEMBLY__
-/* Performance Monitor Registers */
-#define mfpmr(rn)	({unsigned int rval; \
-			asm volatile("mfpmr %0," __stringify(rn) \
-				     : "=r" (rval)); rval;})
-#define mtpmr(rn, v)	asm volatile("mtpmr " __stringify(rn) ",%0" : : "r" (v))
-#endif /* __ASSEMBLY__ */
-
-/* Freescale Book E Performance Monitor APU Registers */
-#define PMRN_PMC0	0x010	/* Performance Monitor Counter 0 */
-#define PMRN_PMC1	0x011	/* Performance Monitor Counter 1 */
-#define PMRN_PMC2	0x012	/* Performance Monitor Counter 1 */
-#define PMRN_PMC3	0x013	/* Performance Monitor Counter 1 */
-#define PMRN_PMLCA0	0x090	/* PM Local Control A0 */
-#define PMRN_PMLCA1	0x091	/* PM Local Control A1 */
-#define PMRN_PMLCA2	0x092	/* PM Local Control A2 */
-#define PMRN_PMLCA3	0x093	/* PM Local Control A3 */
-
-#define PMLCA_FC	0x80000000	/* Freeze Counter */
-#define PMLCA_FCS	0x40000000	/* Freeze in Supervisor */
-#define PMLCA_FCU	0x20000000	/* Freeze in User */
-#define PMLCA_FCM1	0x10000000	/* Freeze when PMM==1 */
-#define PMLCA_FCM0	0x08000000	/* Freeze when PMM==0 */
-#define PMLCA_CE	0x04000000	/* Condition Enable */
-
-#define PMLCA_EVENT_MASK 0x007f0000	/* Event field */
-#define PMLCA_EVENT_SHIFT	16
-
-#define PMRN_PMLCB0	0x110	/* PM Local Control B0 */
-#define PMRN_PMLCB1	0x111	/* PM Local Control B1 */
-#define PMRN_PMLCB2	0x112	/* PM Local Control B2 */
-#define PMRN_PMLCB3	0x113	/* PM Local Control B3 */
-
-#define PMLCB_THRESHMUL_MASK	0x0700	/* Threshhold Multiple Field */
-#define PMLCB_THRESHMUL_SHIFT	8
-
-#define PMLCB_THRESHOLD_MASK	0x003f	/* Threshold Field */
-#define PMLCB_THRESHOLD_SHIFT	0
-
-#define PMRN_PMGC0	0x190	/* PM Global Control 0 */
-
-#define PMGC0_FAC	0x80000000	/* Freeze all Counters */
-#define PMGC0_PMIE	0x40000000	/* Interrupt Enable */
-#define PMGC0_FCECE	0x20000000	/* Freeze countes on
-					   Enabled Condition or
-					   Event */
-
-#define PMRN_UPMC0	0x000	/* User Performance Monitor Counter 0 */
-#define PMRN_UPMC1	0x001	/* User Performance Monitor Counter 1 */
-#define PMRN_UPMC2	0x002	/* User Performance Monitor Counter 1 */
-#define PMRN_UPMC3	0x003	/* User Performance Monitor Counter 1 */
-#define PMRN_UPMLCA0	0x080	/* User PM Local Control A0 */
-#define PMRN_UPMLCA1	0x081	/* User PM Local Control A1 */
-#define PMRN_UPMLCA2	0x082	/* User PM Local Control A2 */
-#define PMRN_UPMLCA3	0x083	/* User PM Local Control A3 */
-#define PMRN_UPMLCB0	0x100	/* User PM Local Control B0 */
-#define PMRN_UPMLCB1	0x101	/* User PM Local Control B1 */
-#define PMRN_UPMLCB2	0x102	/* User PM Local Control B2 */
-#define PMRN_UPMLCB3	0x103	/* User PM Local Control B3 */
-#define PMRN_UPMGC0	0x180	/* User PM Global Control 0 */
-
-
-/* Machine State Register (MSR) Fields */
-#define MSR_UCLE	(1<<26)	/* User-mode cache lock enable */
-#define MSR_SPE		(1<<25)	/* Enable SPE */
-#define MSR_DWE		(1<<10)	/* Debug Wait Enable */
-#define MSR_UBLE	(1<<10)	/* BTB lock enable (e500) */
-#define MSR_IS		MSR_IR	/* Instruction Space */
-#define MSR_DS		MSR_DR	/* Data Space */
-#define MSR_PMM		(1<<2)	/* Performance monitor mark bit */
-
-/* Default MSR for kernel mode. */
-#if defined (CONFIG_40x)
-#define MSR_KERNEL	(MSR_ME|MSR_RI|MSR_IR|MSR_DR|MSR_CE)
-#elif defined(CONFIG_BOOKE)
-#define MSR_KERNEL	(MSR_ME|MSR_RI|MSR_CE)
-#endif
-
-/* Special Purpose Registers (SPRNs)*/
-#define SPRN_DECAR	0x036	/* Decrementer Auto Reload Register */
-#define SPRN_IVPR	0x03F	/* Interrupt Vector Prefix Register */
-#define SPRN_USPRG0	0x100	/* User Special Purpose Register General 0 */
-#define SPRN_SPRG4R	0x104	/* Special Purpose Register General 4 Read */
-#define SPRN_SPRG5R	0x105	/* Special Purpose Register General 5 Read */
-#define SPRN_SPRG6R	0x106	/* Special Purpose Register General 6 Read */
-#define SPRN_SPRG7R	0x107	/* Special Purpose Register General 7 Read */
-#define SPRN_SPRG4W	0x114	/* Special Purpose Register General 4 Write */
-#define SPRN_SPRG5W	0x115	/* Special Purpose Register General 5 Write */
-#define SPRN_SPRG6W	0x116	/* Special Purpose Register General 6 Write */
-#define SPRN_SPRG7W	0x117	/* Special Purpose Register General 7 Write */
-#define SPRN_DBCR2	0x136	/* Debug Control Register 2 */
-#define SPRN_IAC3	0x13A	/* Instruction Address Compare 3 */
-#define SPRN_IAC4	0x13B	/* Instruction Address Compare 4 */
-#define SPRN_DVC1	0x13E	/* Data Value Compare Register 1 */
-#define SPRN_DVC2	0x13F	/* Data Value Compare Register 2 */
-#define SPRN_IVOR0	0x190	/* Interrupt Vector Offset Register 0 */
-#define SPRN_IVOR1	0x191	/* Interrupt Vector Offset Register 1 */
-#define SPRN_IVOR2	0x192	/* Interrupt Vector Offset Register 2 */
-#define SPRN_IVOR3	0x193	/* Interrupt Vector Offset Register 3 */
-#define SPRN_IVOR4	0x194	/* Interrupt Vector Offset Register 4 */
-#define SPRN_IVOR5	0x195	/* Interrupt Vector Offset Register 5 */
-#define SPRN_IVOR6	0x196	/* Interrupt Vector Offset Register 6 */
-#define SPRN_IVOR7	0x197	/* Interrupt Vector Offset Register 7 */
-#define SPRN_IVOR8	0x198	/* Interrupt Vector Offset Register 8 */
-#define SPRN_IVOR9	0x199	/* Interrupt Vector Offset Register 9 */
-#define SPRN_IVOR10	0x19A	/* Interrupt Vector Offset Register 10 */
-#define SPRN_IVOR11	0x19B	/* Interrupt Vector Offset Register 11 */
-#define SPRN_IVOR12	0x19C	/* Interrupt Vector Offset Register 12 */
-#define SPRN_IVOR13	0x19D	/* Interrupt Vector Offset Register 13 */
-#define SPRN_IVOR14	0x19E	/* Interrupt Vector Offset Register 14 */
-#define SPRN_IVOR15	0x19F	/* Interrupt Vector Offset Register 15 */
-#define SPRN_SPEFSCR	0x200	/* SPE & Embedded FP Status & Control */
-#define SPRN_BBEAR	0x201	/* Branch Buffer Entry Address Register */
-#define SPRN_BBTAR	0x202	/* Branch Buffer Target Address Register */
-#define SPRN_IVOR32	0x210	/* Interrupt Vector Offset Register 32 */
-#define SPRN_IVOR33	0x211	/* Interrupt Vector Offset Register 33 */
-#define SPRN_IVOR34	0x212	/* Interrupt Vector Offset Register 34 */
-#define SPRN_IVOR35	0x213	/* Interrupt Vector Offset Register 35 */
-#define SPRN_MCSRR0	0x23A	/* Machine Check Save and Restore Register 0 */
-#define SPRN_MCSRR1	0x23B	/* Machine Check Save and Restore Register 1 */
-#define SPRN_MCSR	0x23C	/* Machine Check Status Register */
-#define SPRN_MCAR	0x23D	/* Machine Check Address Register */
-#define SPRN_DSRR0	0x23E	/* Debug Save and Restore Register 0 */
-#define SPRN_DSRR1	0x23F	/* Debug Save and Restore Register 1 */
-#define SPRN_MAS0	0x270	/* MMU Assist Register 0 */
-#define SPRN_MAS1	0x271	/* MMU Assist Register 1 */
-#define SPRN_MAS2	0x272	/* MMU Assist Register 2 */
-#define SPRN_MAS3	0x273	/* MMU Assist Register 3 */
-#define SPRN_MAS4	0x274	/* MMU Assist Register 4 */
-#define SPRN_MAS5	0x275	/* MMU Assist Register 5 */
-#define SPRN_MAS6	0x276	/* MMU Assist Register 6 */
-#define SPRN_MAS7	0x3b0	/* MMU Assist Register 7 */
-#define SPRN_PID1	0x279	/* Process ID Register 1 */
-#define SPRN_PID2	0x27A	/* Process ID Register 2 */
-#define SPRN_TLB0CFG	0x2B0	/* TLB 0 Config Register */
-#define SPRN_TLB1CFG	0x2B1	/* TLB 1 Config Register */
-#define SPRN_CCR1	0x378	/* Core Configuration Register 1 */
-#define SPRN_ZPR	0x3B0	/* Zone Protection Register (40x) */
-#define SPRN_MMUCR	0x3B2	/* MMU Control Register */
-#define SPRN_CCR0	0x3B3	/* Core Configuration Register 0 */
-#define SPRN_SGR	0x3B9	/* Storage Guarded Register */
-#define SPRN_DCWR	0x3BA	/* Data Cache Write-thru Register */
-#define SPRN_SLER	0x3BB	/* Little-endian real mode */
-#define SPRN_SU0R	0x3BC	/* "User 0" real mode (40x) */
-#define SPRN_DCMP	0x3D1	/* Data TLB Compare Register */
-#define SPRN_ICDBDR	0x3D3	/* Instruction Cache Debug Data Register */
-#define SPRN_EVPR	0x3D6	/* Exception Vector Prefix Register */
-#define SPRN_L1CSR0	0x3F2	/* L1 Cache Control and Status Register 0 */
-#define SPRN_L1CSR1	0x3F3	/* L1 Cache Control and Status Register 1 */
-#define SPRN_PIT	0x3DB	/* Programmable Interval Timer */
-#define SPRN_DCCR	0x3FA	/* Data Cache Cacheability Register */
-#define SPRN_ICCR	0x3FB	/* Instruction Cache Cacheability Register */
-#define SPRN_SVR	0x3FF	/* System Version Register */
-
-/*
- * SPRs which have conflicting definitions on true Book E versus classic,
- * or IBM 40x.
- */
-#ifdef CONFIG_BOOKE
-#define SPRN_PID	0x030	/* Process ID */
-#define SPRN_PID0	SPRN_PID/* Process ID Register 0 */
-#define SPRN_CSRR0	0x03A	/* Critical Save and Restore Register 0 */
-#define SPRN_CSRR1	0x03B	/* Critical Save and Restore Register 1 */
-#define SPRN_DEAR	0x03D	/* Data Error Address Register */
-#define SPRN_ESR	0x03E	/* Exception Syndrome Register */
-#define SPRN_PIR	0x11E	/* Processor Identification Register */
-#define SPRN_DBSR	0x130	/* Debug Status Register */
-#define SPRN_DBCR0	0x134	/* Debug Control Register 0 */
-#define SPRN_DBCR1	0x135	/* Debug Control Register 1 */
-#define SPRN_IAC1	0x138	/* Instruction Address Compare 1 */
-#define SPRN_IAC2	0x139	/* Instruction Address Compare 2 */
-#define SPRN_DAC1	0x13C	/* Data Address Compare 1 */
-#define SPRN_DAC2	0x13D	/* Data Address Compare 2 */
-#define SPRN_TSR	0x150	/* Timer Status Register */
-#define SPRN_TCR	0x154	/* Timer Control Register */
-#endif /* Book E */
-#ifdef CONFIG_40x
-#define SPRN_PID	0x3B1	/* Process ID */
-#define SPRN_DBCR1	0x3BD	/* Debug Control Register 1 */		
-#define SPRN_ESR	0x3D4	/* Exception Syndrome Register */
-#define SPRN_DEAR	0x3D5	/* Data Error Address Register */
-#define SPRN_TSR	0x3D8	/* Timer Status Register */
-#define SPRN_TCR	0x3DA	/* Timer Control Register */
-#define SPRN_SRR2	0x3DE	/* Save/Restore Register 2 */
-#define SPRN_SRR3	0x3DF	/* Save/Restore Register 3 */
-#define SPRN_DBSR	0x3F0	/* Debug Status Register */		
-#define SPRN_DBCR0	0x3F2	/* Debug Control Register 0 */
-#define SPRN_DAC1	0x3F6	/* Data Address Compare 1 */
-#define SPRN_DAC2	0x3F7	/* Data Address Compare 2 */
-#define SPRN_CSRR0	SPRN_SRR2 /* Critical Save and Restore Register 0 */
-#define SPRN_CSRR1	SPRN_SRR3 /* Critical Save and Restore Register 1 */
-#endif
-
-/* Bit definitions for CCR1. */
-#define	CCR1_DPC	0x00000100 /* Disable L1 I-Cache/D-Cache parity checking */
-#define	CCR1_TCS	0x00000080 /* Timer Clock Select */
-
-/* Bit definitions for the MCSR. */
-#ifdef CONFIG_4xx
-#define MCSR_MCS	0x80000000 /* Machine Check Summary */
-#define MCSR_IB		0x40000000 /* Instruction PLB Error */
-#define MCSR_DRB	0x20000000 /* Data Read PLB Error */
-#define MCSR_DWB	0x10000000 /* Data Write PLB Error */
-#define MCSR_TLBP	0x08000000 /* TLB Parity Error */
-#define MCSR_ICP	0x04000000 /* I-Cache Parity Error */
-#define MCSR_DCSP	0x02000000 /* D-Cache Search Parity Error */
-#define MCSR_DCFP	0x01000000 /* D-Cache Flush Parity Error */
-#define MCSR_IMPE	0x00800000 /* Imprecise Machine Check Exception */
-#endif
-
-/* Bit definitions for the DBSR. */
-/*
- * DBSR bits which have conflicting definitions on true Book E versus IBM 40x.
- */
-#ifdef CONFIG_BOOKE
-#define DBSR_IC		0x08000000	/* Instruction Completion */
-#define DBSR_BT		0x04000000	/* Branch Taken */
-#define DBSR_TIE	0x01000000	/* Trap Instruction Event */
-#define DBSR_IAC1	0x00800000	/* Instr Address Compare 1 Event */
-#define DBSR_IAC2	0x00400000	/* Instr Address Compare 2 Event */
-#define DBSR_IAC3	0x00200000	/* Instr Address Compare 3 Event */
-#define DBSR_IAC4	0x00100000	/* Instr Address Compare 4 Event */
-#define DBSR_DAC1R	0x00080000	/* Data Addr Compare 1 Read Event */
-#define DBSR_DAC1W	0x00040000	/* Data Addr Compare 1 Write Event */
-#define DBSR_DAC2R	0x00020000	/* Data Addr Compare 2 Read Event */
-#define DBSR_DAC2W	0x00010000	/* Data Addr Compare 2 Write Event */
-#endif
-#ifdef CONFIG_40x
-#define DBSR_IC		0x80000000	/* Instruction Completion */
-#define DBSR_BT		0x40000000	/* Branch taken */
-#define DBSR_TIE	0x10000000	/* Trap Instruction debug Event */
-#define DBSR_IAC1	0x04000000	/* Instruction Address Compare 1 Event */
-#define DBSR_IAC2	0x02000000	/* Instruction Address Compare 2 Event */
-#define DBSR_IAC3	0x00080000	/* Instruction Address Compare 3 Event */
-#define DBSR_IAC4	0x00040000	/* Instruction Address Compare 4 Event */
-#define DBSR_DAC1R	0x01000000	/* Data Address Compare 1 Read Event */
-#define DBSR_DAC1W	0x00800000	/* Data Address Compare 1 Write Event */
-#define DBSR_DAC2R	0x00400000	/* Data Address Compare 2 Read Event */
-#define DBSR_DAC2W	0x00200000	/* Data Address Compare 2 Write Event */
-#endif
-
-/* Bit definitions related to the ESR. */
-#define ESR_MCI		0x80000000	/* Machine Check - Instruction */
-#define ESR_IMCP	0x80000000	/* Instr. Machine Check - Protection */
-#define ESR_IMCN	0x40000000	/* Instr. Machine Check - Non-config */
-#define ESR_IMCB	0x20000000	/* Instr. Machine Check - Bus error */
-#define ESR_IMCT	0x10000000	/* Instr. Machine Check - Timeout */
-#define ESR_PIL		0x08000000	/* Program Exception - Illegal */
-#define ESR_PPR		0x04000000	/* Program Exception - Privileged */
-#define ESR_PTR		0x02000000	/* Program Exception - Trap */
-#define ESR_FP		0x01000000	/* Floating Point Operation */
-#define ESR_DST		0x00800000	/* Storage Exception - Data miss */
-#define ESR_DIZ		0x00400000	/* Storage Exception - Zone fault */
-#define ESR_ST		0x00800000	/* Store Operation */
-#define ESR_DLK		0x00200000	/* Data Cache Locking */
-#define ESR_ILK		0x00100000	/* Instr. Cache Locking */
-#define ESR_PUO		0x00040000	/* Unimplemented Operation exception */
-#define ESR_BO		0x00020000	/* Byte Ordering */
-
-/* Bit definitions related to the DBCR0. */
-#define DBCR0_EDM	0x80000000	/* External Debug Mode */
-#define DBCR0_IDM	0x40000000	/* Internal Debug Mode */
-#define DBCR0_RST	0x30000000	/* all the bits in the RST field */
-#define DBCR0_RST_SYSTEM 0x30000000	/* System Reset */
-#define DBCR0_RST_CHIP	0x20000000	/* Chip Reset */
-#define DBCR0_RST_CORE	0x10000000	/* Core Reset */
-#define DBCR0_RST_NONE	0x00000000	/* No Reset */
-#define DBCR0_IC	0x08000000	/* Instruction Completion */
-#define DBCR0_BT	0x04000000	/* Branch Taken */
-#define DBCR0_EDE	0x02000000	/* Exception Debug Event */
-#define DBCR0_TDE	0x01000000	/* TRAP Debug Event */
-#define DBCR0_IA1	0x00800000	/* Instr Addr compare 1 enable */
-#define DBCR0_IA2	0x00400000	/* Instr Addr compare 2 enable */
-#define DBCR0_IA12	0x00200000	/* Instr Addr 1-2 range enable */
-#define DBCR0_IA12X	0x00100000	/* Instr Addr 1-2 range eXclusive */
-#define DBCR0_IA3	0x00080000	/* Instr Addr compare 3 enable */
-#define DBCR0_IA4	0x00040000	/* Instr Addr compare 4 enable */
-#define DBCR0_IA34	0x00020000	/* Instr Addr 3-4 range Enable */
-#define DBCR0_IA34X	0x00010000	/* Instr Addr 3-4 range eXclusive */
-#define DBCR0_IA12T	0x00008000	/* Instr Addr 1-2 range Toggle */
-#define DBCR0_IA34T	0x00004000	/* Instr Addr 3-4 range Toggle */
-#define DBCR0_FT	0x00000001	/* Freeze Timers on debug event */
-
-/* Bit definitions related to the TCR. */
-#define TCR_WP(x)	(((x)&0x3)<<30)	/* WDT Period */
-#define TCR_WP_MASK	TCR_WP(3)
-#define WP_2_17		0		/* 2^17 clocks */
-#define WP_2_21		1		/* 2^21 clocks */
-#define WP_2_25		2		/* 2^25 clocks */
-#define WP_2_29		3		/* 2^29 clocks */
-#define TCR_WRC(x)	(((x)&0x3)<<28)	/* WDT Reset Control */
-#define TCR_WRC_MASK	TCR_WRC(3)
-#define WRC_NONE	0		/* No reset will occur */
-#define WRC_CORE	1		/* Core reset will occur */
-#define WRC_CHIP	2		/* Chip reset will occur */
-#define WRC_SYSTEM	3		/* System reset will occur */
-#define TCR_WIE		0x08000000	/* WDT Interrupt Enable */
-#define TCR_PIE		0x04000000	/* PIT Interrupt Enable */
-#define TCR_DIE		TCR_PIE		/* DEC Interrupt Enable */
-#define TCR_FP(x)	(((x)&0x3)<<24)	/* FIT Period */
-#define TCR_FP_MASK	TCR_FP(3)
-#define FP_2_9		0		/* 2^9 clocks */
-#define FP_2_13		1		/* 2^13 clocks */
-#define FP_2_17		2		/* 2^17 clocks */
-#define FP_2_21		3		/* 2^21 clocks */
-#define TCR_FIE		0x00800000	/* FIT Interrupt Enable */
-#define TCR_ARE		0x00400000	/* Auto Reload Enable */
-
-/* Bit definitions for the TSR. */
-#define TSR_ENW		0x80000000	/* Enable Next Watchdog */
-#define TSR_WIS		0x40000000	/* WDT Interrupt Status */
-#define TSR_WRS(x)	(((x)&0x3)<<28)	/* WDT Reset Status */
-#define WRS_NONE	0		/* No WDT reset occurred */
-#define WRS_CORE	1		/* WDT forced core reset */
-#define WRS_CHIP	2		/* WDT forced chip reset */
-#define WRS_SYSTEM	3		/* WDT forced system reset */
-#define TSR_PIS		0x08000000	/* PIT Interrupt Status */
-#define TSR_DIS		TSR_PIS		/* DEC Interrupt Status */
-#define TSR_FIS		0x04000000	/* FIT Interrupt Status */
-
-/* Bit definitions for the DCCR. */
-#define DCCR_NOCACHE	0		/* Noncacheable */
-#define DCCR_CACHE	1		/* Cacheable */
-
-/* Bit definitions for DCWR. */
-#define DCWR_COPY	0		/* Copy-back */
-#define DCWR_WRITE	1		/* Write-through */
-
-/* Bit definitions for ICCR. */
-#define ICCR_NOCACHE	0		/* Noncacheable */
-#define ICCR_CACHE	1		/* Cacheable */
-
-/* Bit definitions for L1CSR0. */
-#define L1CSR0_CLFC	0x00000100	/* Cache Lock Bits Flash Clear */
-#define L1CSR0_DCFI	0x00000002	/* Data Cache Flash Invalidate */
-#define L1CSR0_CFI	0x00000002	/* Cache Flash Invalidate */
-#define L1CSR0_DCE	0x00000001	/* Data Cache Enable */
-
-/* Bit definitions for L1CSR1. */
-#define L1CSR1_ICLFR	0x00000100	/* Instr Cache Lock Bits Flash Reset */
-#define L1CSR1_ICFI	0x00000002	/* Instr Cache Flash Invalidate */
-#define L1CSR1_ICE	0x00000001	/* Instr Cache Enable */
-
-/* Bit definitions for SGR. */
-#define SGR_NORMAL	0		/* Speculative fetching allowed. */
-#define SGR_GUARDED	1		/* Speculative fetching disallowed. */
-
-/* Bit definitions for SPEFSCR. */
-#define SPEFSCR_SOVH	0x80000000	/* Summary integer overflow high */
-#define SPEFSCR_OVH	0x40000000	/* Integer overflow high */
-#define SPEFSCR_FGH	0x20000000	/* Embedded FP guard bit high */
-#define SPEFSCR_FXH	0x10000000	/* Embedded FP sticky bit high */
-#define SPEFSCR_FINVH	0x08000000	/* Embedded FP invalid operation high */
-#define SPEFSCR_FDBZH	0x04000000	/* Embedded FP div by zero high */
-#define SPEFSCR_FUNFH	0x02000000	/* Embedded FP underflow high */
-#define SPEFSCR_FOVFH	0x01000000	/* Embedded FP overflow high */
-#define SPEFSCR_FINXS	0x00200000	/* Embedded FP inexact sticky */
-#define SPEFSCR_FINVS	0x00100000	/* Embedded FP invalid op. sticky */
-#define SPEFSCR_FDBZS	0x00080000	/* Embedded FP div by zero sticky */
-#define SPEFSCR_FUNFS	0x00040000	/* Embedded FP underflow sticky */
-#define SPEFSCR_FOVFS	0x00020000	/* Embedded FP overflow sticky */
-#define SPEFSCR_MODE	0x00010000	/* Embedded FP mode */
-#define SPEFSCR_SOV	0x00008000	/* Integer summary overflow */
-#define SPEFSCR_OV	0x00004000	/* Integer overflow */
-#define SPEFSCR_FG	0x00002000	/* Embedded FP guard bit */
-#define SPEFSCR_FX	0x00001000	/* Embedded FP sticky bit */
-#define SPEFSCR_FINV	0x00000800	/* Embedded FP invalid operation */
-#define SPEFSCR_FDBZ	0x00000400	/* Embedded FP div by zero */
-#define SPEFSCR_FUNF	0x00000200	/* Embedded FP underflow */
-#define SPEFSCR_FOVF	0x00000100	/* Embedded FP overflow */
-#define SPEFSCR_FINXE	0x00000040	/* Embedded FP inexact enable */
-#define SPEFSCR_FINVE	0x00000020	/* Embedded FP invalid op. enable */
-#define SPEFSCR_FDBZE	0x00000010	/* Embedded FP div by zero enable */
-#define SPEFSCR_FUNFE	0x00000008	/* Embedded FP underflow enable */
-#define SPEFSCR_FOVFE	0x00000004	/* Embedded FP overflow enable */
-#define SPEFSCR_FRMC 	0x00000003	/* Embedded FP rounding mode control */
-
-/*
- * The IBM-403 is an even more odd special case, as it is much
- * older than the IBM-405 series.  We put these down here incase someone
- * wishes to support these machines again.
- */
-#ifdef CONFIG_403GCX
-/* Special Purpose Registers (SPRNs)*/
-#define SPRN_TBHU	0x3CC	/* Time Base High User-mode */
-#define SPRN_TBLU	0x3CD	/* Time Base Low User-mode */
-#define SPRN_CDBCR	0x3D7	/* Cache Debug Control Register */
-#define SPRN_TBHI	0x3DC	/* Time Base High */
-#define SPRN_TBLO	0x3DD	/* Time Base Low */
-#define SPRN_DBCR	0x3F2	/* Debug Control Regsiter */
-#define SPRN_PBL1	0x3FC	/* Protection Bound Lower 1 */
-#define SPRN_PBL2	0x3FE	/* Protection Bound Lower 2 */
-#define SPRN_PBU1	0x3FD	/* Protection Bound Upper 1 */
-#define SPRN_PBU2	0x3FF	/* Protection Bound Upper 2 */
-
-
-/* Bit definitions for the DBCR. */
-#define DBCR_EDM	DBCR0_EDM
-#define DBCR_IDM	DBCR0_IDM
-#define DBCR_RST(x)	(((x) & 0x3) << 28)
-#define DBCR_RST_NONE	0
-#define DBCR_RST_CORE	1
-#define DBCR_RST_CHIP	2
-#define DBCR_RST_SYSTEM	3
-#define DBCR_IC		DBCR0_IC	/* Instruction Completion Debug Evnt */
-#define DBCR_BT		DBCR0_BT	/* Branch Taken Debug Event */
-#define DBCR_EDE	DBCR0_EDE	/* Exception Debug Event */
-#define DBCR_TDE	DBCR0_TDE	/* TRAP Debug Event */
-#define DBCR_FER	0x00F80000	/* First Events Remaining Mask */
-#define DBCR_FT		0x00040000	/* Freeze Timers on Debug Event */
-#define DBCR_IA1	0x00020000	/* Instr. Addr. Compare 1 Enable */
-#define DBCR_IA2	0x00010000	/* Instr. Addr. Compare 2 Enable */
-#define DBCR_D1R	0x00008000	/* Data Addr. Compare 1 Read Enable */
-#define DBCR_D1W	0x00004000	/* Data Addr. Compare 1 Write Enable */
-#define DBCR_D1S(x)	(((x) & 0x3) << 12)	/* Data Adrr. Compare 1 Size */
-#define DAC_BYTE	0
-#define DAC_HALF	1
-#define DAC_WORD	2
-#define DAC_QUAD	3
-#define DBCR_D2R	0x00000800	/* Data Addr. Compare 2 Read Enable */
-#define DBCR_D2W	0x00000400	/* Data Addr. Compare 2 Write Enable */
-#define DBCR_D2S(x)	(((x) & 0x3) << 8)	/* Data Addr. Compare 2 Size */
-#define DBCR_SBT	0x00000040	/* Second Branch Taken Debug Event */
-#define DBCR_SED	0x00000020	/* Second Exception Debug Event */
-#define DBCR_STD	0x00000010	/* Second Trap Debug Event */
-#define DBCR_SIA	0x00000008	/* Second IAC Enable */
-#define DBCR_SDA	0x00000004	/* Second DAC Enable */
-#define DBCR_JOI	0x00000002	/* JTAG Serial Outbound Int. Enable */
-#define DBCR_JII	0x00000001	/* JTAG Serial Inbound Int. Enable */
-#endif /* 403GCX */
-#endif /* __ASM_PPC_REG_BOOKE_H__ */
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/residual.h b/include/asm-ppc/residual.h
deleted file mode 100644
index 934810d2566..00000000000
--- a/include/asm-ppc/residual.h
+++ /dev/null
@@ -1,350 +0,0 @@
-/* 7/18/95                                                                    */
-/*----------------------------------------------------------------------------*/
-/*      Residual Data header definitions and prototypes                       */
-/*----------------------------------------------------------------------------*/
-
-/* Structure map for RESIDUAL on PowerPC Reference Platform                   */
-/* residual.h - Residual data structure passed in r3.                         */
-/*              Load point passed in r4 to boot image.                        */
-/* For enum's: if given in hex then they are bit significant,                 */
-/*             i.e. only one bit is on for each enum                          */
-/* Reserved fields must be filled with zeros.                                */
-
-#ifdef __KERNEL__
-#ifndef _RESIDUAL_
-#define _RESIDUAL_
-
-#ifndef __ASSEMBLY__
-
-#define MAX_CPUS 32                     /* These should be set to the maximum */
-#define MAX_MEMS 64                     /* number possible for this system.   */
-#define MAX_DEVICES 256                 /* Changing these will change the     */
-#define AVE_PNP_SIZE 32                 /* structure, hence the version of    */
-#define MAX_MEM_SEGS 64                 /* this header file.                  */
-
-/*----------------------------------------------------------------------------*/
-/*               Public structures...                                         */
-/*----------------------------------------------------------------------------*/
-
-#include <asm/pnp.h>
-
-typedef enum _L1CACHE_TYPE {
-  NoneCAC = 0,
-  SplitCAC = 1,
-  CombinedCAC = 2
-  } L1CACHE_TYPE;
-
-typedef enum _TLB_TYPE {
-  NoneTLB = 0,
-  SplitTLB = 1,
-  CombinedTLB = 2
-  } TLB_TYPE;
-
-typedef enum _FIRMWARE_SUPPORT {
-  Conventional = 0x01,
-  OpenFirmware = 0x02,
-  Diagnostics = 0x04,
-  LowDebug = 0x08,
-  Multiboot = 0x10,
-  LowClient = 0x20,
-  Hex41 = 0x40,
-  FAT = 0x80,
-  ISO9660 = 0x0100,
-  SCSI_InitiatorID_Override = 0x0200,
-  Tape_Boot = 0x0400,
-  FW_Boot_Path = 0x0800
-  } FIRMWARE_SUPPORT;
-
-typedef enum _FIRMWARE_SUPPLIERS {
-  IBMFirmware = 0x00,
-  MotoFirmware = 0x01,                  /* 7/18/95                            */
-  FirmWorks = 0x02,                     /* 10/5/95                            */
-  Bull = 0x03,                          /* 04/03/96                           */
-  } FIRMWARE_SUPPLIERS;
-
-typedef enum _ENDIAN_SWITCH_METHODS {
-  UsePort92 = 0x01,
-  UsePCIConfigA8 = 0x02,
-  UseFF001030 = 0x03,
-  } ENDIAN_SWITCH_METHODS;
-
-typedef enum _SPREAD_IO_METHODS {
-  UsePort850 = 0x00,
-/*UsePCIConfigA8 = 0x02,*/
-  } SPREAD_IO_METHODS;
-
-typedef struct _VPD {
-
-  /* Box dependent stuff */
-  unsigned char PrintableModel[32];     /* Null terminated string.
-                                           Must be of the form:
-                                           vvv,<20h>,<model designation>,<0x0>
-                                           where vvv is the vendor ID
-                                           e.g. IBM PPS MODEL 6015<0x0>       */
-  unsigned char Serial[16];             /* 12/94:
-                                           Serial Number; must be of the form:
-                                           vvv<serial number> where vvv is the
-                                           vendor ID.
-                                           e.g. IBM60151234567<20h><20h>      */
-  unsigned char Reserved[48];
-  unsigned long FirmwareSupplier;       /* See FirmwareSuppliers enum         */
-  unsigned long FirmwareSupports;       /* See FirmwareSupport enum           */
-  unsigned long NvramSize;              /* Size of nvram in bytes             */
-  unsigned long NumSIMMSlots;
-  unsigned short EndianSwitchMethod;    /* See EndianSwitchMethods enum       */
-  unsigned short SpreadIOMethod;        /* See SpreadIOMethods enum           */
-  unsigned long SmpIar;
-  unsigned long RAMErrLogOffset;        /* Heap offset to error log           */
-  unsigned long Reserved5;
-  unsigned long Reserved6;
-  unsigned long ProcessorHz;            /* Processor clock frequency in Hertz */
-  unsigned long ProcessorBusHz;         /* Processor bus clock frequency      */
-  unsigned long Reserved7;
-  unsigned long TimeBaseDivisor;        /* (Bus clocks per timebase tic)*1000 */
-  unsigned long WordWidth;              /* Word width in bits                 */
-  unsigned long PageSize;               /* Page size in bytes                 */
-  unsigned long CoherenceBlockSize;     /* Unit of transfer in/out of cache
-                                           for which coherency is maintained;
-                                           normally <= CacheLineSize.         */
-  unsigned long GranuleSize;            /* Unit of lock allocation to avoid   */
-                                        /*   false sharing of locks.          */
-
-  /* L1 Cache variables */
-  unsigned long CacheSize;              /* L1 Cache size in KB. This is the   */
-                                        /*   total size of the L1, whether    */
-                                        /*   combined or split                */
-  unsigned long CacheAttrib;            /* L1CACHE_TYPE                       */
-  unsigned long CacheAssoc;             /* L1 Cache associativity. Use this
-                                           for combined cache. If split, put
-                                           zeros here.                        */
-  unsigned long CacheLineSize;          /* L1 Cache line size in bytes. Use
-                                           for combined cache. If split, put
-                                           zeros here.                        */
-  /* For split L1 Cache: (= combined if combined cache) */
-  unsigned long I_CacheSize;
-  unsigned long I_CacheAssoc;
-  unsigned long I_CacheLineSize;
-  unsigned long D_CacheSize;
-  unsigned long D_CacheAssoc;
-  unsigned long D_CacheLineSize;
-
-  /* Translation Lookaside Buffer variables */
-  unsigned long TLBSize;                /* Total number of TLBs on the system */
-  unsigned long TLBAttrib;              /* Combined I+D or split TLB          */
-  unsigned long TLBAssoc;               /* TLB Associativity. Use this for
-                                           combined TLB. If split, put zeros
-                                           here.                              */
-  /* For split TLB: (= combined if combined TLB) */
-  unsigned long I_TLBSize;
-  unsigned long I_TLBAssoc;
-  unsigned long D_TLBSize;
-  unsigned long D_TLBAssoc;
-
-  unsigned long ExtendedVPD;            /* Offset to extended VPD area;
-                                           null if unused                     */
-  } VPD;
-
-typedef enum _DEVICE_FLAGS {
-  Enabled = 0x4000,                     /* 1 - PCI device is enabled          */
-  Integrated = 0x2000,
-  Failed = 0x1000,                      /* 1 - device failed POST code tests  */
-  Static = 0x0800,                      /* 0 - dynamically configurable
-                                           1 - static                         */
-  Dock = 0x0400,                        /* 0 - not a docking station device
-                                           1 - is a docking station device    */
-  Boot = 0x0200,                        /* 0 - device cannot be used for BOOT
-                                           1 - can be a BOOT device           */
-  Configurable = 0x0100,                /* 1 - device is configurable         */
-  Disableable = 0x80,                   /* 1 - device can be disabled         */
-  PowerManaged = 0x40,                  /* 0 - not managed; 1 - managed       */
-  ReadOnly = 0x20,                      /* 1 - device is read only            */
-  Removable = 0x10,                     /* 1 - device is removable            */
-  ConsoleIn = 0x08,
-  ConsoleOut = 0x04,
-  Input = 0x02,
-  Output = 0x01
-  } DEVICE_FLAGS;
-
-typedef enum _BUS_ID {
-  ISADEVICE = 0x01,
-  EISADEVICE = 0x02,
-  PCIDEVICE = 0x04,
-  PCMCIADEVICE = 0x08,
-  PNPISADEVICE = 0x10,
-  MCADEVICE = 0x20,
-  MXDEVICE = 0x40,                      /* Devices on mezzanine bus           */
-  PROCESSORDEVICE = 0x80,               /* Devices on processor bus           */
-  VMEDEVICE = 0x100,
-  } BUS_ID;
-
-typedef struct _DEVICE_ID {
-  unsigned long BusId;                  /* See BUS_ID enum above              */
-  unsigned long DevId;                  /* Big Endian format                  */
-  unsigned long SerialNum;              /* For multiple usage of a single
-                                           DevId                              */
-  unsigned long Flags;                  /* See DEVICE_FLAGS enum above        */
-  unsigned char BaseType;               /* See pnp.h for bit definitions      */
-  unsigned char SubType;                /* See pnp.h for bit definitions      */
-  unsigned char Interface;              /* See pnp.h for bit definitions      */
-  unsigned char Spare;
-  } DEVICE_ID;
-
-typedef union _BUS_ACCESS {
-  struct _PnPAccess{
-    unsigned char CSN;
-    unsigned char LogicalDevNumber;
-    unsigned short ReadDataPort;
-    } PnPAccess;
-  struct _ISAAccess{
-    unsigned char SlotNumber;           /* ISA Slot Number generally not
-                                           available; 0 if unknown            */
-    unsigned char LogicalDevNumber;
-    unsigned short ISAReserved;
-    } ISAAccess;
-  struct _MCAAccess{
-    unsigned char SlotNumber;
-    unsigned char LogicalDevNumber;
-    unsigned short MCAReserved;
-    } MCAAccess;
-  struct _PCMCIAAccess{
-    unsigned char SlotNumber;
-    unsigned char LogicalDevNumber;
-    unsigned short PCMCIAReserved;
-    } PCMCIAAccess;
-  struct _EISAAccess{
-    unsigned char SlotNumber;
-    unsigned char FunctionNumber;
-    unsigned short EISAReserved;
-    } EISAAccess;
-  struct _PCIAccess{
-    unsigned char BusNumber;
-    unsigned char DevFuncNumber;
-    unsigned short PCIReserved;
-    } PCIAccess;
-  struct _ProcBusAccess{
-    unsigned char BusNumber;
-    unsigned char BUID;
-    unsigned short ProcBusReserved;
-    } ProcBusAccess;
-  } BUS_ACCESS;
-
-/* Per logical device information */
-typedef struct _PPC_DEVICE {
-  DEVICE_ID DeviceId;
-  BUS_ACCESS BusAccess;
-
-  /* The following three are offsets into the DevicePnPHeap */
-  /* All are in PnP compressed format                       */
-  unsigned long AllocatedOffset;        /* Allocated resource description     */
-  unsigned long PossibleOffset;         /* Possible resource description      */
-  unsigned long CompatibleOffset;       /* Compatible device identifiers      */
-  } PPC_DEVICE;
-
-typedef enum _CPU_STATE {
-  CPU_GOOD = 0,                         /* CPU is present, and active         */
-  CPU_GOOD_FW = 1,                      /* CPU is present, and in firmware    */
-  CPU_OFF = 2,                          /* CPU is present, but inactive       */
-  CPU_FAILED = 3,                       /* CPU is present, but failed POST    */
-  CPU_NOT_PRESENT = 255                 /* CPU not present                    */
-  } CPU_STATE;
-
-typedef struct _PPC_CPU {
-  unsigned long CpuType;                /* Result of mfspr from Processor
-                                           Version Register (PVR).
-                                           PVR(0-15) = Version (e.g. 601)
-                                           PVR(16-31 = EC Level               */
-  unsigned char CpuNumber;              /* CPU Number for this processor      */
-  unsigned char CpuState;               /* CPU State, see CPU_STATE enum      */
-  unsigned short Reserved;
-  } PPC_CPU;
-
-typedef struct _PPC_MEM {
-  unsigned long SIMMSize;               /* 0 - absent or bad
-                                           8M, 32M (in MB)                    */
-  } PPC_MEM;
-
-typedef enum _MEM_USAGE {
-  Other = 0x8000,
-  ResumeBlock = 0x4000,                 /* for use by power management        */
-  SystemROM = 0x2000,                   /* Flash memory (populated)           */
-  UnPopSystemROM = 0x1000,              /* Unpopulated part of SystemROM area */
-  IOMemory = 0x0800,
-  SystemIO = 0x0400,
-  SystemRegs = 0x0200,
-  PCIAddr = 0x0100,
-  PCIConfig = 0x80,
-  ISAAddr = 0x40,
-  Unpopulated = 0x20,                   /* Unpopulated part of System Memory  */
-  Free = 0x10,                          /* Free part of System Memory         */
-  BootImage = 0x08,                     /* BootImage part of System Memory    */
-  FirmwareCode = 0x04,                  /* FirmwareCode part of System Memory */
-  FirmwareHeap = 0x02,                  /* FirmwareHeap part of System Memory */
-  FirmwareStack = 0x01                  /* FirmwareStack part of System Memory*/
-  } MEM_USAGE;
-
-typedef struct _MEM_MAP {
-  unsigned long Usage;                  /* See MEM_USAGE above                */
-  unsigned long BasePage;               /* Page number measured in 4KB pages  */
-  unsigned long PageCount;              /* Page count measured in 4KB pages   */
-  } MEM_MAP;
-
-typedef struct _RESIDUAL {
-  unsigned long ResidualLength;         /* Length of Residual                 */
-  unsigned char Version;                /* of this data structure             */
-  unsigned char Revision;               /* of this data structure             */
-  unsigned short EC;                    /* of this data structure             */
-  /* VPD */
-  VPD VitalProductData;
-  /* CPU */
-  unsigned short MaxNumCpus;            /* Max CPUs in this system            */
-  unsigned short ActualNumCpus;         /* ActualNumCpus < MaxNumCpus means   */
-                                        /* that there are unpopulated or      */
-                                        /* otherwise unusable cpu locations   */
-  PPC_CPU Cpus[MAX_CPUS];
-  /* Memory */
-  unsigned long TotalMemory;            /* Total amount of memory installed   */
-  unsigned long GoodMemory;             /* Total amount of good memory        */
-  unsigned long ActualNumMemSegs;
-  MEM_MAP Segs[MAX_MEM_SEGS];
-  unsigned long ActualNumMemories;
-  PPC_MEM Memories[MAX_MEMS];
-  /* Devices */
-  unsigned long ActualNumDevices;
-  PPC_DEVICE Devices[MAX_DEVICES];
-  unsigned char DevicePnPHeap[2*MAX_DEVICES*AVE_PNP_SIZE];
-  } RESIDUAL;
-
-
-/*
- * Forward declaration - we can't include <linux/pci.h> because it
- * breaks the boot loader
- */
-struct pci_dev;
-
-extern RESIDUAL *res;
-extern void print_residual_device_info(void);
-extern PPC_DEVICE *residual_find_device(unsigned long BusMask,
-					unsigned char * DevID, int BaseType,
-					int SubType, int Interface, int n);
-extern int residual_pcidev_irq(struct pci_dev *dev);
-extern void residual_irq_mask(char *irq_edge_mask_lo, char *irq_edge_mask_hi);
-extern unsigned int residual_isapic_addr(void);
-extern PnP_TAG_PACKET *PnP_find_packet(unsigned char *p, unsigned packet_tag,
-				       int n);
-extern PnP_TAG_PACKET *PnP_find_small_vendor_packet(unsigned char *p,
-						    unsigned packet_type,
-						    int n);
-extern PnP_TAG_PACKET *PnP_find_large_vendor_packet(unsigned char *p,
-						    unsigned packet_type,
-						    int n);
-
-#ifdef CONFIG_PREP_RESIDUAL
-#define have_residual_data	(res && res->ResidualLength)
-#else
-#define have_residual_data	0
-#endif
-
-#endif /* __ASSEMBLY__ */
-#endif  /* ndef _RESIDUAL_ */
-
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/rtc.h b/include/asm-ppc/rtc.h
deleted file mode 100644
index 6025b46d0a2..00000000000
--- a/include/asm-ppc/rtc.h
+++ /dev/null
@@ -1,95 +0,0 @@
-/*
- * include/asm-ppc/rtc.h
- *
- * Author: Tom Rini <trini@mvista.com>
- *
- * 2002 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- *
- * Based on:
- * include/asm-m68k/rtc.h
- *
- * Copyright Richard Zidlicky
- * implementation details for genrtc/q40rtc driver
- *
- * And the old drivers/macintosh/rtc.c which was heavily based on:
- * Linux/SPARC Real Time Clock Driver
- * Copyright (C) 1996 Thomas K. Dyas (tdyas@eden.rutgers.edu)
- *
- * With additional work by Paul Mackerras and Franz Sirl.
- */
-
-#ifndef __ASM_RTC_H__
-#define __ASM_RTC_H__
-
-#ifdef __KERNEL__
-
-#include <linux/rtc.h>
-
-#include <asm/machdep.h>
-#include <asm/time.h>
-
-#define RTC_PIE 0x40		/* periodic interrupt enable */
-#define RTC_AIE 0x20		/* alarm interrupt enable */
-#define RTC_UIE 0x10		/* update-finished interrupt enable */
-
-/* some dummy definitions */
-#define RTC_BATT_BAD 0x100	/* battery bad */
-#define RTC_SQWE 0x08		/* enable square-wave output */
-#define RTC_DM_BINARY 0x04	/* all time/date values are BCD if clear */
-#define RTC_24H 0x02		/* 24 hour mode - else hours bit 7 means pm */
-#define RTC_DST_EN 0x01	        /* auto switch DST - works f. USA only */
-
-static inline unsigned int get_rtc_time(struct rtc_time *time)
-{
-	if (ppc_md.get_rtc_time) {
-		unsigned long nowtime;
-
-		nowtime = (ppc_md.get_rtc_time)();
-
-		to_tm(nowtime, time);
-
-		time->tm_year -= 1900;
-		time->tm_mon -= 1; /* Make sure userland has a 0-based month */
-	}
-	return RTC_24H;
-}
-
-/* Set the current date and time in the real time clock. */
-static inline int set_rtc_time(struct rtc_time *time)
-{
-	if (ppc_md.get_rtc_time) {
-		unsigned long nowtime;
-
-		nowtime = mktime(time->tm_year+1900, time->tm_mon+1,
-				time->tm_mday, time->tm_hour, time->tm_min,
-				time->tm_sec);
-
-		(ppc_md.set_rtc_time)(nowtime);
-
-		return 0;
-	} else
-		return -EINVAL;
-}
-
-static inline unsigned int get_rtc_ss(void)
-{
-	struct rtc_time h;
-
-	get_rtc_time(&h);
-	return h.tm_sec;
-}
-
-static inline int get_rtc_pll(struct rtc_pll_info *pll)
-{
-	return -EINVAL;
-}
-static inline int set_rtc_pll(struct rtc_pll_info *pll)
-{
-	return -EINVAL;
-}
-
-#endif /* __KERNEL__ */
-#endif /* __ASM_RTC_H__ */
diff --git a/include/asm-ppc/serial.h b/include/asm-ppc/serial.h
deleted file mode 100644
index d35ed10315b..00000000000
--- a/include/asm-ppc/serial.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * include/asm-ppc/serial.h
- */
-
-#ifdef __KERNEL__
-#ifndef __ASM_SERIAL_H__
-#define __ASM_SERIAL_H__
-
-
-#if defined(CONFIG_EV64260)
-#include <platforms/ev64260.h>
-#elif defined(CONFIG_CHESTNUT)
-#include <platforms/chestnut.h>
-#elif defined(CONFIG_POWERPMC250)
-#include <platforms/powerpmc250.h>
-#elif defined(CONFIG_LOPEC)
-#include <platforms/lopec.h>
-#elif defined(CONFIG_MVME5100)
-#include <platforms/mvme5100.h>
-#elif defined(CONFIG_PAL4)
-#include <platforms/pal4_serial.h>
-#elif defined(CONFIG_PRPMC750)
-#include <platforms/prpmc750.h>
-#elif defined(CONFIG_PRPMC800)
-#include <platforms/prpmc800.h>
-#elif defined(CONFIG_SANDPOINT)
-#include <platforms/sandpoint.h>
-#elif defined(CONFIG_SPRUCE)
-#include <platforms/spruce.h>
-#elif defined(CONFIG_4xx)
-#include <asm/ibm4xx.h>
-#elif defined(CONFIG_RADSTONE_PPC7D)
-#include <platforms/radstone_ppc7d.h>
-#else
-
-/*
- * XXX Assume it has PC-style ISA serial ports - true for PReP at least.
- */
-#include <asm/pc_serial.h>
-
-#endif /* !CONFIG_GEMINI and others */
-#endif /* __ASM_SERIAL_H__ */
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/smp.h b/include/asm-ppc/smp.h
deleted file mode 100644
index e75791ea33a..00000000000
--- a/include/asm-ppc/smp.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/* smp.h: PPC specific SMP stuff.
- *
- * Original was a copy of sparc smp.h.  Now heavily modified
- * for PPC.
- *
- * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
- * Copyright (C) 1996-2001 Cort Dougan <cort@fsmlabs.com>
- */
-#ifdef __KERNEL__
-#ifndef _PPC_SMP_H
-#define _PPC_SMP_H
-
-#include <linux/kernel.h>
-#include <linux/bitops.h>
-#include <linux/errno.h>
-#include <linux/cpumask.h>
-#include <linux/threads.h>
-
-#ifdef CONFIG_SMP
-
-#ifndef __ASSEMBLY__
-
-struct cpuinfo_PPC {
-	unsigned long loops_per_jiffy;
-	unsigned long pvr;
-	unsigned long *pgd_cache;
-	unsigned long *pte_cache;
-	unsigned long pgtable_cache_sz;
-};
-
-extern struct cpuinfo_PPC cpu_data[];
-extern cpumask_t cpu_online_map;
-extern cpumask_t cpu_possible_map;
-extern unsigned long smp_proc_in_lock[];
-extern volatile unsigned long cpu_callin_map[];
-extern int smp_tb_synchronized;
-extern struct smp_ops_t *smp_ops;
-
-extern void smp_send_tlb_invalidate(int);
-extern void smp_send_xmon_break(int cpu);
-struct pt_regs;
-extern void smp_message_recv(int);
-
-extern int __cpu_disable(void);
-extern void __cpu_die(unsigned int cpu);
-extern void cpu_die(void) __attribute__((noreturn));
-
-#define raw_smp_processor_id()	(current_thread_info()->cpu)
-
-extern int __cpu_up(unsigned int cpu);
-
-extern int smp_hw_index[];
-#define hard_smp_processor_id() 	(smp_hw_index[smp_processor_id()])
-#define get_hard_smp_processor_id(cpu)	(smp_hw_index[(cpu)])
-#define set_hard_smp_processor_id(cpu, phys)\
-					(smp_hw_index[(cpu)] = (phys))
- 
-#endif /* __ASSEMBLY__ */
-
-#else /* !(CONFIG_SMP) */
-
-static inline void cpu_die(void) { }
-#define get_hard_smp_processor_id(cpu) 0
-#define set_hard_smp_processor_id(cpu, phys)
-#define hard_smp_processor_id() 0
-
-#endif /* !(CONFIG_SMP) */
-
-#ifndef __ASSEMBLY__
-extern int boot_cpuid;
-extern int boot_cpuid_phys;
-#endif
-
-#endif /* !(_PPC_SMP_H) */
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/spinlock.h b/include/asm-ppc/spinlock.h
deleted file mode 100644
index fccaf5531e5..00000000000
--- a/include/asm-ppc/spinlock.h
+++ /dev/null
@@ -1,168 +0,0 @@
-#ifndef __ASM_SPINLOCK_H
-#define __ASM_SPINLOCK_H
-
-#include <asm/system.h>
-
-/*
- * Simple spin lock operations.
- *
- * (the type definitions are in asm/raw_spinlock_types.h)
- */
-
-#define __raw_spin_is_locked(x)		((x)->slock != 0)
-#define __raw_spin_unlock_wait(lock) \
-	do { while (__raw_spin_is_locked(lock)) cpu_relax(); } while (0)
-#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
-
-static inline void __raw_spin_lock(raw_spinlock_t *lock)
-{
-	unsigned long tmp;
-
-	__asm__ __volatile__(
-	"b	1f		# __raw_spin_lock\n\
-2:	lwzx	%0,0,%1\n\
-	cmpwi	0,%0,0\n\
-	bne+	2b\n\
-1:	lwarx	%0,0,%1\n\
-	cmpwi	0,%0,0\n\
-	bne-	2b\n"
-	PPC405_ERR77(0,%1)
-"	stwcx.	%2,0,%1\n\
-	bne-	2b\n\
-	isync"
-	: "=&r"(tmp)
-	: "r"(&lock->slock), "r"(1)
-	: "cr0", "memory");
-}
-
-static inline void __raw_spin_unlock(raw_spinlock_t *lock)
-{
-	__asm__ __volatile__("eieio	# __raw_spin_unlock": : :"memory");
-	lock->slock = 0;
-}
-
-#define __raw_spin_trylock(l) (!test_and_set_bit(0,(volatile unsigned long *)(&(l)->slock)))
-
-/*
- * Read-write spinlocks, allowing multiple readers
- * but only one writer.
- *
- * NOTE! it is quite common to have readers in interrupts
- * but no interrupt writers. For those circumstances we
- * can "mix" irq-safe locks - any writer needs to get a
- * irq-safe write-lock, but readers can get non-irqsafe
- * read-locks.
- */
-
-#define __raw_read_can_lock(rw)	((rw)->lock >= 0)
-#define __raw_write_can_lock(rw)	(!(rw)->lock)
-
-static __inline__ int __raw_read_trylock(raw_rwlock_t *rw)
-{
-	signed int tmp;
-
-	__asm__ __volatile__(
-"2:	lwarx	%0,0,%1		# read_trylock\n\
-	addic.	%0,%0,1\n\
-	ble-	1f\n"
-	PPC405_ERR77(0,%1)
-"	stwcx.	%0,0,%1\n\
-	bne-	2b\n\
-	isync\n\
-1:"
-	: "=&r"(tmp)
-	: "r"(&rw->lock)
-	: "cr0", "memory");
-
-	return tmp > 0;
-}
-
-static __inline__ void __raw_read_lock(raw_rwlock_t *rw)
-{
-	signed int tmp;
-
-	__asm__ __volatile__(
-	"b	2f		# read_lock\n\
-1:	lwzx	%0,0,%1\n\
-	cmpwi	0,%0,0\n\
-	blt+	1b\n\
-2:	lwarx	%0,0,%1\n\
-	addic.	%0,%0,1\n\
-	ble-	1b\n"
-	PPC405_ERR77(0,%1)
-"	stwcx.	%0,0,%1\n\
-	bne-	2b\n\
-	isync"
-	: "=&r"(tmp)
-	: "r"(&rw->lock)
-	: "cr0", "memory");
-}
-
-static __inline__ void __raw_read_unlock(raw_rwlock_t *rw)
-{
-	signed int tmp;
-
-	__asm__ __volatile__(
-	"eieio			# read_unlock\n\
-1:	lwarx	%0,0,%1\n\
-	addic	%0,%0,-1\n"
-	PPC405_ERR77(0,%1)
-"	stwcx.	%0,0,%1\n\
-	bne-	1b"
-	: "=&r"(tmp)
-	: "r"(&rw->lock)
-	: "cr0", "memory");
-}
-
-static __inline__ int __raw_write_trylock(raw_rwlock_t *rw)
-{
-	signed int tmp;
-
-	__asm__ __volatile__(
-"2:	lwarx	%0,0,%1		# write_trylock\n\
-	cmpwi	0,%0,0\n\
-	bne-	1f\n"
-	PPC405_ERR77(0,%1)
-"	stwcx.	%2,0,%1\n\
-	bne-	2b\n\
-	isync\n\
-1:"
-	: "=&r"(tmp)
-	: "r"(&rw->lock), "r"(-1)
-	: "cr0", "memory");
-
-	return tmp == 0;
-}
-
-static __inline__ void __raw_write_lock(raw_rwlock_t *rw)
-{
-	signed int tmp;
-
-	__asm__ __volatile__(
-	"b	2f		# write_lock\n\
-1:  	lwzx	%0,0,%1\n\
-	cmpwi	0,%0,0\n\
-	bne+	1b\n\
-2:	lwarx	%0,0,%1\n\
-	cmpwi	0,%0,0\n\
-	bne-	1b\n"
-	PPC405_ERR77(0,%1)
-"	stwcx.	%2,0,%1\n\
-	bne-	2b\n\
-	isync"
-	: "=&r"(tmp)
-	: "r"(&rw->lock), "r"(-1)
-	: "cr0", "memory");
-}
-
-static __inline__ void __raw_write_unlock(raw_rwlock_t *rw)
-{
-	__asm__ __volatile__("eieio		# write_unlock": : :"memory");
-	rw->lock = 0;
-}
-
-#define _raw_spin_relax(lock)	cpu_relax()
-#define _raw_read_relax(lock)	cpu_relax()
-#define _raw_write_relax(lock)	cpu_relax()
-
-#endif /* __ASM_SPINLOCK_H */
diff --git a/include/asm-ppc/suspend.h b/include/asm-ppc/suspend.h
deleted file mode 100644
index 3df9f32bd83..00000000000
--- a/include/asm-ppc/suspend.h
+++ /dev/null
@@ -1,12 +0,0 @@
-static inline int arch_prepare_suspend(void)
-{
-	return 0;
-}
-
-static inline void save_processor_state(void)
-{
-}
-
-static inline void restore_processor_state(void)
-{
-}
diff --git a/include/asm-ppc/system.h b/include/asm-ppc/system.h
deleted file mode 100644
index 70ebd333c55..00000000000
--- a/include/asm-ppc/system.h
+++ /dev/null
@@ -1,289 +0,0 @@
-/*
- * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
- */
-#ifndef __PPC_SYSTEM_H
-#define __PPC_SYSTEM_H
-
-#include <linux/kernel.h>
-
-#include <asm/hw_irq.h>
-
-/*
- * Memory barrier.
- * The sync instruction guarantees that all memory accesses initiated
- * by this processor have been performed (with respect to all other
- * mechanisms that access memory).  The eieio instruction is a barrier
- * providing an ordering (separately) for (a) cacheable stores and (b)
- * loads and stores to non-cacheable memory (e.g. I/O devices).
- *
- * mb() prevents loads and stores being reordered across this point.
- * rmb() prevents loads being reordered across this point.
- * wmb() prevents stores being reordered across this point.
- * read_barrier_depends() prevents data-dependent loads being reordered
- *	across this point (nop on PPC).
- *
- * We can use the eieio instruction for wmb, but since it doesn't
- * give any ordering guarantees about loads, we have to use the
- * stronger but slower sync instruction for mb and rmb.
- */
-#define mb()  __asm__ __volatile__ ("sync" : : : "memory")
-#define rmb()  __asm__ __volatile__ ("sync" : : : "memory")
-#define wmb()  __asm__ __volatile__ ("eieio" : : : "memory")
-#define read_barrier_depends()  do { } while(0)
-
-#define set_mb(var, value)	do { var = value; mb(); } while (0)
-
-#define AT_VECTOR_SIZE_ARCH 6 /* entries in ARCH_DLINFO */
-#ifdef CONFIG_SMP
-#define smp_mb()	mb()
-#define smp_rmb()	rmb()
-#define smp_wmb()	__asm__ __volatile__ ("eieio" : : : "memory")
-#define smp_read_barrier_depends()	read_barrier_depends()
-#else
-#define smp_mb()	barrier()
-#define smp_rmb()	barrier()
-#define smp_wmb()	barrier()
-#define smp_read_barrier_depends()	do { } while(0)
-#endif /* CONFIG_SMP */
-
-#ifdef __KERNEL__
-struct task_struct;
-struct pt_regs;
-
-extern void print_backtrace(unsigned long *);
-extern void show_regs(struct pt_regs * regs);
-extern void flush_instruction_cache(void);
-extern void hard_reset_now(void);
-extern void poweroff_now(void);
-extern int set_dabr(unsigned long dabr);
-#ifdef CONFIG_6xx
-extern long _get_L2CR(void);
-extern long _get_L3CR(void);
-extern void _set_L2CR(unsigned long);
-extern void _set_L3CR(unsigned long);
-#else
-#define _get_L2CR()	0L
-#define _get_L3CR()	0L
-#define _set_L2CR(val)	do { } while(0)
-#define _set_L3CR(val)	do { } while(0)
-#endif
-extern void via_cuda_init(void);
-extern void pmac_nvram_init(void);
-extern void chrp_nvram_init(void);
-extern void read_rtc_time(void);
-extern void pmac_find_display(void);
-extern void giveup_fpu(struct task_struct *);
-extern void disable_kernel_fp(void);
-extern void enable_kernel_fp(void);
-extern void flush_fp_to_thread(struct task_struct *);
-extern void enable_kernel_altivec(void);
-extern void giveup_altivec(struct task_struct *);
-extern void load_up_altivec(struct task_struct *);
-extern int emulate_altivec(struct pt_regs *);
-extern void giveup_spe(struct task_struct *);
-extern void load_up_spe(struct task_struct *);
-extern int fix_alignment(struct pt_regs *);
-extern void cvt_fd(float *from, double *to, struct thread_struct *thread);
-extern void cvt_df(double *from, float *to, struct thread_struct *thread);
-
-#ifndef CONFIG_SMP
-extern void discard_lazy_cpu_state(void);
-#else
-static inline void discard_lazy_cpu_state(void)
-{
-}
-#endif
-
-#ifdef CONFIG_ALTIVEC
-extern void flush_altivec_to_thread(struct task_struct *);
-#else
-static inline void flush_altivec_to_thread(struct task_struct *t)
-{
-}
-#endif
-
-#ifdef CONFIG_SPE
-extern void flush_spe_to_thread(struct task_struct *);
-#else
-static inline void flush_spe_to_thread(struct task_struct *t)
-{
-}
-#endif
-
-extern int call_rtas(const char *, int, int, unsigned long *, ...);
-extern void cacheable_memzero(void *p, unsigned int nb);
-extern void *cacheable_memcpy(void *, const void *, unsigned int);
-extern int do_page_fault(struct pt_regs *, unsigned long, unsigned long);
-extern void bad_page_fault(struct pt_regs *, unsigned long, int);
-extern int die(const char *, struct pt_regs *, long);
-extern void _exception(int, struct pt_regs *, int, unsigned long);
-void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
-
-#ifdef CONFIG_BOOKE_WDT
-extern u32 booke_wdt_enabled;
-extern u32 booke_wdt_period;
-#endif /* CONFIG_BOOKE_WDT */
-
-struct device_node;
-extern void note_scsi_host(struct device_node *, void *);
-
-extern struct task_struct *__switch_to(struct task_struct *,
-	struct task_struct *);
-#define switch_to(prev, next, last)	((last) = __switch_to((prev), (next)))
-
-struct thread_struct;
-extern struct task_struct *_switch(struct thread_struct *prev,
-				   struct thread_struct *next);
-
-extern unsigned int rtas_data;
-
-static __inline__ unsigned long
-xchg_u32(volatile void *p, unsigned long val)
-{
-	unsigned long prev;
-
-	__asm__ __volatile__ ("\n\
-1:	lwarx	%0,0,%2 \n"
-	PPC405_ERR77(0,%2)
-"	stwcx.	%3,0,%2 \n\
-	bne-	1b"
-	: "=&r" (prev), "=m" (*(volatile unsigned long *)p)
-	: "r" (p), "r" (val), "m" (*(volatile unsigned long *)p)
-	: "cc", "memory");
-
-	return prev;
-}
-
-/*
- * This function doesn't exist, so you'll get a linker error
- * if something tries to do an invalid xchg().
- */
-extern void __xchg_called_with_bad_pointer(void);
-
-#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
-
-static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size)
-{
-	switch (size) {
-	case 4:
-		return (unsigned long) xchg_u32(ptr, x);
-#if 0	/* xchg_u64 doesn't exist on 32-bit PPC */
-	case 8:
-		return (unsigned long) xchg_u64(ptr, x);
-#endif /* 0 */
-	}
-	__xchg_called_with_bad_pointer();
-	return x;
-
-
-}
-
-static inline void * xchg_ptr(void * m, void * val)
-{
-	return (void *) xchg_u32(m, (unsigned long) val);
-}
-
-
-#define __HAVE_ARCH_CMPXCHG	1
-
-static __inline__ unsigned long
-__cmpxchg_u32(volatile unsigned int *p, unsigned int old, unsigned int new)
-{
-	unsigned int prev;
-
-	__asm__ __volatile__ ("\n\
-1:	lwarx	%0,0,%2 \n\
-	cmpw	0,%0,%3 \n\
-	bne	2f \n"
-	PPC405_ERR77(0,%2)
-"	stwcx.	%4,0,%2 \n\
-	bne-	1b\n"
-#ifdef CONFIG_SMP
-"	sync\n"
-#endif /* CONFIG_SMP */
-"2:"
-	: "=&r" (prev), "=m" (*p)
-	: "r" (p), "r" (old), "r" (new), "m" (*p)
-	: "cc", "memory");
-
-	return prev;
-}
-
-static inline unsigned long
-__cmpxchg_u32_local(volatile unsigned int *p, unsigned int old,
-	unsigned int new)
-{
-	unsigned int prev;
-
-	__asm__ __volatile__ ("\n\
-1:	lwarx	%0,0,%2 \n\
-	cmpw	0,%0,%3 \n\
-	bne	2f \n"
-	PPC405_ERR77(0,%2)
-"	stwcx.	%4,0,%2 \n\
-	bne-	1b\n"
-"2:"
-	: "=&r" (prev), "=m" (*p)
-	: "r" (p), "r" (old), "r" (new), "m" (*p)
-	: "cc", "memory");
-
-	return prev;
-}
-
-/* This function doesn't exist, so you'll get a linker error
-   if something tries to do an invalid cmpxchg().  */
-extern void __cmpxchg_called_with_bad_pointer(void);
-
-static __inline__ unsigned long
-__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new,
-	unsigned int size)
-{
-	switch (size) {
-	case 4:
-		return __cmpxchg_u32(ptr, old, new);
-#if 0	/* we don't have __cmpxchg_u64 on 32-bit PPC */
-	case 8:
-		return __cmpxchg_u64(ptr, old, new);
-#endif /* 0 */
-	}
-	__cmpxchg_called_with_bad_pointer();
-	return old;
-}
-
-#define cmpxchg(ptr, o, n)						 \
-  ({									 \
-     __typeof__(*(ptr)) _o_ = (o);					 \
-     __typeof__(*(ptr)) _n_ = (n);					 \
-     (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_,		 \
-				    (unsigned long)_n_, sizeof(*(ptr))); \
-  })
-
-#include <asm-generic/cmpxchg-local.h>
-
-static inline unsigned long __cmpxchg_local(volatile void *ptr,
-				      unsigned long old,
-				      unsigned long new, int size)
-{
-	switch (size) {
-	case 4:
-		return __cmpxchg_u32_local(ptr, old, new);
-	default:
-		return __cmpxchg_local_generic(ptr, old, new, size);
-	}
-
-	return old;
-}
-
-/*
- * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
- * them available.
- */
-#define cmpxchg_local(ptr, o, n)				  	\
-	((__typeof__(*(ptr)))__cmpxchg_local((ptr), (unsigned long)(o),	\
-			(unsigned long)(n), sizeof(*(ptr))))
-#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
-
-#define arch_align_stack(x) (x)
-
-#endif /* __KERNEL__ */
-#endif /* __PPC_SYSTEM_H */
diff --git a/include/asm-ppc/time.h b/include/asm-ppc/time.h
deleted file mode 100644
index 81dbcd43a50..00000000000
--- a/include/asm-ppc/time.h
+++ /dev/null
@@ -1,161 +0,0 @@
-/*
- * Common time prototypes and such for all ppc machines.
- *
- * Written by Cort Dougan (cort@fsmlabs.com) to merge
- * Paul Mackerras' version and mine for PReP and Pmac.
- */
-
-#ifdef __KERNEL__
-#ifndef __ASM_TIME_H__
-#define __ASM_TIME_H__
-
-#include <linux/types.h>
-#include <linux/rtc.h>
-#include <linux/threads.h>
-
-#include <asm/reg.h>
-
-/* time.c */
-extern unsigned tb_ticks_per_jiffy;
-extern unsigned tb_to_us;
-extern unsigned tb_last_stamp;
-extern unsigned long disarm_decr[NR_CPUS];
-
-extern void to_tm(int tim, struct rtc_time * tm);
-extern time_t last_rtc_update;
-
-extern void set_dec_cpu6(unsigned int val);
-
-int via_calibrate_decr(void);
-
-/* Accessor functions for the decrementer register.
- * The 4xx doesn't even have a decrementer.  I tried to use the
- * generic timer interrupt code, which seems OK, with the 4xx PIT
- * in auto-reload mode.  The problem is PIT stops counting when it
- * hits zero.  If it would wrap, we could use it just like a decrementer.
- */
-static __inline__ unsigned int get_dec(void)
-{
-#if defined(CONFIG_40x)
-	return (mfspr(SPRN_PIT));
-#else
-	return (mfspr(SPRN_DEC));
-#endif
-}
-
-static __inline__ void set_dec(unsigned int val)
-{
-#if defined(CONFIG_40x)
-	return;		/* Have to let it auto-reload */
-#elif defined(CONFIG_8xx_CPU6)
-	set_dec_cpu6(val);
-#else
-	mtspr(SPRN_DEC, val);
-#endif
-}
-
-/* Accessor functions for the timebase (RTC on 601) registers. */
-/* If one day CONFIG_POWER is added just define __USE_RTC as 1 */
-#ifdef CONFIG_6xx
-extern __inline__ int __pure __USE_RTC(void) {
-	return (mfspr(SPRN_PVR)>>16) == 1;
-}
-#else
-#define __USE_RTC() 0
-#endif
-
-extern __inline__ unsigned long get_tbl(void) {
-	unsigned long tbl;
-#if defined(CONFIG_403GCX)
-	asm volatile("mfspr %0, 0x3dd" : "=r" (tbl));
-#else
-	asm volatile("mftb %0" : "=r" (tbl));
-#endif
-	return tbl;
-}
-
-extern __inline__ unsigned long get_tbu(void) {
-	unsigned long tbl;
-#if defined(CONFIG_403GCX)
-	asm volatile("mfspr %0, 0x3dc" : "=r" (tbl));
-#else
-	asm volatile("mftbu %0" : "=r" (tbl));
-#endif
-	return tbl;
-}
-
-extern __inline__ void set_tb(unsigned int upper, unsigned int lower)
-{
-	mtspr(SPRN_TBWL, 0);
-	mtspr(SPRN_TBWU, upper);
-	mtspr(SPRN_TBWL, lower);
-}
-
-extern __inline__ unsigned long get_rtcl(void) {
-	unsigned long rtcl;
-	asm volatile("mfrtcl %0" : "=r" (rtcl));
-	return rtcl;
-}
-
-extern __inline__ unsigned long get_rtcu(void)
-{
-	unsigned long rtcu;
-	asm volatile("mfrtcu %0" : "=r" (rtcu));
-	return rtcu;
-}
-
-extern __inline__ unsigned get_native_tbl(void) {
-	if (__USE_RTC())
-		return get_rtcl();
-	else
-	  	return get_tbl();
-}
-
-/* On machines with RTC, this function can only be used safely
- * after the timestamp and for 1 second. It is only used by gettimeofday
- * however so it should not matter.
- */
-extern __inline__ unsigned tb_ticks_since(unsigned tstamp) {
-	if (__USE_RTC()) {
-		int delta = get_rtcl() - tstamp;
-		return delta<0 ? delta + 1000000000 : delta;
-	} else {
-        	return get_tbl() - tstamp;
-	}
-}
-
-#if 0
-extern __inline__ unsigned long get_bin_rtcl(void) {
-      unsigned long rtcl, rtcu1, rtcu2;
-      asm volatile("\
-1:    mfrtcu  %0\n\
-      mfrtcl  %1\n\
-      mfrtcu  %2\n\
-      cmpw    %0,%2\n\
-      bne-    1b\n"
-      : "=r" (rtcu1), "=r" (rtcl), "=r" (rtcu2)
-      : : "cr0");
-      return rtcu2*1000000000+rtcl;
-}
-
-extern __inline__ unsigned binary_tbl(void) {
-      if (__USE_RTC())
-              return get_bin_rtcl();
-      else
-              return get_tbl();
-}
-#endif
-
-/* Use mulhwu to scale processor timebase to timeval */
-/* Specifically, this computes (x * y) / 2^32.  -- paulus */
-#define mulhwu(x,y) \
-({unsigned z; asm ("mulhwu %0,%1,%2" : "=r" (z) : "r" (x), "r" (y)); z;})
-
-unsigned mulhwu_scale_factor(unsigned, unsigned);
-
-#define account_process_vtime(tsk)		do { } while (0)
-#define calculate_steal_time()			do { } while (0)
-#define snapshot_timebases()			do { } while (0)
-
-#endif /* __ASM_TIME_H__ */
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/todc.h b/include/asm-ppc/todc.h
deleted file mode 100644
index 937c7dbe6e5..00000000000
--- a/include/asm-ppc/todc.h
+++ /dev/null
@@ -1,488 +0,0 @@
-/*
- * Definitions for the M48Txx and mc146818 series of Time of day/Real Time
- * Clock chips.
- *
- * Author: Mark A. Greer
- *         mgreer@mvista.com
- *
- * 2001 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-/*
- * Support for the M48T37/M48T59/.../mc146818 Real Time Clock chips.
- * Purpose is to make one generic file that handles all of these chips instead
- * of every platform implementing the same code over & over again.
- */
-
-#ifndef __PPC_KERNEL_TODC_H
-#define __PPC_KERNEL_TODC_H
-
-typedef struct {
-	uint rtc_type;		/* your particular chip */
-
-	/*
-	 * Following are the addresses of the AS0, AS1, and DATA registers
-	 * of these chips.  Note that these are board-specific.
-	 */
-	unsigned int nvram_as0;
-	unsigned int nvram_as1;
-	unsigned int nvram_data;
-
-	/*
-	 * Define bits to stop external set of regs from changing so
-	 * the chip can be read/written reliably.
-	 */
-	unsigned char enable_read;
-	unsigned char enable_write;
-
-	/*
-	 * Following is the number of AS0 address bits.  This is normally
-	 * 8 but some bad hardware routes address lines incorrectly.
-	 */
-	int as0_bits;
-
-	int nvram_size;	/* Size of NVRAM on chip */
-	int sw_flags;	/* Software control flags */
-
-	/* Following are the register offsets for the particular chip */
-	int year;
-	int month;
-	int day_of_month;
-	int day_of_week;
-	int hours;
-	int minutes;
-	int seconds;
-	int control_b;
-	int control_a;
-	int watchdog;
-	int interrupts;
-	int alarm_date;
-	int alarm_hour;
-	int alarm_minutes;
-	int alarm_seconds;
-	int century;
-	int flags;
-
-	/*
-	 * Some RTC chips have their NVRAM buried behind a addr/data pair of
-	 * regs on the first level/clock registers.  The following fields
-	 * are the addresses for those addr/data regs.
-	 */
-	int nvram_addr_reg;
-	int nvram_data_reg;
-} todc_info_t;
-
-/*
- * Define the types of TODC/RTC variants that are supported in
- * arch/ppc/kernel/todc_time.c
- * Make a new one of these for any chip somehow differs from what's already
- * defined.  That way, if you ever need to put in code to touch those
- * bits/registers in todc_time.c, you can put it inside an
- * 'if (todc_info->rtc_type ==  TODC_TYPE_XXX)' so you won't break
- * anyone else.
- */
-#define	TODC_TYPE_MK48T35		1
-#define	TODC_TYPE_MK48T37		2
-#define	TODC_TYPE_MK48T59		3
-#define	TODC_TYPE_DS1693		4	/* Dallas DS1693 RTC */
-#define	TODC_TYPE_DS1743		5	/* Dallas DS1743 RTC */
-#define	TODC_TYPE_DS1746		6	/* Dallas DS1746 RTC */
-#define	TODC_TYPE_DS1747		7	/* Dallas DS1747 RTC */
-#define	TODC_TYPE_DS1501		8	/* Dallas DS1501 RTC */
-#define TODC_TYPE_DS1643		9	/* Dallas DS1643 RTC */
-#define TODC_TYPE_PC97307		10	/* PC97307 internal RTC */
-#define TODC_TYPE_DS1557		11	/* Dallas DS1557 RTC */
-#define TODC_TYPE_DS17285		12	/* Dallas DS17285 RTC */
-#define TODC_TYPE_DS1553		13	/* Dallas DS1553 RTC */
-#define	TODC_TYPE_MC146818		100	/* Leave room for m48txx's */
-
-/*
- * Bit to clear/set to enable reads/writes to the chip
- */
-#define	TODC_MK48TXX_CNTL_A_R		0x40
-#define	TODC_MK48TXX_CNTL_A_W		0x80
-#define	TODC_MK48TXX_DAY_CB		0x80
-
-#define	TODC_DS1501_CNTL_B_TE		0x80
-
-/*
- * Define flag bits used by todc routines.
- */
-#define	TODC_FLAG_2_LEVEL_NVRAM		0x00000001
-
-/*
- * Define the values for the various RTC's that should to into the todc_info
- * table.
- * Note: The XXX_NVRAM_SIZE, XXX_NVRAM_ADDR_REG, and XXX_NVRAM_DATA_REG only
- * matter if XXX_SW_FLAGS has TODC_FLAG_2_LEVEL_NVRAM set.
- */
-#define	TODC_TYPE_MK48T35_NVRAM_SIZE		0x7ff8
-#define	TODC_TYPE_MK48T35_SW_FLAGS		0
-#define	TODC_TYPE_MK48T35_YEAR			0x7fff
-#define	TODC_TYPE_MK48T35_MONTH			0x7ffe
-#define	TODC_TYPE_MK48T35_DOM			0x7ffd	/* Day of Month */
-#define	TODC_TYPE_MK48T35_DOW			0x7ffc	/* Day of Week */
-#define	TODC_TYPE_MK48T35_HOURS			0x7ffb
-#define	TODC_TYPE_MK48T35_MINUTES		0x7ffa
-#define	TODC_TYPE_MK48T35_SECONDS		0x7ff9
-#define	TODC_TYPE_MK48T35_CNTL_B		0x7ff9
-#define	TODC_TYPE_MK48T35_CNTL_A		0x7ff8
-#define	TODC_TYPE_MK48T35_WATCHDOG		0x0000
-#define	TODC_TYPE_MK48T35_INTERRUPTS		0x0000
-#define	TODC_TYPE_MK48T35_ALARM_DATE		0x0000
-#define	TODC_TYPE_MK48T35_ALARM_HOUR		0x0000
-#define	TODC_TYPE_MK48T35_ALARM_MINUTES		0x0000
-#define	TODC_TYPE_MK48T35_ALARM_SECONDS		0x0000
-#define	TODC_TYPE_MK48T35_CENTURY		0x0000
-#define	TODC_TYPE_MK48T35_FLAGS			0x0000
-#define	TODC_TYPE_MK48T35_NVRAM_ADDR_REG	0
-#define	TODC_TYPE_MK48T35_NVRAM_DATA_REG	0
-
-#define	TODC_TYPE_MK48T37_NVRAM_SIZE		0x7ff0
-#define	TODC_TYPE_MK48T37_SW_FLAGS		0
-#define	TODC_TYPE_MK48T37_YEAR			0x7fff
-#define	TODC_TYPE_MK48T37_MONTH			0x7ffe
-#define	TODC_TYPE_MK48T37_DOM			0x7ffd	/* Day of Month */
-#define	TODC_TYPE_MK48T37_DOW			0x7ffc	/* Day of Week */
-#define	TODC_TYPE_MK48T37_HOURS			0x7ffb
-#define	TODC_TYPE_MK48T37_MINUTES		0x7ffa
-#define	TODC_TYPE_MK48T37_SECONDS		0x7ff9
-#define	TODC_TYPE_MK48T37_CNTL_B		0x7ff9
-#define	TODC_TYPE_MK48T37_CNTL_A		0x7ff8
-#define	TODC_TYPE_MK48T37_WATCHDOG		0x7ff7
-#define	TODC_TYPE_MK48T37_INTERRUPTS		0x7ff6
-#define	TODC_TYPE_MK48T37_ALARM_DATE		0x7ff5
-#define	TODC_TYPE_MK48T37_ALARM_HOUR		0x7ff4
-#define	TODC_TYPE_MK48T37_ALARM_MINUTES		0x7ff3
-#define	TODC_TYPE_MK48T37_ALARM_SECONDS		0x7ff2
-#define	TODC_TYPE_MK48T37_CENTURY		0x7ff1
-#define	TODC_TYPE_MK48T37_FLAGS			0x7ff0
-#define	TODC_TYPE_MK48T37_NVRAM_ADDR_REG	0
-#define	TODC_TYPE_MK48T37_NVRAM_DATA_REG	0
-
-#define	TODC_TYPE_MK48T59_NVRAM_SIZE		0x1ff0
-#define	TODC_TYPE_MK48T59_SW_FLAGS		0
-#define	TODC_TYPE_MK48T59_YEAR			0x1fff
-#define	TODC_TYPE_MK48T59_MONTH			0x1ffe
-#define	TODC_TYPE_MK48T59_DOM			0x1ffd	/* Day of Month */
-#define	TODC_TYPE_MK48T59_DOW			0x1ffc	/* Day of Week */
-#define	TODC_TYPE_MK48T59_HOURS			0x1ffb
-#define	TODC_TYPE_MK48T59_MINUTES		0x1ffa
-#define	TODC_TYPE_MK48T59_SECONDS		0x1ff9
-#define	TODC_TYPE_MK48T59_CNTL_B		0x1ff9
-#define	TODC_TYPE_MK48T59_CNTL_A		0x1ff8
-#define	TODC_TYPE_MK48T59_WATCHDOG		0x1fff
-#define	TODC_TYPE_MK48T59_INTERRUPTS		0x1fff
-#define	TODC_TYPE_MK48T59_ALARM_DATE		0x1fff
-#define	TODC_TYPE_MK48T59_ALARM_HOUR		0x1fff
-#define	TODC_TYPE_MK48T59_ALARM_MINUTES		0x1fff
-#define	TODC_TYPE_MK48T59_ALARM_SECONDS		0x1fff
-#define	TODC_TYPE_MK48T59_CENTURY		0x1fff
-#define	TODC_TYPE_MK48T59_FLAGS			0x1fff
-#define	TODC_TYPE_MK48T59_NVRAM_ADDR_REG	0
-#define	TODC_TYPE_MK48T59_NVRAM_DATA_REG	0
-
-#define	TODC_TYPE_DS1501_NVRAM_SIZE	0x100
-#define	TODC_TYPE_DS1501_SW_FLAGS	TODC_FLAG_2_LEVEL_NVRAM
-#define	TODC_TYPE_DS1501_YEAR		(TODC_TYPE_DS1501_NVRAM_SIZE + 0x06)
-#define	TODC_TYPE_DS1501_MONTH		(TODC_TYPE_DS1501_NVRAM_SIZE + 0x05)
-#define	TODC_TYPE_DS1501_DOM		(TODC_TYPE_DS1501_NVRAM_SIZE + 0x04)
-#define	TODC_TYPE_DS1501_DOW		(TODC_TYPE_DS1501_NVRAM_SIZE + 0x03)
-#define	TODC_TYPE_DS1501_HOURS		(TODC_TYPE_DS1501_NVRAM_SIZE + 0x02)
-#define	TODC_TYPE_DS1501_MINUTES	(TODC_TYPE_DS1501_NVRAM_SIZE + 0x01)
-#define	TODC_TYPE_DS1501_SECONDS	(TODC_TYPE_DS1501_NVRAM_SIZE + 0x00)
-#define	TODC_TYPE_DS1501_CNTL_B		(TODC_TYPE_DS1501_NVRAM_SIZE + 0x0f)
-#define	TODC_TYPE_DS1501_CNTL_A		(TODC_TYPE_DS1501_NVRAM_SIZE + 0x0f)
-#define	TODC_TYPE_DS1501_WATCHDOG	(TODC_TYPE_DS1501_NVRAM_SIZE + 0xff)
-#define	TODC_TYPE_DS1501_INTERRUPTS	(TODC_TYPE_DS1501_NVRAM_SIZE + 0xff)
-#define	TODC_TYPE_DS1501_ALARM_DATE	(TODC_TYPE_DS1501_NVRAM_SIZE + 0x0b)
-#define	TODC_TYPE_DS1501_ALARM_HOUR	(TODC_TYPE_DS1501_NVRAM_SIZE + 0x0a)
-#define	TODC_TYPE_DS1501_ALARM_MINUTES	(TODC_TYPE_DS1501_NVRAM_SIZE + 0x09)
-#define	TODC_TYPE_DS1501_ALARM_SECONDS	(TODC_TYPE_DS1501_NVRAM_SIZE + 0x08)
-#define	TODC_TYPE_DS1501_CENTURY	(TODC_TYPE_DS1501_NVRAM_SIZE + 0x07)
-#define	TODC_TYPE_DS1501_FLAGS		(TODC_TYPE_DS1501_NVRAM_SIZE + 0xff)
-#define	TODC_TYPE_DS1501_NVRAM_ADDR_REG	0x10
-#define	TODC_TYPE_DS1501_NVRAM_DATA_REG	0x13
-
-#define	TODC_TYPE_DS1553_NVRAM_SIZE		0x1ff0
-#define	TODC_TYPE_DS1553_SW_FLAGS		0
-#define	TODC_TYPE_DS1553_YEAR			0x1fff
-#define	TODC_TYPE_DS1553_MONTH			0x1ffe
-#define	TODC_TYPE_DS1553_DOM			0x1ffd	/* Day of Month */
-#define	TODC_TYPE_DS1553_DOW			0x1ffc	/* Day of Week */
-#define	TODC_TYPE_DS1553_HOURS			0x1ffb
-#define	TODC_TYPE_DS1553_MINUTES		0x1ffa
-#define	TODC_TYPE_DS1553_SECONDS		0x1ff9
-#define	TODC_TYPE_DS1553_CNTL_B			0x1ff9
-#define	TODC_TYPE_DS1553_CNTL_A			0x1ff8	/* control_a R/W regs */
-#define	TODC_TYPE_DS1553_WATCHDOG		0x1ff7
-#define	TODC_TYPE_DS1553_INTERRUPTS		0x1ff6
-#define	TODC_TYPE_DS1553_ALARM_DATE		0x1ff5
-#define	TODC_TYPE_DS1553_ALARM_HOUR		0x1ff4
-#define	TODC_TYPE_DS1553_ALARM_MINUTES		0x1ff3
-#define	TODC_TYPE_DS1553_ALARM_SECONDS		0x1ff2
-#define	TODC_TYPE_DS1553_CENTURY		0x1ff8
-#define	TODC_TYPE_DS1553_FLAGS			0x1ff0
-#define	TODC_TYPE_DS1553_NVRAM_ADDR_REG		0
-#define	TODC_TYPE_DS1553_NVRAM_DATA_REG		0
-
-#define	TODC_TYPE_DS1557_NVRAM_SIZE		0x7fff0
-#define	TODC_TYPE_DS1557_SW_FLAGS		0
-#define	TODC_TYPE_DS1557_YEAR			0x7ffff
-#define	TODC_TYPE_DS1557_MONTH			0x7fffe
-#define	TODC_TYPE_DS1557_DOM			0x7fffd	/* Day of Month */
-#define	TODC_TYPE_DS1557_DOW			0x7fffc	/* Day of Week */
-#define	TODC_TYPE_DS1557_HOURS			0x7fffb
-#define	TODC_TYPE_DS1557_MINUTES		0x7fffa
-#define	TODC_TYPE_DS1557_SECONDS		0x7fff9
-#define	TODC_TYPE_DS1557_CNTL_B			0x7fff9
-#define	TODC_TYPE_DS1557_CNTL_A			0x7fff8	/* control_a R/W regs */
-#define	TODC_TYPE_DS1557_WATCHDOG		0x7fff7
-#define	TODC_TYPE_DS1557_INTERRUPTS		0x7fff6
-#define	TODC_TYPE_DS1557_ALARM_DATE		0x7fff5
-#define	TODC_TYPE_DS1557_ALARM_HOUR		0x7fff4
-#define	TODC_TYPE_DS1557_ALARM_MINUTES		0x7fff3
-#define	TODC_TYPE_DS1557_ALARM_SECONDS		0x7fff2
-#define	TODC_TYPE_DS1557_CENTURY		0x7fff8
-#define	TODC_TYPE_DS1557_FLAGS			0x7fff0
-#define	TODC_TYPE_DS1557_NVRAM_ADDR_REG		0
-#define	TODC_TYPE_DS1557_NVRAM_DATA_REG		0
-
-#define	TODC_TYPE_DS1643_NVRAM_SIZE		0x1ff8
-#define	TODC_TYPE_DS1643_SW_FLAGS		0
-#define	TODC_TYPE_DS1643_YEAR			0x1fff
-#define	TODC_TYPE_DS1643_MONTH			0x1ffe
-#define	TODC_TYPE_DS1643_DOM			0x1ffd	/* Day of Month */
-#define	TODC_TYPE_DS1643_DOW			0x1ffc	/* Day of Week */
-#define	TODC_TYPE_DS1643_HOURS			0x1ffb
-#define	TODC_TYPE_DS1643_MINUTES		0x1ffa
-#define	TODC_TYPE_DS1643_SECONDS		0x1ff9
-#define	TODC_TYPE_DS1643_CNTL_B			0x1ff9
-#define	TODC_TYPE_DS1643_CNTL_A			0x1ff8	/* control_a R/W regs */
-#define	TODC_TYPE_DS1643_WATCHDOG		0x1fff
-#define	TODC_TYPE_DS1643_INTERRUPTS		0x1fff
-#define	TODC_TYPE_DS1643_ALARM_DATE		0x1fff
-#define	TODC_TYPE_DS1643_ALARM_HOUR		0x1fff
-#define	TODC_TYPE_DS1643_ALARM_MINUTES		0x1fff
-#define	TODC_TYPE_DS1643_ALARM_SECONDS		0x1fff
-#define	TODC_TYPE_DS1643_CENTURY		0x1ff8
-#define	TODC_TYPE_DS1643_FLAGS			0x1fff
-#define	TODC_TYPE_DS1643_NVRAM_ADDR_REG		0
-#define	TODC_TYPE_DS1643_NVRAM_DATA_REG		0
-
-#define	TODC_TYPE_DS1693_NVRAM_SIZE		0 /* Not handled yet */
-#define	TODC_TYPE_DS1693_SW_FLAGS		0
-#define	TODC_TYPE_DS1693_YEAR			0x09
-#define	TODC_TYPE_DS1693_MONTH			0x08
-#define	TODC_TYPE_DS1693_DOM			0x07	/* Day of Month */
-#define	TODC_TYPE_DS1693_DOW			0x06	/* Day of Week */
-#define	TODC_TYPE_DS1693_HOURS			0x04
-#define	TODC_TYPE_DS1693_MINUTES		0x02
-#define	TODC_TYPE_DS1693_SECONDS		0x00
-#define	TODC_TYPE_DS1693_CNTL_B			0x0b
-#define	TODC_TYPE_DS1693_CNTL_A			0x0a
-#define	TODC_TYPE_DS1693_WATCHDOG		0xff
-#define	TODC_TYPE_DS1693_INTERRUPTS		0xff
-#define	TODC_TYPE_DS1693_ALARM_DATE		0x49
-#define	TODC_TYPE_DS1693_ALARM_HOUR		0x05
-#define	TODC_TYPE_DS1693_ALARM_MINUTES		0x03
-#define	TODC_TYPE_DS1693_ALARM_SECONDS		0x01
-#define	TODC_TYPE_DS1693_CENTURY		0x48
-#define	TODC_TYPE_DS1693_FLAGS			0xff
-#define	TODC_TYPE_DS1693_NVRAM_ADDR_REG		0
-#define	TODC_TYPE_DS1693_NVRAM_DATA_REG		0
-
-#define	TODC_TYPE_DS1743_NVRAM_SIZE		0x1ff8
-#define	TODC_TYPE_DS1743_SW_FLAGS		0
-#define	TODC_TYPE_DS1743_YEAR			0x1fff
-#define	TODC_TYPE_DS1743_MONTH			0x1ffe
-#define	TODC_TYPE_DS1743_DOM			0x1ffd	/* Day of Month */
-#define	TODC_TYPE_DS1743_DOW			0x1ffc	/* Day of Week */
-#define	TODC_TYPE_DS1743_HOURS			0x1ffb
-#define	TODC_TYPE_DS1743_MINUTES		0x1ffa
-#define	TODC_TYPE_DS1743_SECONDS		0x1ff9
-#define	TODC_TYPE_DS1743_CNTL_B			0x1ff9
-#define	TODC_TYPE_DS1743_CNTL_A			0x1ff8	/* control_a R/W regs */
-#define	TODC_TYPE_DS1743_WATCHDOG		0x1fff
-#define	TODC_TYPE_DS1743_INTERRUPTS		0x1fff
-#define	TODC_TYPE_DS1743_ALARM_DATE		0x1fff
-#define	TODC_TYPE_DS1743_ALARM_HOUR		0x1fff
-#define	TODC_TYPE_DS1743_ALARM_MINUTES		0x1fff
-#define	TODC_TYPE_DS1743_ALARM_SECONDS		0x1fff
-#define	TODC_TYPE_DS1743_CENTURY		0x1ff8
-#define	TODC_TYPE_DS1743_FLAGS			0x1fff
-#define	TODC_TYPE_DS1743_NVRAM_ADDR_REG		0
-#define	TODC_TYPE_DS1743_NVRAM_DATA_REG		0
-
-#define	TODC_TYPE_DS1746_NVRAM_SIZE		0x1fff8
-#define	TODC_TYPE_DS1746_SW_FLAGS		0
-#define	TODC_TYPE_DS1746_YEAR			0x1ffff
-#define	TODC_TYPE_DS1746_MONTH			0x1fffe
-#define	TODC_TYPE_DS1746_DOM			0x1fffd	/* Day of Month */
-#define	TODC_TYPE_DS1746_DOW			0x1fffc	/* Day of Week */
-#define	TODC_TYPE_DS1746_HOURS			0x1fffb
-#define	TODC_TYPE_DS1746_MINUTES		0x1fffa
-#define	TODC_TYPE_DS1746_SECONDS		0x1fff9
-#define	TODC_TYPE_DS1746_CNTL_B			0x1fff9
-#define	TODC_TYPE_DS1746_CNTL_A			0x1fff8	/* control_a R/W regs */
-#define	TODC_TYPE_DS1746_WATCHDOG		0x00000
-#define	TODC_TYPE_DS1746_INTERRUPTS		0x00000
-#define	TODC_TYPE_DS1746_ALARM_DATE		0x00000
-#define	TODC_TYPE_DS1746_ALARM_HOUR		0x00000
-#define	TODC_TYPE_DS1746_ALARM_MINUTES		0x00000
-#define	TODC_TYPE_DS1746_ALARM_SECONDS		0x00000
-#define	TODC_TYPE_DS1746_CENTURY		0x00000
-#define	TODC_TYPE_DS1746_FLAGS			0x00000
-#define	TODC_TYPE_DS1746_NVRAM_ADDR_REG		0
-#define	TODC_TYPE_DS1746_NVRAM_DATA_REG		0
-
-#define	TODC_TYPE_DS1747_NVRAM_SIZE		0x7fff8
-#define	TODC_TYPE_DS1747_SW_FLAGS		0
-#define	TODC_TYPE_DS1747_YEAR			0x7ffff
-#define	TODC_TYPE_DS1747_MONTH			0x7fffe
-#define	TODC_TYPE_DS1747_DOM			0x7fffd	/* Day of Month */
-#define	TODC_TYPE_DS1747_DOW			0x7fffc	/* Day of Week */
-#define	TODC_TYPE_DS1747_HOURS			0x7fffb
-#define	TODC_TYPE_DS1747_MINUTES		0x7fffa
-#define	TODC_TYPE_DS1747_SECONDS		0x7fff9
-#define	TODC_TYPE_DS1747_CNTL_B			0x7fff9
-#define	TODC_TYPE_DS1747_CNTL_A			0x7fff8	/* control_a R/W regs */
-#define	TODC_TYPE_DS1747_WATCHDOG		0x00000
-#define	TODC_TYPE_DS1747_INTERRUPTS		0x00000
-#define	TODC_TYPE_DS1747_ALARM_DATE		0x00000
-#define	TODC_TYPE_DS1747_ALARM_HOUR		0x00000
-#define	TODC_TYPE_DS1747_ALARM_MINUTES		0x00000
-#define	TODC_TYPE_DS1747_ALARM_SECONDS		0x00000
-#define	TODC_TYPE_DS1747_CENTURY		0x00000
-#define	TODC_TYPE_DS1747_FLAGS			0x00000
-#define	TODC_TYPE_DS1747_NVRAM_ADDR_REG		0
-#define	TODC_TYPE_DS1747_NVRAM_DATA_REG		0
-
-#define TODC_TYPE_DS17285_NVRAM_SIZE		(0x1000-0x80)    /* 4Kx8 NVRAM (minus RTC regs) */
-#define TODC_TYPE_DS17285_SW_FLAGS		TODC_FLAG_2_LEVEL_NVRAM
-#define TODC_TYPE_DS17285_SECONDS		(TODC_TYPE_DS17285_NVRAM_SIZE + 0x00)
-#define TODC_TYPE_DS17285_ALARM_SECONDS		(TODC_TYPE_DS17285_NVRAM_SIZE + 0x01)
-#define TODC_TYPE_DS17285_MINUTES		(TODC_TYPE_DS17285_NVRAM_SIZE + 0x02)
-#define TODC_TYPE_DS17285_ALARM_MINUTES		(TODC_TYPE_DS17285_NVRAM_SIZE + 0x03)
-#define TODC_TYPE_DS17285_HOURS			(TODC_TYPE_DS17285_NVRAM_SIZE + 0x04)
-#define TODC_TYPE_DS17285_ALARM_HOUR		(TODC_TYPE_DS17285_NVRAM_SIZE + 0x05)
-#define TODC_TYPE_DS17285_DOW			(TODC_TYPE_DS17285_NVRAM_SIZE + 0x06)
-#define TODC_TYPE_DS17285_DOM			(TODC_TYPE_DS17285_NVRAM_SIZE + 0x07)
-#define TODC_TYPE_DS17285_MONTH			(TODC_TYPE_DS17285_NVRAM_SIZE + 0x08)
-#define TODC_TYPE_DS17285_YEAR			(TODC_TYPE_DS17285_NVRAM_SIZE + 0x09)
-#define TODC_TYPE_DS17285_CNTL_A		(TODC_TYPE_DS17285_NVRAM_SIZE + 0x0A)
-#define TODC_TYPE_DS17285_CNTL_B		(TODC_TYPE_DS17285_NVRAM_SIZE + 0x0B)
-#define TODC_TYPE_DS17285_CNTL_C		(TODC_TYPE_DS17285_NVRAM_SIZE + 0x0C)
-#define TODC_TYPE_DS17285_CNTL_D		(TODC_TYPE_DS17285_NVRAM_SIZE + 0x0D)
-#define TODC_TYPE_DS17285_WATCHDOG		0
-#define TODC_TYPE_DS17285_INTERRUPTS		0
-#define TODC_TYPE_DS17285_ALARM_DATE		0
-#define TODC_TYPE_DS17285_CENTURY		0
-#define TODC_TYPE_DS17285_FLAGS			0
-#define TODC_TYPE_DS17285_NVRAM_ADDR_REG	0x50
-#define TODC_TYPE_DS17285_NVRAM_DATA_REG	0x53
- 
-#define	TODC_TYPE_MC146818_NVRAM_SIZE		0	/* XXXX */
-#define	TODC_TYPE_MC146818_SW_FLAGS		0
-#define	TODC_TYPE_MC146818_YEAR			0x09
-#define	TODC_TYPE_MC146818_MONTH		0x08
-#define	TODC_TYPE_MC146818_DOM			0x07	/* Day of Month */
-#define	TODC_TYPE_MC146818_DOW			0x06	/* Day of Week */
-#define	TODC_TYPE_MC146818_HOURS		0x04
-#define	TODC_TYPE_MC146818_MINUTES		0x02
-#define	TODC_TYPE_MC146818_SECONDS		0x00
-#define	TODC_TYPE_MC146818_CNTL_B		0x0a
-#define	TODC_TYPE_MC146818_CNTL_A		0x0b	/* control_a R/W regs */
-#define	TODC_TYPE_MC146818_WATCHDOG		0
-#define	TODC_TYPE_MC146818_INTERRUPTS		0x0c
-#define	TODC_TYPE_MC146818_ALARM_DATE		0xff
-#define	TODC_TYPE_MC146818_ALARM_HOUR		0x05
-#define	TODC_TYPE_MC146818_ALARM_MINUTES	0x03
-#define	TODC_TYPE_MC146818_ALARM_SECONDS	0x01
-#define	TODC_TYPE_MC146818_CENTURY		0xff
-#define	TODC_TYPE_MC146818_FLAGS		0xff
-#define	TODC_TYPE_MC146818_NVRAM_ADDR_REG	0
-#define	TODC_TYPE_MC146818_NVRAM_DATA_REG	0
-  
-#define	TODC_TYPE_PC97307_NVRAM_SIZE		0	/* No NVRAM? */
-#define	TODC_TYPE_PC97307_SW_FLAGS		0
-#define	TODC_TYPE_PC97307_YEAR			0x09
-#define	TODC_TYPE_PC97307_MONTH			0x08
-#define	TODC_TYPE_PC97307_DOM			0x07	/* Day of Month */
-#define	TODC_TYPE_PC97307_DOW			0x06	/* Day of Week */
-#define	TODC_TYPE_PC97307_HOURS			0x04
-#define	TODC_TYPE_PC97307_MINUTES		0x02
-#define	TODC_TYPE_PC97307_SECONDS		0x00
-#define	TODC_TYPE_PC97307_CNTL_B		0x0a
-#define	TODC_TYPE_PC97307_CNTL_A		0x0b	/* control_a R/W regs */
-#define	TODC_TYPE_PC97307_WATCHDOG		0x0c
-#define	TODC_TYPE_PC97307_INTERRUPTS		0x0d
-#define	TODC_TYPE_PC97307_ALARM_DATE		0xff
-#define	TODC_TYPE_PC97307_ALARM_HOUR		0x05
-#define	TODC_TYPE_PC97307_ALARM_MINUTES		0x03
-#define	TODC_TYPE_PC97307_ALARM_SECONDS		0x01
-#define	TODC_TYPE_PC97307_CENTURY		0xff
-#define	TODC_TYPE_PC97307_FLAGS			0xff
-#define	TODC_TYPE_PC97307_NVRAM_ADDR_REG	0
-#define	TODC_TYPE_PC97307_NVRAM_DATA_REG	0
-
-/*
- * Define macros to allocate and init the todc_info_t table that will
- * be used by the todc_time.c routines.
- */
-#define	TODC_ALLOC()							\
-	static todc_info_t todc_info_alloc;				\
-	todc_info_t *todc_info = &todc_info_alloc;
-
-#define	TODC_INIT(clock_type, as0, as1, data, bits) {			\
-	todc_info->rtc_type = clock_type;				\
-									\
-	todc_info->nvram_as0  = (unsigned int)(as0);			\
-	todc_info->nvram_as1  = (unsigned int)(as1);			\
-	todc_info->nvram_data = (unsigned int)(data);			\
-									\
-	todc_info->as0_bits = (bits);					\
-									\
-	todc_info->nvram_size     = clock_type ##_NVRAM_SIZE;		\
-	todc_info->sw_flags       = clock_type ##_SW_FLAGS;		\
-									\
-	todc_info->year           = clock_type ##_YEAR;			\
-	todc_info->month          = clock_type ##_MONTH;		\
-	todc_info->day_of_month   = clock_type ##_DOM;			\
-	todc_info->day_of_week    = clock_type ##_DOW;			\
-	todc_info->hours          = clock_type ##_HOURS;		\
-	todc_info->minutes        = clock_type ##_MINUTES;		\
-	todc_info->seconds        = clock_type ##_SECONDS;		\
-	todc_info->control_b      = clock_type ##_CNTL_B;		\
-	todc_info->control_a      = clock_type ##_CNTL_A;		\
-	todc_info->watchdog       = clock_type ##_WATCHDOG;		\
-	todc_info->interrupts     = clock_type ##_INTERRUPTS;		\
-	todc_info->alarm_date     = clock_type ##_ALARM_DATE;		\
-	todc_info->alarm_hour     = clock_type ##_ALARM_HOUR;		\
-	todc_info->alarm_minutes  = clock_type ##_ALARM_MINUTES;	\
-	todc_info->alarm_seconds  = clock_type ##_ALARM_SECONDS;	\
-	todc_info->century        = clock_type ##_CENTURY;		\
-	todc_info->flags          = clock_type ##_FLAGS;		\
-									\
-	todc_info->nvram_addr_reg = clock_type ##_NVRAM_ADDR_REG;	\
-	todc_info->nvram_data_reg = clock_type ##_NVRAM_DATA_REG;	\
-}
-
-extern todc_info_t *todc_info;
-
-unsigned char todc_direct_read_val(int addr);
-void todc_direct_write_val(int addr, unsigned char val);
-unsigned char todc_m48txx_read_val(int addr);
-void todc_m48txx_write_val(int addr, unsigned char val);
-unsigned char todc_mc146818_read_val(int addr);
-void todc_mc146818_write_val(int addr, unsigned char val);
-
-long todc_time_init(void);
-unsigned long todc_get_rtc_time(void);
-int todc_set_rtc_time(unsigned long nowtime);
-void todc_calibrate_decr(void);
-
-#endif				/* __PPC_KERNEL_TODC_H */
diff --git a/include/asm-ppc/traps.h b/include/asm-ppc/traps.h
deleted file mode 100644
index 68e7326b56f..00000000000
--- a/include/asm-ppc/traps.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-m68k/traps.h>
diff --git a/include/asm-ppc/zorro.h b/include/asm-ppc/zorro.h
deleted file mode 100644
index 1e5fbc65e77..00000000000
--- a/include/asm-ppc/zorro.h
+++ /dev/null
@@ -1,30 +0,0 @@
-#ifndef _ASM_PPC_ZORRO_H
-#define _ASM_PPC_ZORRO_H
-
-#include <asm/io.h>
-
-#define z_readb in_8
-#define z_readw in_be16
-#define z_readl in_be32
-
-#define z_writeb(val, port) out_8((port), (val))
-#define z_writew(val, port) out_be16((port), (val))
-#define z_writel(val, port) out_be32((port), (val))
-
-#define z_memset_io(a,b,c)	memset((void *)(a),(b),(c))
-#define z_memcpy_fromio(a,b,c)	memcpy((a),(void *)(b),(c))
-#define z_memcpy_toio(a,b,c)	memcpy((void *)(a),(b),(c))
-
-extern void *__ioremap(unsigned long address, unsigned long size,
-		       unsigned long flags);
-
-extern void *ioremap(unsigned long address, unsigned long size);
-extern void iounmap(void *addr);
-
-extern void *__ioremap(unsigned long address, unsigned long size,
-                       unsigned long flags);
-
-#define z_ioremap ioremap
-#define z_iounmap iounmap
-
-#endif /* _ASM_PPC_ZORRO_H */