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authorLinus Torvalds <torvalds@linux-foundation.org>2008-08-07 18:14:07 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2008-08-07 18:14:07 -0700
commit273b2578392bbf6e5c47a8a3d1ee461ce6fc7182 (patch)
tree1b00bd21574b1f8db084be4f682d7251a3a0ff3e /include/linux
parent8e43e12d638f732fa32600c324711f4be8fe0b1d (diff)
parent06a91a02e9b249695f964bb59c8b02152c21e90c (diff)
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/roland/infiniband
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/roland/infiniband: IB/mad: Test ib_create_send_mad() return with IS_ERR(), not == NULL IB/mlx4: Allow 4K messages for UD QPs mlx4_core: Add ethernet fields to CQE struct IB/ipath: Fix printk format warnings RDMA/cxgb3: Fix deadlock initializing iw_cxgb3 device RDMA/cxgb3: Fix up MW access rights RDMA/cxgb3: Fix QP capabilities RDMA/cma: Remove padding arrays by using struct sockaddr_storage IB/ipath: Use unsigned long for irq flags IPoIB/cm: Set correct SG list in ipoib_cm_init_rx_wr()
Diffstat (limited to 'include/linux')
-rw-r--r--include/linux/mlx4/cq.h36
1 files changed, 24 insertions, 12 deletions
diff --git a/include/linux/mlx4/cq.h b/include/linux/mlx4/cq.h
index 071cf96cf01..6f65b2c8bb8 100644
--- a/include/linux/mlx4/cq.h
+++ b/include/linux/mlx4/cq.h
@@ -39,17 +39,18 @@
#include <linux/mlx4/doorbell.h>
struct mlx4_cqe {
- __be32 my_qpn;
+ __be32 vlan_my_qpn;
__be32 immed_rss_invalid;
__be32 g_mlpath_rqpn;
- u8 sl;
- u8 reserved1;
+ __be16 sl_vid;
__be16 rlid;
- __be32 ipoib_status;
+ __be16 status;
+ u8 ipv6_ext_mask;
+ u8 badfcs_enc;
__be32 byte_cnt;
__be16 wqe_index;
__be16 checksum;
- u8 reserved2[3];
+ u8 reserved[3];
u8 owner_sr_opcode;
};
@@ -64,6 +65,11 @@ struct mlx4_err_cqe {
};
enum {
+ MLX4_CQE_VLAN_PRESENT_MASK = 1 << 29,
+ MLX4_CQE_QPN_MASK = 0xffffff,
+};
+
+enum {
MLX4_CQE_OWNER_MASK = 0x80,
MLX4_CQE_IS_SEND_MASK = 0x40,
MLX4_CQE_OPCODE_MASK = 0x1f
@@ -86,13 +92,19 @@ enum {
};
enum {
- MLX4_CQE_IPOIB_STATUS_IPV4 = 1 << 22,
- MLX4_CQE_IPOIB_STATUS_IPV4F = 1 << 23,
- MLX4_CQE_IPOIB_STATUS_IPV6 = 1 << 24,
- MLX4_CQE_IPOIB_STATUS_IPV4OPT = 1 << 25,
- MLX4_CQE_IPOIB_STATUS_TCP = 1 << 26,
- MLX4_CQE_IPOIB_STATUS_UDP = 1 << 27,
- MLX4_CQE_IPOIB_STATUS_IPOK = 1 << 28,
+ MLX4_CQE_STATUS_IPV4 = 1 << 6,
+ MLX4_CQE_STATUS_IPV4F = 1 << 7,
+ MLX4_CQE_STATUS_IPV6 = 1 << 8,
+ MLX4_CQE_STATUS_IPV4OPT = 1 << 9,
+ MLX4_CQE_STATUS_TCP = 1 << 10,
+ MLX4_CQE_STATUS_UDP = 1 << 11,
+ MLX4_CQE_STATUS_IPOK = 1 << 12,
+};
+
+enum {
+ MLX4_CQE_LLC = 1,
+ MLX4_CQE_SNAP = 1 << 1,
+ MLX4_CQE_BAD_FCS = 1 << 4,
};
static inline void mlx4_cq_arm(struct mlx4_cq *cq, u32 cmd,