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-rw-r--r--arch/arm/mach-orion5x/addr-map.c2
-rw-r--r--arch/arm/mach-orion5x/include/mach/bridge-regs.h41
-rw-r--r--arch/arm/mach-orion5x/include/mach/entry-macro.S2
-rw-r--r--arch/arm/mach-orion5x/include/mach/orion5x.h68
-rw-r--r--arch/arm/mach-orion5x/include/mach/system.h3
-rw-r--r--arch/arm/mach-orion5x/irq.c2
-rw-r--r--arch/arm/mach-orion5x/mss2-setup.c1
-rw-r--r--arch/arm/mach-orion5x/pci.c1
8 files changed, 68 insertions, 52 deletions
diff --git a/arch/arm/mach-orion5x/addr-map.c b/arch/arm/mach-orion5x/addr-map.c
index 719957e05d9..c14d1213727 100644
--- a/arch/arm/mach-orion5x/addr-map.c
+++ b/arch/arm/mach-orion5x/addr-map.c
@@ -57,12 +57,14 @@
/*
* Helpers to get DDR bank info
*/
+#define ORION5X_DDR_REG(x) (ORION5X_DDR_VIRT_BASE | (x))
#define DDR_BASE_CS(n) ORION5X_DDR_REG(0x1500 + ((n) << 3))
#define DDR_SIZE_CS(n) ORION5X_DDR_REG(0x1504 + ((n) << 3))
/*
* CPU Address Decode Windows registers
*/
+#define ORION5X_BRIDGE_REG(x) (ORION5X_BRIDGE_VIRT_BASE | (x))
#define CPU_WIN_CTRL(n) ORION5X_BRIDGE_REG(0x000 | ((n) << 4))
#define CPU_WIN_BASE(n) ORION5X_BRIDGE_REG(0x004 | ((n) << 4))
#define CPU_WIN_REMAP_LO(n) ORION5X_BRIDGE_REG(0x008 | ((n) << 4))
diff --git a/arch/arm/mach-orion5x/include/mach/bridge-regs.h b/arch/arm/mach-orion5x/include/mach/bridge-regs.h
new file mode 100644
index 00000000000..be896e59d3e
--- /dev/null
+++ b/arch/arm/mach-orion5x/include/mach/bridge-regs.h
@@ -0,0 +1,41 @@
+/*
+ * arch/arm/mach-orion5x/include/mach/bridge-regs.h
+ *
+ * Orion CPU Bridge Registers
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_BRIDGE_REGS_H
+#define __ASM_ARCH_BRIDGE_REGS_H
+
+#include <mach/orion5x.h>
+
+#define CPU_CONF (ORION5X_BRIDGE_VIRT_BASE | 0x100)
+
+#define CPU_CTRL (ORION5X_BRIDGE_VIRT_BASE | 0x104)
+
+#define CPU_RESET_MASK (ORION5X_BRIDGE_VIRT_BASE | 0x108)
+#define WDT_RESET 0x0002
+
+#define CPU_SOFT_RESET (ORION5X_BRIDGE_VIRT_BASE | 0x10c)
+
+#define POWER_MNG_CTRL_REG (ORION5X_BRIDGE_VIRT_BASE | 0x11C)
+
+#define BRIDGE_CAUSE (ORION5X_BRIDGE_VIRT_BASE | 0x110)
+#define WDT_INT_REQ 0x0008
+
+#define BRIDGE_MASK (ORION5X_BRIDGE_VIRT_BASE | 0x114)
+#define BRIDGE_INT_TIMER0 0x0002
+#define BRIDGE_INT_TIMER1 0x0004
+#define BRIDGE_INT_TIMER1_CLR (~0x0004)
+
+#define MAIN_IRQ_CAUSE (ORION5X_BRIDGE_VIRT_BASE | 0x200)
+
+#define MAIN_IRQ_MASK (ORION5X_BRIDGE_VIRT_BASE | 0x204)
+
+#define TIMER_VIRT_BASE (ORION5X_BRIDGE_VIRT_BASE | 0x300)
+
+#endif
diff --git a/arch/arm/mach-orion5x/include/mach/entry-macro.S b/arch/arm/mach-orion5x/include/mach/entry-macro.S
index 4351937035c..d658992e540 100644
--- a/arch/arm/mach-orion5x/include/mach/entry-macro.S
+++ b/arch/arm/mach-orion5x/include/mach/entry-macro.S
@@ -8,7 +8,7 @@
* warranty of any kind, whether express or implied.
*/
-#include <mach/orion5x.h>
+#include <mach/bridge-regs.h>
.macro disable_fiq
.endm
diff --git a/arch/arm/mach-orion5x/include/mach/orion5x.h b/arch/arm/mach-orion5x/include/mach/orion5x.h
index 67bda31406d..377a773ae53 100644
--- a/arch/arm/mach-orion5x/include/mach/orion5x.h
+++ b/arch/arm/mach-orion5x/include/mach/orion5x.h
@@ -61,30 +61,10 @@
#define ORION5X_PCI_MEM_SIZE SZ_128M
/*******************************************************************************
- * Supported Devices & Revisions
- ******************************************************************************/
-/* Orion-1 (88F5181) and Orion-VoIP (88F5181L) */
-#define MV88F5181_DEV_ID 0x5181
-#define MV88F5181_REV_B1 3
-#define MV88F5181L_REV_A0 8
-#define MV88F5181L_REV_A1 9
-/* Orion-NAS (88F5182) */
-#define MV88F5182_DEV_ID 0x5182
-#define MV88F5182_REV_A2 2
-/* Orion-2 (88F5281) */
-#define MV88F5281_DEV_ID 0x5281
-#define MV88F5281_REV_D0 4
-#define MV88F5281_REV_D1 5
-#define MV88F5281_REV_D2 6
-/* Orion-1-90 (88F6183) */
-#define MV88F6183_DEV_ID 0x6183
-#define MV88F6183_REV_B0 3
-
-/*******************************************************************************
* Orion Registers Map
******************************************************************************/
+
#define ORION5X_DDR_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x00000)
-#define ORION5X_DDR_REG(x) (ORION5X_DDR_VIRT_BASE | (x))
#define ORION5X_DEV_BUS_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x10000)
#define ORION5X_DEV_BUS_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x10000)
@@ -97,34 +77,25 @@
#define UART1_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE | 0x2100)
#define ORION5X_BRIDGE_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x20000)
-#define ORION5X_BRIDGE_REG(x) (ORION5X_BRIDGE_VIRT_BASE | (x))
-#define TIMER_VIRT_BASE (ORION5X_BRIDGE_VIRT_BASE | 0x300)
#define ORION5X_PCI_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x30000)
-#define ORION5X_PCI_REG(x) (ORION5X_PCI_VIRT_BASE | (x))
#define ORION5X_PCIE_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x40000)
-#define ORION5X_PCIE_REG(x) (ORION5X_PCIE_VIRT_BASE | (x))
#define ORION5X_USB0_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x50000)
#define ORION5X_USB0_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x50000)
-#define ORION5X_USB0_REG(x) (ORION5X_USB0_VIRT_BASE | (x))
#define ORION5X_XOR_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x60900)
#define ORION5X_XOR_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x60900)
-#define ORION5X_XOR_REG(x) (ORION5X_XOR_VIRT_BASE | (x))
#define ORION5X_ETH_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x70000)
#define ORION5X_ETH_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x70000)
-#define ORION5X_ETH_REG(x) (ORION5X_ETH_VIRT_BASE | (x))
#define ORION5X_SATA_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x80000)
#define ORION5X_SATA_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x80000)
-#define ORION5X_SATA_REG(x) (ORION5X_SATA_VIRT_BASE | (x))
#define ORION5X_USB1_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0xa0000)
#define ORION5X_USB1_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0xa0000)
-#define ORION5X_USB1_REG(x) (ORION5X_USB1_VIRT_BASE | (x))
/*******************************************************************************
* Device Bus Registers
@@ -142,23 +113,24 @@
#define DEV_BUS_INT_CAUSE ORION5X_DEV_BUS_REG(0x4d0)
#define DEV_BUS_INT_MASK ORION5X_DEV_BUS_REG(0x4d4)
-/***************************************************************************
- * Orion CPU Bridge Registers
- **************************************************************************/
-#define CPU_CONF ORION5X_BRIDGE_REG(0x100)
-#define CPU_CTRL ORION5X_BRIDGE_REG(0x104)
-#define CPU_RESET_MASK ORION5X_BRIDGE_REG(0x108)
-#define WDT_RESET 0x0002
-#define CPU_SOFT_RESET ORION5X_BRIDGE_REG(0x10c)
-#define POWER_MNG_CTRL_REG ORION5X_BRIDGE_REG(0x11C)
-#define BRIDGE_CAUSE ORION5X_BRIDGE_REG(0x110)
-#define WDT_INT_REQ 0x0008
-#define BRIDGE_MASK ORION5X_BRIDGE_REG(0x114)
-#define BRIDGE_INT_TIMER0 0x0002
-#define BRIDGE_INT_TIMER1 0x0004
-#define BRIDGE_INT_TIMER1_CLR (~0x0004)
-#define MAIN_IRQ_CAUSE ORION5X_BRIDGE_REG(0x200)
-#define MAIN_IRQ_MASK ORION5X_BRIDGE_REG(0x204)
-
+/*******************************************************************************
+ * Supported Devices & Revisions
+ ******************************************************************************/
+/* Orion-1 (88F5181) and Orion-VoIP (88F5181L) */
+#define MV88F5181_DEV_ID 0x5181
+#define MV88F5181_REV_B1 3
+#define MV88F5181L_REV_A0 8
+#define MV88F5181L_REV_A1 9
+/* Orion-NAS (88F5182) */
+#define MV88F5182_DEV_ID 0x5182
+#define MV88F5182_REV_A2 2
+/* Orion-2 (88F5281) */
+#define MV88F5281_DEV_ID 0x5281
+#define MV88F5281_REV_D0 4
+#define MV88F5281_REV_D1 5
+#define MV88F5281_REV_D2 6
+/* Orion-1-90 (88F6183) */
+#define MV88F6183_DEV_ID 0x6183
+#define MV88F6183_REV_B0 3
#endif
diff --git a/arch/arm/mach-orion5x/include/mach/system.h b/arch/arm/mach-orion5x/include/mach/system.h
index 9b8db1dcfa8..e912490fff2 100644
--- a/arch/arm/mach-orion5x/include/mach/system.h
+++ b/arch/arm/mach-orion5x/include/mach/system.h
@@ -11,8 +11,7 @@
#ifndef __ASM_ARCH_SYSTEM_H
#define __ASM_ARCH_SYSTEM_H
-#include <mach/hardware.h>
-#include <mach/orion5x.h>
+#include <mach/bridge-regs.h>
static inline void arch_idle(void)
{
diff --git a/arch/arm/mach-orion5x/irq.c b/arch/arm/mach-orion5x/irq.c
index e03f7b45cb0..d7512b925a8 100644
--- a/arch/arm/mach-orion5x/irq.c
+++ b/arch/arm/mach-orion5x/irq.c
@@ -15,7 +15,7 @@
#include <linux/irq.h>
#include <linux/io.h>
#include <asm/gpio.h>
-#include <mach/orion5x.h>
+#include <mach/bridge-regs.h>
#include <plat/irq.h>
#include "common.h"
diff --git a/arch/arm/mach-orion5x/mss2-setup.c b/arch/arm/mach-orion5x/mss2-setup.c
index 68acca98e63..41e6d5033d5 100644
--- a/arch/arm/mach-orion5x/mss2-setup.c
+++ b/arch/arm/mach-orion5x/mss2-setup.c
@@ -26,6 +26,7 @@
#include <asm/mach/arch.h>
#include <asm/mach/pci.h>
#include <mach/orion5x.h>
+#include <mach/bridge-regs.h>
#include "common.h"
#include "mpp.h"
diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c
index d0a785a3b88..36dc5413cc9 100644
--- a/arch/arm/mach-orion5x/pci.c
+++ b/arch/arm/mach-orion5x/pci.c
@@ -196,6 +196,7 @@ static int __init pcie_setup(struct pci_sys_data *sys)
/*****************************************************************************
* PCI controller
****************************************************************************/
+#define ORION5X_PCI_REG(x) (ORION5X_PCI_VIRT_BASE | (x))
#define PCI_MODE ORION5X_PCI_REG(0xd00)
#define PCI_CMD ORION5X_PCI_REG(0xc00)
#define PCI_P2P_CONF ORION5X_PCI_REG(0x1d14)
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-03 12:45:28 +0000