diff options
Diffstat (limited to 'arch/arm/mach-s5pc100/include')
| -rw-r--r-- | arch/arm/mach-s5pc100/include/mach/debug-macro.S | 38 | ||||
| -rw-r--r-- | arch/arm/mach-s5pc100/include/mach/entry-macro.S | 50 | ||||
| -rw-r--r-- | arch/arm/mach-s5pc100/include/mach/gpio-core.h | 21 | ||||
| -rw-r--r-- | arch/arm/mach-s5pc100/include/mach/gpio.h | 146 | ||||
| -rw-r--r-- | arch/arm/mach-s5pc100/include/mach/hardware.h | 14 | ||||
| -rw-r--r-- | arch/arm/mach-s5pc100/include/mach/irqs.h | 14 | ||||
| -rw-r--r-- | arch/arm/mach-s5pc100/include/mach/map.h | 75 | ||||
| -rw-r--r-- | arch/arm/mach-s5pc100/include/mach/memory.h | 18 | ||||
| -rw-r--r-- | arch/arm/mach-s5pc100/include/mach/pwm-clock.h | 56 | ||||
| -rw-r--r-- | arch/arm/mach-s5pc100/include/mach/regs-irq.h | 24 | ||||
| -rw-r--r-- | arch/arm/mach-s5pc100/include/mach/system.h | 24 | ||||
| -rw-r--r-- | arch/arm/mach-s5pc100/include/mach/tick.h | 29 | ||||
| -rw-r--r-- | arch/arm/mach-s5pc100/include/mach/uncompress.h | 28 |
13 files changed, 537 insertions, 0 deletions
diff --git a/arch/arm/mach-s5pc100/include/mach/debug-macro.S b/arch/arm/mach-s5pc100/include/mach/debug-macro.S new file mode 100644 index 00000000000..9d142ccf654 --- /dev/null +++ b/arch/arm/mach-s5pc100/include/mach/debug-macro.S @@ -0,0 +1,38 @@ +/* arch/arm/mach-s5pc100/include/mach/debug-macro.S + * + * Copyright 2009 Samsung Electronics Co. + * Byungho Min <bhmin@samsung.com> + * + * + * Based on mach-s3c6400/include/mach/debug-macro.S + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/* pull in the relevant register and map files. */ + +#include <mach/map.h> +#include <plat/regs-serial.h> + + /* note, for the boot process to work we have to keep the UART + * virtual address aligned to an 1MiB boundary for the L1 + * mapping the head code makes. We keep the UART virtual address + * aligned and add in the offset when we load the value here. + */ + + .macro addruart, rx + mrc p15, 0, \rx, c1, c0 + tst \rx, #1 + ldreq \rx, = S3C_PA_UART + ldrne \rx, = (S3C_VA_UART + S3C_PA_UART & 0xfffff) + add \rx, \rx, #(0x400 * CONFIG_DEBUG_S3C_UART) + .endm + +/* include the reset of the code which will do the work, we're only + * compiling for a single cpu processor type so the default of s3c2440 + * will be fine with us. + */ + +#include <plat/debug-macro.S> diff --git a/arch/arm/mach-s5pc100/include/mach/entry-macro.S b/arch/arm/mach-s5pc100/include/mach/entry-macro.S new file mode 100644 index 00000000000..67131939e62 --- /dev/null +++ b/arch/arm/mach-s5pc100/include/mach/entry-macro.S @@ -0,0 +1,50 @@ +/* arch/arm/mach-s5pc100/include/mach/entry-macro.S + * + * Copyright 2009 Samsung Electronics Co. + * Byungho Min <bhmin@samsung.com> + * + * Based on mach-s3c6400/include/mach/entry-macro.S + * + * Low-level IRQ helper macros for the Samsung S5PC1XX series + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. +*/ + +#include <asm/hardware/vic.h> +#include <mach/map.h> +#include <plat/irqs.h> + + .macro disable_fiq + .endm + + .macro get_irqnr_preamble, base, tmp + ldr \base, =S3C_VA_VIC0 + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + + @ check the vic0 + mov \irqnr, # S3C_IRQ_OFFSET + 31 + ldr \irqstat, [ \base, # VIC_IRQ_STATUS ] + teq \irqstat, #0 + + @ otherwise try vic1 + addeq \tmp, \base, #(S3C_VA_VIC1 - S3C_VA_VIC0) + addeq \irqnr, \irqnr, #32 + ldreq \irqstat, [ \tmp, # VIC_IRQ_STATUS ] + teqeq \irqstat, #0 + + @ otherwise try vic2 + addeq \tmp, \base, #(S3C_VA_VIC2 - S3C_VA_VIC0) + addeq \irqnr, \irqnr, #32 + ldreq \irqstat, [ \tmp, # VIC_IRQ_STATUS ] + teqeq \irqstat, #0 + + clzne \irqstat, \irqstat + subne \irqnr, \irqnr, \irqstat + .endm diff --git a/arch/arm/mach-s5pc100/include/mach/gpio-core.h b/arch/arm/mach-s5pc100/include/mach/gpio-core.h new file mode 100644 index 00000000000..ad28d8ec8a7 --- /dev/null +++ b/arch/arm/mach-s5pc100/include/mach/gpio-core.h @@ -0,0 +1,21 @@ +/* arch/arm/mach-s5pc100/include/mach/gpio-core.h + * + * Copyright 2009 Samsung Electronics Co. + * Byungho Min <bhmin@samsung.com> + * + * S5PC100 - GPIO core support + * + * Based on mach-s3c6400/include/mach/gpio-core.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_GPIO_CORE_H +#define __ASM_ARCH_GPIO_CORE_H __FILE__ + +/* currently we just include the platform support */ +#include <plat/gpio-core.h> + +#endif /* __ASM_ARCH_GPIO_CORE_H */ diff --git a/arch/arm/mach-s5pc100/include/mach/gpio.h b/arch/arm/mach-s5pc100/include/mach/gpio.h new file mode 100644 index 00000000000..c74fc93d7d1 --- /dev/null +++ b/arch/arm/mach-s5pc100/include/mach/gpio.h @@ -0,0 +1,146 @@ +/* arch/arm/mach-s5pc100/include/mach/gpio.h + * + * Copyright 2009 Samsung Electronics Co. + * Byungho Min <bhmin@samsung.com> + * + * S5PC100 - GPIO lib support + * + * Base on mach-s3c6400/include/mach/gpio.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#define gpio_get_value __gpio_get_value +#define gpio_set_value __gpio_set_value +#define gpio_cansleep __gpio_cansleep +#define gpio_to_irq __gpio_to_irq + +/* GPIO bank sizes */ +#define S5PC1XX_GPIO_A0_NR (8) +#define S5PC1XX_GPIO_A1_NR (5) +#define S5PC1XX_GPIO_B_NR (8) +#define S5PC1XX_GPIO_C_NR (5) +#define S5PC1XX_GPIO_D_NR (7) +#define S5PC1XX_GPIO_E0_NR (8) +#define S5PC1XX_GPIO_E1_NR (6) +#define S5PC1XX_GPIO_F0_NR (8) +#define S5PC1XX_GPIO_F1_NR (8) +#define S5PC1XX_GPIO_F2_NR (8) +#define S5PC1XX_GPIO_F3_NR (4) +#define S5PC1XX_GPIO_G0_NR (8) +#define S5PC1XX_GPIO_G1_NR (3) +#define S5PC1XX_GPIO_G2_NR (7) +#define S5PC1XX_GPIO_G3_NR (7) +#define S5PC1XX_GPIO_H0_NR (8) +#define S5PC1XX_GPIO_H1_NR (8) +#define S5PC1XX_GPIO_H2_NR (8) +#define S5PC1XX_GPIO_H3_NR (8) +#define S5PC1XX_GPIO_I_NR (8) +#define S5PC1XX_GPIO_J0_NR (8) +#define S5PC1XX_GPIO_J1_NR (5) +#define S5PC1XX_GPIO_J2_NR (8) +#define S5PC1XX_GPIO_J3_NR (8) +#define S5PC1XX_GPIO_J4_NR (4) +#define S5PC1XX_GPIO_K0_NR (8) +#define S5PC1XX_GPIO_K1_NR (6) +#define S5PC1XX_GPIO_K2_NR (8) +#define S5PC1XX_GPIO_K3_NR (8) +#define S5PC1XX_GPIO_MP00_NR (8) +#define S5PC1XX_GPIO_MP01_NR (8) +#define S5PC1XX_GPIO_MP02_NR (8) +#define S5PC1XX_GPIO_MP03_NR (8) +#define S5PC1XX_GPIO_MP04_NR (5) + +/* GPIO bank numbes */ + +/* CONFIG_S3C_GPIO_SPACE allows the user to select extra + * space for debugging purposes so that any accidental + * change from one gpio bank to another can be caught. +*/ + +#define S5PC1XX_GPIO_NEXT(__gpio) \ + ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1) + +enum s3c_gpio_number { + S5PC1XX_GPIO_A0_START = 0, + S5PC1XX_GPIO_A1_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_A0), + S5PC1XX_GPIO_B_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_A1), + S5PC1XX_GPIO_C_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_B), + S5PC1XX_GPIO_D_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_C), + S5PC1XX_GPIO_E0_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_D), + S5PC1XX_GPIO_E1_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_E0), + S5PC1XX_GPIO_F0_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_E1), + S5PC1XX_GPIO_F1_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_F0), + S5PC1XX_GPIO_F2_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_F1), + S5PC1XX_GPIO_F3_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_F2), + S5PC1XX_GPIO_G0_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_F3), + S5PC1XX_GPIO_G1_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_G0), + S5PC1XX_GPIO_G2_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_G1), + S5PC1XX_GPIO_G3_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_G2), + S5PC1XX_GPIO_H0_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_G3), + S5PC1XX_GPIO_H1_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_H0), + S5PC1XX_GPIO_H2_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_H1), + S5PC1XX_GPIO_H3_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_H2), + S5PC1XX_GPIO_I_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_H3), + S5PC1XX_GPIO_J0_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_I), + S5PC1XX_GPIO_J1_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_J0), + S5PC1XX_GPIO_J2_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_J1), + S5PC1XX_GPIO_J3_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_J2), + S5PC1XX_GPIO_J4_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_J3), + S5PC1XX_GPIO_K0_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_J4), + S5PC1XX_GPIO_K1_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_K0), + S5PC1XX_GPIO_K2_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_K1), + S5PC1XX_GPIO_K3_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_K2), + S5PC1XX_GPIO_MP00_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_K3), + S5PC1XX_GPIO_MP01_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_MP00), + S5PC1XX_GPIO_MP02_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_MP01), + S5PC1XX_GPIO_MP03_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_MP02), + S5PC1XX_GPIO_MP04_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_MP03), +}; + +/* S5PC1XX GPIO number definitions. */ +#define S5PC1XX_GPA0(_nr) (S5PC1XX_GPIO_A0_START + (_nr)) +#define S5PC1XX_GPA1(_nr) (S5PC1XX_GPIO_A1_START + (_nr)) +#define S5PC1XX_GPB(_nr) (S5PC1XX_GPIO_B_START + (_nr)) +#define S5PC1XX_GPC(_nr) (S5PC1XX_GPIO_C_START + (_nr)) +#define S5PC1XX_GPD(_nr) (S5PC1XX_GPIO_D_START + (_nr)) +#define S5PC1XX_GPE0(_nr) (S5PC1XX_GPIO_E0_START + (_nr)) +#define S5PC1XX_GPE1(_nr) (S5PC1XX_GPIO_E1_START + (_nr)) +#define S5PC1XX_GPF0(_nr) (S5PC1XX_GPIO_F0_START + (_nr)) +#define S5PC1XX_GPF1(_nr) (S5PC1XX_GPIO_F1_START + (_nr)) +#define S5PC1XX_GPF2(_nr) (S5PC1XX_GPIO_F2_START + (_nr)) +#define S5PC1XX_GPF3(_nr) (S5PC1XX_GPIO_F3_START + (_nr)) +#define S5PC1XX_GPG0(_nr) (S5PC1XX_GPIO_G0_START + (_nr)) +#define S5PC1XX_GPG1(_nr) (S5PC1XX_GPIO_G1_START + (_nr)) +#define S5PC1XX_GPG2(_nr) (S5PC1XX_GPIO_G2_START + (_nr)) +#define S5PC1XX_GPG3(_nr) (S5PC1XX_GPIO_G3_START + (_nr)) +#define S5PC1XX_GPH0(_nr) (S5PC1XX_GPIO_H0_START + (_nr)) +#define S5PC1XX_GPH1(_nr) (S5PC1XX_GPIO_H1_START + (_nr)) +#define S5PC1XX_GPH2(_nr) (S5PC1XX_GPIO_H2_START + (_nr)) +#define S5PC1XX_GPH3(_nr) (S5PC1XX_GPIO_H3_START + (_nr)) +#define S5PC1XX_GPI(_nr) (S5PC1XX_GPIO_I_START + (_nr)) +#define S5PC1XX_GPJ0(_nr) (S5PC1XX_GPIO_J0_START + (_nr)) +#define S5PC1XX_GPJ1(_nr) (S5PC1XX_GPIO_J1_START + (_nr)) +#define S5PC1XX_GPJ2(_nr) (S5PC1XX_GPIO_J2_START + (_nr)) +#define S5PC1XX_GPJ3(_nr) (S5PC1XX_GPIO_J3_START + (_nr)) +#define S5PC1XX_GPJ4(_nr) (S5PC1XX_GPIO_J4_START + (_nr)) +#define S5PC1XX_GPK0(_nr) (S5PC1XX_GPIO_K0_START + (_nr)) +#define S5PC1XX_GPK1(_nr) (S5PC1XX_GPIO_K1_START + (_nr)) +#define S5PC1XX_GPK2(_nr) (S5PC1XX_GPIO_K2_START + (_nr)) +#define S5PC1XX_GPK3(_nr) (S5PC1XX_GPIO_K3_START + (_nr)) +#define S5PC1XX_MP00(_nr) (S5PC1XX_GPIO_MP00_START + (_nr)) +#define S5PC1XX_MP01(_nr) (S5PC1XX_GPIO_MP01_START + (_nr)) +#define S5PC1XX_MP02(_nr) (S5PC1XX_GPIO_MP02_START + (_nr)) +#define S5PC1XX_MP03(_nr) (S5PC1XX_GPIO_MP03_START + (_nr)) +#define S5PC1XX_MP04(_nr) (S5PC1XX_GPIO_MP04_START + (_nr)) + +/* the end of the S5PC1XX specific gpios */ +#define S5PC1XX_GPIO_END (S5PC1XX_MP04(S5PC1XX_GPIO_MP04_NR) + 1) +#define S3C_GPIO_END S5PC1XX_GPIO_END + +/* define the number of gpios we need to the one after the MP04() range */ +#define ARCH_NR_GPIOS (S5PC1XX_MP04(S5PC1XX_GPIO_MP04_NR) + 1) + +#include <asm-generic/gpio.h> diff --git a/arch/arm/mach-s5pc100/include/mach/hardware.h b/arch/arm/mach-s5pc100/include/mach/hardware.h new file mode 100644 index 00000000000..6b38618c2fd --- /dev/null +++ b/arch/arm/mach-s5pc100/include/mach/hardware.h @@ -0,0 +1,14 @@ +/* linux/arch/arm/mach-s5pc100/include/mach/hardware.h + * + * Copyright 2009 Samsung Electronics Co. + * Byungho Min <bhmin@samsung.com> + * + * S5PC100 - Hardware support + */ + +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H __FILE__ + +/* currently nothing here, placeholder */ + +#endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/mach-s5pc100/include/mach/irqs.h b/arch/arm/mach-s5pc100/include/mach/irqs.h new file mode 100644 index 00000000000..622720dba28 --- /dev/null +++ b/arch/arm/mach-s5pc100/include/mach/irqs.h @@ -0,0 +1,14 @@ +/* linux/arch/arm/mach-s5pc100/include/mach/irqs.h + * + * Copyright 2009 Samsung Electronics Co. + * Byungho Min <bhmin@samsung.com> + * + * S5PC100 - IRQ definitions + */ + +#ifndef __ASM_ARCH_IRQS_H +#define __ASM_ARCH_IRQS_H __FILE__ + +#include <plat/irqs.h> + +#endif /* __ASM_ARCH_IRQ_H */ diff --git a/arch/arm/mach-s5pc100/include/mach/map.h b/arch/arm/mach-s5pc100/include/mach/map.h new file mode 100644 index 00000000000..9e9f39130b2 --- /dev/null +++ b/arch/arm/mach-s5pc100/include/mach/map.h @@ -0,0 +1,75 @@ +/* linux/arch/arm/mach-s5pc100/include/mach/map.h + * + * Copyright 2009 Samsung Electronics Co. + * Byungho Min <bhmin@samsung.com> + * + * Based on mach-s3c6400/include/mach/map.h + * + * S5PC1XX - Memory map definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_MAP_H +#define __ASM_ARCH_MAP_H __FILE__ + +#include <plat/map-base.h> + + +/* Chip ID */ +#define S5PC100_PA_CHIPID (0xE0000000) +#define S5PC1XX_PA_CHIPID S5PC100_PA_CHIPID +#define S5PC1XX_VA_CHIPID S3C_VA_SYS + +/* System */ +#define S5PC100_PA_SYS (0xE0100000) +#define S5PC100_PA_CLK (S5PC100_PA_SYS + 0x0) +#define S5PC100_PA_PWR (S5PC100_PA_SYS + 0x8000) +#define S5PC1XX_PA_CLK S5PC100_PA_CLK +#define S5PC1XX_PA_PWR S5PC100_PA_PWR +#define S5PC1XX_VA_CLK (S3C_VA_SYS + 0x10000) +#define S5PC1XX_VA_PWR (S3C_VA_SYS + 0x20000) + +/* Interrupt */ +#define S5PC100_PA_VIC (0xE4000000) +#define S5PC100_VA_VIC S3C_VA_IRQ +#define S5PC100_PA_VIC_OFFSET 0x100000 +#define S5PC100_VA_VIC_OFFSET 0x10000 +#define S5PC1XX_PA_VIC(x) (S5PC100_PA_VIC + ((x) * S5PC100_PA_VIC_OFFSET)) +#define S5PC1XX_VA_VIC(x) (S5PC100_VA_VIC + ((x) * S5PC100_VA_VIC_OFFSET)) + +/* Timer */ +#define S5PC100_PA_TIMER (0xEA000000) +#define S5PC1XX_PA_TIMER S5PC100_PA_TIMER +#define S5PC1XX_VA_TIMER S3C_VA_TIMER + +/* UART */ +#define S5PC100_PA_UART (0xEC000000) +#define S5PC1XX_PA_UART S5PC100_PA_UART +#define S5PC1XX_VA_UART S3C_VA_UART + +/* IIC */ +#define S5PC100_PA_IIC (0xEC100000) + +/* ETC */ +#define S5PC100_PA_SDRAM (0x20000000) + +/* compatibility defines. */ +#define S3C_PA_UART S5PC100_PA_UART +#define S3C_PA_UART0 (S5PC100_PA_UART + 0x0) +#define S3C_PA_UART1 (S5PC100_PA_UART + 0x400) +#define S3C_PA_UART2 (S5PC100_PA_UART + 0x800) +#define S3C_PA_UART3 (S5PC100_PA_UART + 0xC00) +#define S3C_VA_UART0 (S3C_VA_UART + 0x0) +#define S3C_VA_UART1 (S3C_VA_UART + 0x400) +#define S3C_VA_UART2 (S3C_VA_UART + 0x800) +#define S3C_VA_UART3 (S3C_VA_UART + 0xC00) +#define S3C_UART_OFFSET 0x400 +#define S3C_VA_VIC0 (S3C_VA_IRQ + 0x0) +#define S3C_VA_VIC1 (S3C_VA_IRQ + 0x10000) +#define S3C_VA_VIC2 (S3C_VA_IRQ + 0x20000) +#define S3C_PA_IIC S5PC100_PA_IIC + +#endif /* __ASM_ARCH_C100_MAP_H */ diff --git a/arch/arm/mach-s5pc100/include/mach/memory.h b/arch/arm/mach-s5pc100/include/mach/memory.h new file mode 100644 index 00000000000..4b60d18179f --- /dev/null +++ b/arch/arm/mach-s5pc100/include/mach/memory.h @@ -0,0 +1,18 @@ +/* arch/arm/mach-s5pc100/include/mach/memory.h + * + * Copyright 2008 Samsung Electronics Co. + * Byungho Min <bhmin@samsung.com> + * + * Based on mach-s3c6400/include/mach/memory.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_MEMORY_H +#define __ASM_ARCH_MEMORY_H + +#define PHYS_OFFSET UL(0x20000000) + +#endif diff --git a/arch/arm/mach-s5pc100/include/mach/pwm-clock.h b/arch/arm/mach-s5pc100/include/mach/pwm-clock.h new file mode 100644 index 00000000000..b34d2f7aae5 --- /dev/null +++ b/arch/arm/mach-s5pc100/include/mach/pwm-clock.h @@ -0,0 +1,56 @@ +/* linux/arch/arm/mach-s5pc100/include/mach/pwm-clock.h + * + * Copyright 2009 Samsung Electronics Co. + * Byungho Min <bhmin@samsung.com> + * + * S5PC100 - pwm clock and timer support + * + * Based on mach-s3c6400/include/mach/pwm-clock.h + */ + +/** + * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk + * @tcfg: The timer TCFG1 register bits shifted down to 0. + * + * Return true if the given configuration from TCFG1 is a TCLK instead + * any of the TDIV clocks. + */ +static inline int pwm_cfg_src_is_tclk(unsigned long tcfg) +{ + return tcfg >= S3C64XX_TCFG1_MUX_TCLK; +} + +/** + * tcfg_to_divisor() - convert tcfg1 setting to a divisor + * @tcfg1: The tcfg1 setting, shifted down. + * + * Get the divisor value for the given tcfg1 setting. We assume the + * caller has already checked to see if this is not a TCLK source. + */ +static inline unsigned long tcfg_to_divisor(unsigned long tcfg1) +{ + return 1 << tcfg1; +} + +/** + * pwm_tdiv_has_div1() - does the tdiv setting have a /1 + * + * Return true if we have a /1 in the tdiv setting. + */ +static inline unsigned int pwm_tdiv_has_div1(void) +{ + return 1; +} + +/** + * pwm_tdiv_div_bits() - calculate TCFG1 divisor value. + * @div: The divisor to calculate the bit information for. + * + * Turn a divisor into the necessary bit field for TCFG1. + */ +static inline unsigned long pwm_tdiv_div_bits(unsigned int div) +{ + return ilog2(div); +} + +#define S3C_TCFG1_MUX_TCLK S3C64XX_TCFG1_MUX_TCLK diff --git a/arch/arm/mach-s5pc100/include/mach/regs-irq.h b/arch/arm/mach-s5pc100/include/mach/regs-irq.h new file mode 100644 index 00000000000..751ac15438c --- /dev/null +++ b/arch/arm/mach-s5pc100/include/mach/regs-irq.h @@ -0,0 +1,24 @@ +/* linux/arch/arm/mach-s5pc100/include/mach/regs-irq.h + * + * Copyright 2009 Samsung Electronics Co. + * Byungho Min <bhmin@samsung.com> + * + * S5PC1XX - IRQ register definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_REGS_IRQ_H +#define __ASM_ARCH_REGS_IRQ_H __FILE__ + +#include <mach/map.h> +#include <asm/hardware/vic.h> + +/* interrupt controller */ +#define S5PC1XX_VIC0REG(x) ((x) + S5PC1XX_VA_VIC(0)) +#define S5PC1XX_VIC1REG(x) ((x) + S5PC1XX_VA_VIC(1)) +#define S5PC1XX_VIC2REG(x) ((x) + S5PC1XX_VA_VIC(2)) + +#endif /* __ASM_ARCH_REGS_IRQ_H */ diff --git a/arch/arm/mach-s5pc100/include/mach/system.h b/arch/arm/mach-s5pc100/include/mach/system.h new file mode 100644 index 00000000000..e3901437547 --- /dev/null +++ b/arch/arm/mach-s5pc100/include/mach/system.h @@ -0,0 +1,24 @@ +/* linux/arch/arm/mach-s5pc100/include/mach/system.h + * + * Copyright 2009 Samsung Electronics Co. + * Byungho Min <bhmin@samsung.com> + * + * S5PC1XX - system implementation + * + * Based on mach-s3c6400/include/mach/system.h + */ + +#ifndef __ASM_ARCH_SYSTEM_H +#define __ASM_ARCH_SYSTEM_H __FILE__ + +static void arch_idle(void) +{ + /* nothing here yet */ +} + +static void arch_reset(char mode, const char *cmd) +{ + /* nothing here yet */ +} + +#endif /* __ASM_ARCH_IRQ_H */ diff --git a/arch/arm/mach-s5pc100/include/mach/tick.h b/arch/arm/mach-s5pc100/include/mach/tick.h new file mode 100644 index 00000000000..d3de0f3591a --- /dev/null +++ b/arch/arm/mach-s5pc100/include/mach/tick.h @@ -0,0 +1,29 @@ +/* linux/arch/arm/mach-s5pc100/include/mach/tick.h + * + * Copyright 2009 Samsung Electronics Co. + * Byungho Min <bhmin@samsung.com> + * + * S3C64XX - Timer tick support definitions + * + * Based on mach-s3c6400/include/mach/tick.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_TICK_H +#define __ASM_ARCH_TICK_H __FILE__ + +/* note, the timer interrutps turn up in 2 places, the vic and then + * the timer block. We take the VIC as the base at the moment. + */ +static inline u32 s3c24xx_ostimer_pending(void) +{ + u32 pend = __raw_readl(S3C_VA_VIC0 + VIC_RAW_STATUS); + return pend & 1 << (IRQ_TIMER4 - S5PC1XX_IRQ_VIC0(0)); +} + +#define TICK_MAX (0xffffffff) + +#endif /* __ASM_ARCH_TICK_H */ diff --git a/arch/arm/mach-s5pc100/include/mach/uncompress.h b/arch/arm/mach-s5pc100/include/mach/uncompress.h new file mode 100644 index 00000000000..01ccf535e76 --- /dev/null +++ b/arch/arm/mach-s5pc100/include/mach/uncompress.h @@ -0,0 +1,28 @@ +/* arch/arm/mach-s5pc100/include/mach/uncompress.h + * + * Copyright 2009 Samsung Electronics Co. + * Byungho Min <bhmin@samsung.com> + * + * S5PC100 - uncompress code + * + * Based on mach-s3c6400/include/mach/uncompress.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_UNCOMPRESS_H +#define __ASM_ARCH_UNCOMPRESS_H + +#include <mach/map.h> +#include <plat/uncompress.h> + +static void arch_detect_cpu(void) +{ + /* we do not need to do any cpu detection here at the moment. */ + fifo_mask = S3C2440_UFSTAT_TXMASK; + fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT; +} + +#endif /* __ASM_ARCH_UNCOMPRESS_H */ |