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-rw-r--r--arch/mips/mm/page.c10
-rw-r--r--arch/mips/mm/tlbex.c3
2 files changed, 8 insertions, 5 deletions
diff --git a/arch/mips/mm/page.c b/arch/mips/mm/page.c
index d827d614436..cab81f42eee 100644
--- a/arch/mips/mm/page.c
+++ b/arch/mips/mm/page.c
@@ -310,8 +310,8 @@ void __cpuinit build_clear_page(void)
if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())
uasm_i_lui(&buf, AT, 0xa000);
- off = min(8, pref_bias_clear_store / cache_line_size) *
- cache_line_size;
+ off = cache_line_size ? min(8, pref_bias_clear_store / cache_line_size)
+ * cache_line_size : 0;
while (off) {
build_clear_pref(&buf, -off);
off -= cache_line_size;
@@ -454,12 +454,14 @@ void __cpuinit build_copy_page(void)
if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())
uasm_i_lui(&buf, AT, 0xa000);
- off = min(8, pref_bias_copy_load / cache_line_size) * cache_line_size;
+ off = cache_line_size ? min(8, pref_bias_copy_load / cache_line_size) *
+ cache_line_size : 0;
while (off) {
build_copy_load_pref(&buf, -off);
off -= cache_line_size;
}
- off = min(8, pref_bias_copy_store / cache_line_size) * cache_line_size;
+ off = cache_line_size ? min(8, pref_bias_copy_load / cache_line_size) *
+ cache_line_size : 0;
while (off) {
build_copy_store_pref(&buf, -off);
off -= cache_line_size;
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 382738ca8a0..76da73a5ab3 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -224,8 +224,9 @@ static u32 final_handler[64] __cpuinitdata;
static void __cpuinit __maybe_unused build_tlb_probe_entry(u32 **p)
{
switch (current_cpu_type()) {
- /* Found by experiment: R4600 v2.0 needs this, too. */
+ /* Found by experiment: R4600 v2.0/R4700 needs this, too. */
case CPU_R4600:
+ case CPU_R4700:
case CPU_R5000:
case CPU_R5000A:
case CPU_NEVADA: