diff options
Diffstat (limited to 'arch/powerpc/boot/dts')
| -rw-r--r-- | arch/powerpc/boot/dts/kuroboxHG.dts | 148 | ||||
| -rw-r--r-- | arch/powerpc/boot/dts/lite5200.dts | 313 | ||||
| -rw-r--r-- | arch/powerpc/boot/dts/lite5200b.dts | 318 | ||||
| -rw-r--r-- | arch/powerpc/boot/dts/mpc7448hpc2.dts | 44 |
4 files changed, 807 insertions, 16 deletions
diff --git a/arch/powerpc/boot/dts/kuroboxHG.dts b/arch/powerpc/boot/dts/kuroboxHG.dts new file mode 100644 index 00000000000..d06b0b01889 --- /dev/null +++ b/arch/powerpc/boot/dts/kuroboxHG.dts @@ -0,0 +1,148 @@ +/* + * Device Tree Souce for Buffalo KuroboxHG + * + * Choose CONFIG_LINKSTATION to build a kernel for KuroboxHG, or use + * the default configuration linkstation_defconfig. + * + * Based on sandpoint.dts + * + * 2006 (c) G. Liakhovetski <g.liakhovetski@gmx.de> + * + * This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + +XXXX add flash parts, rtc, ?? + +build with: "dtc -f -I dts -O dtb -o kuroboxHG.dtb -V 16 kuroboxHG.dts" + + + */ + +/ { + linux,phandle = <1000>; + model = "KuroboxHG"; + compatible = "linkstation"; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + linux,phandle = <2000>; + #cpus = <1>; + #address-cells = <1>; + #size-cells = <0>; + + PowerPC,603e { /* Really 8241 */ + linux,phandle = <2100>; + linux,boot-cpu; + device_type = "cpu"; + reg = <0>; + clock-frequency = <fdad680>; /* Fixed by bootwrapper */ + timebase-frequency = <1F04000>; /* Fixed by bootwrapper */ + bus-frequency = <0>; /* From bootloader */ + /* Following required by dtc but not used */ + i-cache-line-size = <0>; + d-cache-line-size = <0>; + i-cache-size = <4000>; + d-cache-size = <4000>; + }; + }; + + memory { + linux,phandle = <3000>; + device_type = "memory"; + reg = <00000000 08000000>; + }; + + soc10x { /* AFAICT need to make soc for 8245's uarts to be defined */ + linux,phandle = <4000>; + #address-cells = <1>; + #size-cells = <1>; + #interrupt-cells = <2>; + device_type = "soc"; + compatible = "mpc10x"; + store-gathering = <0>; /* 0 == off, !0 == on */ + reg = <80000000 00100000>; + ranges = <80000000 80000000 70000000 /* pci mem space */ + fc000000 fc000000 00100000 /* EUMB */ + fe000000 fe000000 00c00000 /* pci i/o space */ + fec00000 fec00000 00300000 /* pci cfg regs */ + fef00000 fef00000 00100000>; /* pci iack */ + + i2c@80003000 { + linux,phandle = <4300>; + device_type = "i2c"; + compatible = "fsl-i2c"; + reg = <80003000 1000>; + interrupts = <5 2>; + interrupt-parent = <4400>; + }; + + serial@80004500 { + linux,phandle = <4511>; + device_type = "serial"; + compatible = "ns16550"; + reg = <80004500 8>; + clock-frequency = <7c044a8>; + current-speed = <2580>; + interrupts = <9 2>; + interrupt-parent = <4400>; + }; + + serial@80004600 { + linux,phandle = <4512>; + device_type = "serial"; + compatible = "ns16550"; + reg = <80004600 8>; + clock-frequency = <7c044a8>; + current-speed = <e100>; + interrupts = <a 0>; + interrupt-parent = <4400>; + }; + + pic@80040000 { + linux,phandle = <4400>; + #interrupt-cells = <2>; + #address-cells = <0>; + device_type = "open-pic"; + compatible = "chrp,open-pic"; + interrupt-controller; + reg = <80040000 40000>; + built-in; + }; + + pci@fec00000 { + linux,phandle = <4500>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + compatible = "mpc10x-pci"; + reg = <fec00000 400000>; + ranges = <01000000 0 0 fe000000 0 00c00000 + 02000000 0 80000000 80000000 0 70000000>; + bus-range = <0 ff>; + clock-frequency = <7f28155>; + interrupt-parent = <4400>; + interrupt-map-mask = <f800 0 0 7>; + interrupt-map = < + /* IDSEL 0x11 - IRQ0 ETH */ + 5800 0 0 1 4400 0 1 + 5800 0 0 2 4400 1 1 + 5800 0 0 3 4400 2 1 + 5800 0 0 4 4400 3 1 + /* IDSEL 0x12 - IRQ1 IDE0 */ + 6000 0 0 1 4400 1 1 + 6000 0 0 2 4400 2 1 + 6000 0 0 3 4400 3 1 + 6000 0 0 4 4400 0 1 + /* IDSEL 0x14 - IRQ3 USB2.0 */ + 7000 0 0 1 4400 3 1 + 7000 0 0 2 4400 3 1 + 7000 0 0 3 4400 3 1 + 7000 0 0 4 4400 3 1 + >; + }; + }; +}; diff --git a/arch/powerpc/boot/dts/lite5200.dts b/arch/powerpc/boot/dts/lite5200.dts new file mode 100644 index 00000000000..8bc0d259796 --- /dev/null +++ b/arch/powerpc/boot/dts/lite5200.dts @@ -0,0 +1,313 @@ +/* + * Lite5200 board Device Tree Source + * + * Copyright 2006 Secret Lab Technologies Ltd. + * Grant Likely <grant.likely@secretlab.ca> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +/ { + model = "Lite5200"; + compatible = "lite5200\0lite52xx\0mpc5200\0mpc52xx"; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #cpus = <1>; + #address-cells = <1>; + #size-cells = <0>; + + PowerPC,5200@0 { + device_type = "cpu"; + reg = <0>; + d-cache-line-size = <20>; + i-cache-line-size = <20>; + d-cache-size = <4000>; // L1, 16K + i-cache-size = <4000>; // L1, 16K + timebase-frequency = <0>; // from bootloader + bus-frequency = <0>; // from bootloader + clock-frequency = <0>; // from bootloader + 32-bit; + }; + }; + + memory { + device_type = "memory"; + reg = <00000000 04000000>; // 64MB + }; + + soc5200@f0000000 { + #interrupt-cells = <3>; + device_type = "soc"; + ranges = <0 f0000000 f0010000>; + reg = <f0000000 00010000>; + bus-frequency = <0>; // from bootloader + + cdm@200 { + compatible = "mpc5200-cdm\0mpc52xx-cdm"; + reg = <200 38>; + }; + + pic@500 { + // 5200 interrupts are encoded into two levels; + linux,phandle = <500>; + interrupt-controller; + #interrupt-cells = <3>; + device_type = "interrupt-controller"; + compatible = "mpc5200-pic\0mpc52xx-pic"; + reg = <500 80>; + built-in; + }; + + gpt@600 { // General Purpose Timer + compatible = "mpc5200-gpt\0mpc52xx-gpt"; + device_type = "gpt"; + reg = <600 10>; + interrupts = <1 9 0>; + interrupt-parent = <500>; + }; + + gpt@610 { // General Purpose Timer + compatible = "mpc5200-gpt\0mpc52xx-gpt"; + device_type = "gpt"; + reg = <610 10>; + interrupts = <1 a 0>; + interrupt-parent = <500>; + }; + + gpt@620 { // General Purpose Timer + compatible = "mpc5200-gpt\0mpc52xx-gpt"; + device_type = "gpt"; + reg = <620 10>; + interrupts = <1 b 0>; + interrupt-parent = <500>; + }; + + gpt@630 { // General Purpose Timer + compatible = "mpc5200-gpt\0mpc52xx-gpt"; + device_type = "gpt"; + reg = <630 10>; + interrupts = <1 c 0>; + interrupt-parent = <500>; + }; + + gpt@640 { // General Purpose Timer + compatible = "mpc5200-gpt\0mpc52xx-gpt"; + device_type = "gpt"; + reg = <640 10>; + interrupts = <1 d 0>; + interrupt-parent = <500>; + }; + + gpt@650 { // General Purpose Timer + compatible = "mpc5200-gpt\0mpc52xx-gpt"; + device_type = "gpt"; + reg = <650 10>; + interrupts = <1 e 0>; + interrupt-parent = <500>; + }; + + gpt@660 { // General Purpose Timer + compatible = "mpc5200-gpt\0mpc52xx-gpt"; + device_type = "gpt"; + reg = <660 10>; + interrupts = <1 f 0>; + interrupt-parent = <500>; + }; + + gpt@670 { // General Purpose Timer + compatible = "mpc5200-gpt\0mpc52xx-gpt"; + device_type = "gpt"; + reg = <670 10>; + interrupts = <1 10 0>; + interrupt-parent = <500>; + }; + + rtc@800 { // Real time clock + compatible = "mpc5200-rtc\0mpc52xx-rtc"; + device_type = "rtc"; + reg = <800 100>; + interrupts = <1 5 0 1 6 0>; + interrupt-parent = <500>; + }; + + mscan@900 { + device_type = "mscan"; + compatible = "mpc5200-mscan\0mpc52xx-mscan"; + interrupts = <2 11 0>; + interrupt-parent = <500>; + reg = <900 80>; + }; + + mscan@980 { + device_type = "mscan"; + compatible = "mpc5200-mscan\0mpc52xx-mscan"; + interrupts = <1 12 0>; + interrupt-parent = <500>; + reg = <980 80>; + }; + + gpio@b00 { + compatible = "mpc5200-gpio\0mpc52xx-gpio"; + reg = <b00 40>; + interrupts = <1 7 0>; + interrupt-parent = <500>; + }; + + gpio-wkup@b00 { + compatible = "mpc5200-gpio-wkup\0mpc52xx-gpio-wkup"; + reg = <c00 40>; + interrupts = <1 8 0 0 3 0>; + interrupt-parent = <500>; + }; + + pci@0d00 { + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + compatible = "mpc5200-pci\0mpc52xx-pci"; + reg = <d00 100>; + interrupt-map-mask = <f800 0 0 7>; + interrupt-map = <c000 0 0 1 500 0 0 3 + c000 0 0 2 500 0 0 3 + c000 0 0 3 500 0 0 3 + c000 0 0 4 500 0 0 3>; + clock-frequency = <0>; // From boot loader + interrupts = <2 8 0 2 9 0 2 a 0>; + interrupt-parent = <500>; + bus-range = <0 0>; + ranges = <42000000 0 80000000 80000000 0 20000000 + 02000000 0 a0000000 a0000000 0 10000000 + 01000000 0 00000000 b0000000 0 01000000>; + }; + + spi@f00 { + device_type = "spi"; + compatible = "mpc5200-spi\0mpc52xx-spi"; + reg = <f00 20>; + interrupts = <2 d 0 2 e 0>; + interrupt-parent = <500>; + }; + + usb@1000 { + device_type = "usb-ohci-be"; + compatible = "mpc5200-ohci\0mpc52xx-ohci\0ohci-be"; + reg = <1000 ff>; + interrupts = <2 6 0>; + interrupt-parent = <500>; + }; + + bestcomm@1200 { + device_type = "dma-controller"; + compatible = "mpc5200-bestcomm\0mpc52xx-bestcomm"; + reg = <1200 80>; + interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 + 3 4 0 3 5 0 3 6 0 3 7 0 + 3 8 0 3 9 0 3 a 0 3 b 0 + 3 c 0 3 d 0 3 e 0 3 f 0>; + interrupt-parent = <500>; + }; + + xlb@1f00 { + compatible = "mpc5200-xlb\0mpc52xx-xlb"; + reg = <1f00 100>; + }; + + serial@2000 { // PSC1 + device_type = "serial"; + compatible = "mpc5200-psc-uart\0mpc52xx-psc-uart"; + port-number = <0>; // Logical port assignment + reg = <2000 100>; + interrupts = <2 1 0>; + interrupt-parent = <500>; + }; + + // PSC2 in spi mode example + spi@2200 { // PSC2 + device_type = "spi"; + compatible = "mpc5200-psc-spi\0mpc52xx-psc-spi"; + reg = <2200 100>; + interrupts = <2 2 0>; + interrupt-parent = <500>; + }; + + // PSC3 in CODEC mode example + i2s@2400 { // PSC3 + device_type = "i2s"; + compatible = "mpc5200-psc-i2s\0mpc52xx-psc-i2s"; + reg = <2400 100>; + interrupts = <2 3 0>; + interrupt-parent = <500>; + }; + + // PSC4 unconfigured + //serial@2600 { // PSC4 + // device_type = "serial"; + // compatible = "mpc5200-psc-uart\0mpc52xx-psc-uart"; + // reg = <2600 100>; + // interrupts = <2 b 0>; + // interrupt-parent = <500>; + //}; + + // PSC5 unconfigured + //serial@2800 { // PSC5 + // device_type = "serial"; + // compatible = "mpc5200-psc-uart\0mpc52xx-psc-uart"; + // reg = <2800 100>; + // interrupts = <2 c 0>; + // interrupt-parent = <500>; + //}; + + // PSC6 in AC97 mode example + ac97@2c00 { // PSC6 + device_type = "ac97"; + compatible = "mpc5200-psc-ac97\0mpc52xx-psc-ac97"; + reg = <2c00 100>; + interrupts = <2 4 0>; + interrupt-parent = <500>; + }; + + ethernet@3000 { + device_type = "network"; + compatible = "mpc5200-fec\0mpc52xx-fec"; + reg = <3000 800>; + mac-address = [ 02 03 04 05 06 07 ]; // Bad! + interrupts = <2 5 0>; + interrupt-parent = <500>; + }; + + ata@3a00 { + device_type = "ata"; + compatible = "mpc5200-ata\0mpc52xx-ata"; + reg = <3a00 100>; + interrupts = <2 7 0>; + interrupt-parent = <500>; + }; + + i2c@3d00 { + device_type = "i2c"; + compatible = "mpc5200-i2c\0mpc52xx-i2c"; + reg = <3d00 40>; + interrupts = <2 f 0>; + interrupt-parent = <500>; + }; + + i2c@3d40 { + device_type = "i2c"; + compatible = "mpc5200-i2c\0mpc52xx-i2c"; + reg = <3d40 40>; + interrupts = <2 10 0>; + interrupt-parent = <500>; + }; + sram@8000 { + device_type = "sram"; + compatible = "mpc5200-sram\0mpc52xx-sram\0sram"; + reg = <8000 4000>; + }; + }; +}; diff --git a/arch/powerpc/boot/dts/lite5200b.dts b/arch/powerpc/boot/dts/lite5200b.dts new file mode 100644 index 00000000000..81cb76418a7 --- /dev/null +++ b/arch/powerpc/boot/dts/lite5200b.dts @@ -0,0 +1,318 @@ +/* + * Lite5200B board Device Tree Source + * + * Copyright 2006 Secret Lab Technologies Ltd. + * Grant Likely <grant.likely@secretlab.ca> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +/ { + model = "Lite5200b"; + compatible = "lite5200b\0lite52xx\0mpc5200b\0mpc52xx"; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #cpus = <1>; + #address-cells = <1>; + #size-cells = <0>; + + PowerPC,5200@0 { + device_type = "cpu"; + reg = <0>; + d-cache-line-size = <20>; + i-cache-line-size = <20>; + d-cache-size = <4000>; // L1, 16K + i-cache-size = <4000>; // L1, 16K + timebase-frequency = <0>; // from bootloader + bus-frequency = <0>; // from bootloader + clock-frequency = <0>; // from bootloader + 32-bit; + }; + }; + + memory { + device_type = "memory"; + reg = <00000000 10000000>; // 256MB + }; + + soc5200@f0000000 { + #interrupt-cells = <3>; + device_type = "soc"; + ranges = <0 f0000000 f0010000>; + reg = <f0000000 00010000>; + bus-frequency = <0>; // from bootloader + + cdm@200 { + compatible = "mpc5200b-cdm\0mpc52xx-cdm"; + reg = <200 38>; + }; + + pic@500 { + // 5200 interrupts are encoded into two levels; + linux,phandle = <500>; + interrupt-controller; + #interrupt-cells = <3>; + device_type = "interrupt-controller"; + compatible = "mpc5200b-pic\0mpc52xx-pic"; + reg = <500 80>; + built-in; + }; + + gpt@600 { // General Purpose Timer + compatible = "mpc5200b-gpt\0mpc52xx-gpt"; + device_type = "gpt"; + reg = <600 10>; + interrupts = <1 9 0>; + interrupt-parent = <500>; + }; + + gpt@610 { // General Purpose Timer + compatible = "mpc5200b-gpt\0mpc52xx-gpt"; + device_type = "gpt"; + reg = <610 10>; + interrupts = <1 a 0>; + interrupt-parent = <500>; + }; + + gpt@620 { // General Purpose Timer + compatible = "mpc5200b-gpt\0mpc52xx-gpt"; + device_type = "gpt"; + reg = <620 10>; + interrupts = <1 b 0>; + interrupt-parent = <500>; + }; + + gpt@630 { // General Purpose Timer + compatible = "mpc5200b-gpt\0mpc52xx-gpt"; + device_type = "gpt"; + reg = <630 10>; + interrupts = <1 c 0>; + interrupt-parent = <500>; + }; + + gpt@640 { // General Purpose Timer + compatible = "mpc5200b-gpt\0mpc52xx-gpt"; + device_type = "gpt"; + reg = <640 10>; + interrupts = <1 d 0>; + interrupt-parent = <500>; + }; + + gpt@650 { // General Purpose Timer + compatible = "mpc5200b-gpt\0mpc52xx-gpt"; + device_type = "gpt"; + reg = <650 10>; + interrupts = <1 e 0>; + interrupt-parent = <500>; + }; + + gpt@660 { // General Purpose Timer + compatible = "mpc5200b-gpt\0mpc52xx-gpt"; + device_type = "gpt"; + reg = <660 10>; + interrupts = <1 f 0>; + interrupt-parent = <500>; + }; + + gpt@670 { // General Purpose Timer + compatible = "mpc5200b-gpt\0mpc52xx-gpt"; + device_type = "gpt"; + reg = <670 10>; + interrupts = <1 10 0>; + interrupt-parent = <500>; + }; + + rtc@800 { // Real time clock + compatible = "mpc5200b-rtc\0mpc52xx-rtc"; + device_type = "rtc"; + reg = <800 100>; + interrupts = <1 5 0 1 6 0>; + interrupt-parent = <500>; + }; + + mscan@900 { + device_type = "mscan"; + compatible = "mpc5200b-mscan\0mpc52xx-mscan"; + interrupts = <2 11 0>; + interrupt-parent = <500>; + reg = <900 80>; + }; + + mscan@980 { + device_type = "mscan"; + compatible = "mpc5200b-mscan\0mpc52xx-mscan"; + interrupts = <1 12 0>; + interrupt-parent = <500>; + reg = <980 80>; + }; + + gpio@b00 { + compatible = "mpc5200b-gpio\0mpc52xx-gpio"; + reg = <b00 40>; + interrupts = <1 7 0>; + interrupt-parent = <500>; + }; + + gpio-wkup@b00 { + compatible = "mpc5200b-gpio-wkup\0mpc52xx-gpio-wkup"; + reg = <c00 40>; + interrupts = <1 8 0 0 3 0>; + interrupt-parent = <500>; + }; + + pci@0d00 { + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + compatible = "mpc5200b-pci\0mpc52xx-pci"; + reg = <d00 100>; + interrupt-map-mask = <f800 0 0 7>; + interrupt-map = <c000 0 0 1 500 0 0 3 // 1st slot + c000 0 0 2 500 1 1 3 + c000 0 0 3 500 1 2 3 + c000 0 0 4 500 1 3 3 + + c800 0 0 1 500 1 1 3 // 2nd slot + c800 0 0 2 500 1 2 3 + c800 0 0 3 500 1 3 3 + c800 0 0 4 500 0 0 3>; + clock-frequency = <0>; // From boot loader + interrupts = <2 8 0 2 9 0 2 a 0>; + interrupt-parent = <500>; + bus-range = <0 0>; + ranges = <42000000 0 80000000 80000000 0 20000000 + 02000000 0 a0000000 a0000000 0 10000000 + 01000000 0 00000000 b0000000 0 01000000>; + }; + + spi@f00 { + device_type = "spi"; + compatible = "mpc5200b-spi\0mpc52xx-spi"; + reg = <f00 20>; + interrupts = <2 d 0 2 e 0>; + interrupt-parent = <500>; + }; + + usb@1000 { + device_type = "usb-ohci-be"; + compatible = "mpc5200b-ohci\0mpc52xx-ohci\0ohci-be"; + reg = <1000 ff>; + interrupts = <2 6 0>; + interrupt-parent = <500>; + }; + + bestcomm@1200 { + device_type = "dma-controller"; + compatible = "mpc5200b-bestcomm\0mpc52xx-bestcomm"; + reg = <1200 80>; + interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 + 3 4 0 3 5 0 3 6 0 3 7 0 + 3 8 0 3 9 0 3 a 0 3 b 0 + 3 c 0 3 d 0 3 e 0 3 f 0>; + interrupt-parent = <500>; + }; + + xlb@1f00 { + compatible = "mpc5200b-xlb\0mpc52xx-xlb"; + reg = <1f00 100>; + }; + + serial@2000 { // PSC1 + device_type = "serial"; + compatible = "mpc5200b-psc-uart\0mpc52xx-psc-uart"; + port-number = <0>; // Logical port assignment + reg = <2000 100>; + interrupts = <2 1 0>; + interrupt-parent = <500>; + }; + + // PSC2 in spi mode example + spi@2200 { // PSC2 + device_type = "spi"; + compatible = "mpc5200b-psc-spi\0mpc52xx-psc-spi"; + reg = <2200 100>; + interrupts = <2 2 0>; + interrupt-parent = <500>; + }; + + // PSC3 in CODEC mode example + i2s@2400 { // PSC3 + device_type = "i2s"; + compatible = "mpc5200b-psc-i2s\0mpc52xx-psc-i2s"; + reg = <2400 100>; + interrupts = <2 3 0>; + interrupt-parent = <500>; + }; + + // PSC4 unconfigured + //serial@2600 { // PSC4 + // device_type = "serial"; + // compatible = "mpc5200b-psc-uart\0mpc52xx-psc-uart"; + // reg = <2600 100>; + // interrupts = <2 b 0>; + // interrupt-parent = <500>; + //}; + + // PSC5 unconfigured + //serial@2800 { // PSC5 + // device_type = "serial"; + // compatible = "mpc5200b-psc-uart\0mpc52xx-psc-uart"; + // reg = <2800 100>; + // interrupts = <2 c 0>; + // interrupt-parent = <500>; + //}; + + // PSC6 in AC97 mode example + ac97@2c00 { // PSC6 + device_type = "ac97"; + compatible = "mpc5200b-psc-ac97\0mpc52xx-psc-ac97"; + reg = <2c00 100>; + interrupts = <2 4 0>; + interrupt-parent = <500>; + }; + + ethernet@3000 { + device_type = "network"; + compatible = "mpc5200b-fec\0mpc52xx-fec"; + reg = <3000 800>; + mac-address = [ 02 03 04 05 06 07 ]; // Bad! + interrupts = <2 5 0>; + interrupt-parent = <500>; + }; + + ata@3a00 { + device_type = "ata"; + compatible = "mpc5200b-ata\0mpc52xx-ata"; + reg = <3a00 100>; + interrupts = <2 7 0>; + interrupt-parent = <500>; + }; + + i2c@3d00 { + device_type = "i2c"; + compatible = "mpc5200b-i2c\0mpc52xx-i2c"; + reg = <3d00 40>; + interrupts = <2 f 0>; + interrupt-parent = <500>; + }; + + i2c@3d40 { + device_type = "i2c"; + compatible = "mpc5200b-i2c\0mpc52xx-i2c"; + reg = <3d40 40>; + interrupts = <2 10 0>; + interrupt-parent = <500>; + }; + sram@8000 { + device_type = "sram"; + compatible = "mpc5200b-sram\0mpc52xx-sram\0sram"; + reg = <8000 4000>; + }; + }; +}; diff --git a/arch/powerpc/boot/dts/mpc7448hpc2.dts b/arch/powerpc/boot/dts/mpc7448hpc2.dts index d7b985e6bd2..c4d9562cbaa 100644 --- a/arch/powerpc/boot/dts/mpc7448hpc2.dts +++ b/arch/powerpc/boot/dts/mpc7448hpc2.dts @@ -161,29 +161,41 @@ interrupt-map = < /* IDSEL 0x11 */ - 0800 0 0 1 7400 24 0 - 0800 0 0 2 7400 25 0 - 0800 0 0 3 7400 26 0 - 0800 0 0 4 7400 27 0 + 0800 0 0 1 1180 24 0 + 0800 0 0 2 1180 25 0 + 0800 0 0 3 1180 26 0 + 0800 0 0 4 1180 27 0 /* IDSEL 0x12 */ - 1000 0 0 1 7400 25 0 - 1000 0 0 2 7400 26 0 - 1000 0 0 3 7400 27 0 - 1000 0 0 4 7400 24 0 + 1000 0 0 1 1180 25 0 + 1000 0 0 2 1180 26 0 + 1000 0 0 3 1180 27 0 + 1000 0 0 4 1180 24 0 /* IDSEL 0x13 */ - 1800 0 0 1 7400 26 0 - 1800 0 0 2 7400 27 0 - 1800 0 0 3 7400 24 0 - 1800 0 0 4 7400 25 0 + 1800 0 0 1 1180 26 0 + 1800 0 0 2 1180 27 0 + 1800 0 0 3 1180 24 0 + 1800 0 0 4 1180 25 0 /* IDSEL 0x14 */ - 2000 0 0 1 7400 27 0 - 2000 0 0 2 7400 24 0 - 2000 0 0 3 7400 25 0 - 2000 0 0 4 7400 26 0 + 2000 0 0 1 1180 27 0 + 2000 0 0 2 1180 24 0 + 2000 0 0 3 1180 25 0 + 2000 0 0 4 1180 26 0 >; + router@1180 { + linux,phandle = <1180>; + clock-frequency = <0>; + interrupt-controller; + device_type = "pic-router"; + #address-cells = <0>; + #interrupt-cells = <2>; + built-in; + big-endian; + interrupts = <17 2>; + interrupt-parent = <7400>; + }; }; }; |