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-rw-r--r--arch/sh/boards/se/7343/irq.c232
-rw-r--r--arch/sh/boards/se/7343/setup.c70
2 files changed, 119 insertions, 183 deletions
diff --git a/arch/sh/boards/se/7343/irq.c b/arch/sh/boards/se/7343/irq.c
index 763f6deba81..1112e86aa93 100644
--- a/arch/sh/boards/se/7343/irq.c
+++ b/arch/sh/boards/se/7343/irq.c
@@ -1,202 +1,80 @@
/*
- * arch/sh/boards/se/7343/irq.c
+ * linux/arch/sh/boards/se/7343/irq.c
*
+ * Copyright (C) 2008 Yoshihiro Shimoda
+ *
+ * Based on linux/arch/sh/boards/se/7722/irq.c
+ * Copyright (C) 2007 Nobuhiro Iwamatsu
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
*/
#include <linux/init.h>
-#include <linux/interrupt.h>
#include <linux/irq.h>
+#include <linux/interrupt.h>
#include <asm/irq.h>
#include <asm/io.h>
-#include <asm/mach/se7343.h>
+#include <asm/se7343.h>
-static void
-disable_intreq_irq(unsigned int irq)
+static void disable_se7343_irq(unsigned int irq)
{
- int bit = irq - OFFCHIP_IRQ_BASE;
- u16 val;
-
- val = ctrl_inw(PA_CPLD_IMSK);
- val |= 1 << bit;
- ctrl_outw(val, PA_CPLD_IMSK);
+ unsigned int bit = irq - SE7343_FPGA_IRQ_BASE;
+ ctrl_outw(ctrl_inw(PA_CPLD_IMSK) | 1 << bit, PA_CPLD_IMSK);
}
-static void
-enable_intreq_irq(unsigned int irq)
+static void enable_se7343_irq(unsigned int irq)
{
- int bit = irq - OFFCHIP_IRQ_BASE;
- u16 val;
-
- val = ctrl_inw(PA_CPLD_IMSK);
- val &= ~(1 << bit);
- ctrl_outw(val, PA_CPLD_IMSK);
+ unsigned int bit = irq - SE7343_FPGA_IRQ_BASE;
+ ctrl_outw(ctrl_inw(PA_CPLD_IMSK) & ~(1 << bit), PA_CPLD_IMSK);
}
-static void
-mask_and_ack_intreq_irq(unsigned int irq)
-{
- disable_intreq_irq(irq);
-}
-
-static unsigned int
-startup_intreq_irq(unsigned int irq)
-{
- enable_intreq_irq(irq);
- return 0;
-}
-
-static void
-shutdown_intreq_irq(unsigned int irq)
-{
- disable_intreq_irq(irq);
-}
-
-static void
-end_intreq_irq(unsigned int irq)
-{
- if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
- enable_intreq_irq(irq);
-}
-
-static struct hw_interrupt_type intreq_irq_type = {
- .typename = "FPGA-IRQ",
- .startup = startup_intreq_irq,
- .shutdown = shutdown_intreq_irq,
- .enable = enable_intreq_irq,
- .disable = disable_intreq_irq,
- .ack = mask_and_ack_intreq_irq,
- .end = end_intreq_irq
+static struct irq_chip se7343_irq_chip __read_mostly = {
+ .name = "SE7343-FPGA",
+ .mask = disable_se7343_irq,
+ .unmask = enable_se7343_irq,
+ .mask_ack = disable_se7343_irq,
};
-static void
-make_intreq_irq(unsigned int irq)
-{
- disable_irq_nosync(irq);
- irq_desc[irq].chip = &intreq_irq_type;
- disable_intreq_irq(irq);
-}
-
-int
-shmse_irq_demux(int irq)
+static void se7343_irq_demux(unsigned int irq, struct irq_desc *desc)
{
- int bit;
- volatile u16 val;
-
- if (irq == IRQ5_IRQ) {
- /* Read status Register */
- val = ctrl_inw(PA_CPLD_ST);
- bit = ffs(val);
- if (bit != 0)
- return OFFCHIP_IRQ_BASE + bit - 1;
+ unsigned short intv = ctrl_inw(PA_CPLD_ST);
+ struct irq_desc *ext_desc;
+ unsigned int ext_irq = SE7343_FPGA_IRQ_BASE;
+
+ intv &= (1 << SE7343_FPGA_IRQ_NR) - 1;
+
+ while (intv) {
+ if (intv & 1) {
+ ext_desc = irq_desc + ext_irq;
+ handle_level_irq(ext_irq, ext_desc);
+ }
+ intv >>= 1;
+ ext_irq++;
}
- return irq;
}
-/* IRQ5 is multiplexed between the following sources:
- * 1. PC Card socket
- * 2. Extension slot
- * 3. USB Controller
- * 4. Serial Controller
- *
- * We configure IRQ5 as a cascade IRQ.
- */
-static struct irqaction irq5 = {
- .handler = no_action,
- .mask = CPU_MASK_NONE,
- .name = "IRQ5-cascade",
-};
-
-static struct ipr_data se7343_irq5_ipr_map[] = {
- { IRQ5_IRQ, IRQ5_IPR_ADDR+2, IRQ5_IPR_POS, IRQ5_PRIORITY },
-};
-static struct ipr_data se7343_siof0_vpu_ipr_map[] = {
- { SIOF0_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY },
- { VPU_IRQ, VPU_IPR_ADDR, VPU_IPR_POS, 8 },
-};
-static struct ipr_data se7343_other_ipr_map[] = {
- { DMTE0_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY },
- { DMTE1_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY },
- { DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY },
- { DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY },
- { DMTE4_IRQ, DMA2_IPR_ADDR, DMA2_IPR_POS, DMA2_PRIORITY },
- { DMTE5_IRQ, DMA2_IPR_ADDR, DMA2_IPR_POS, DMA2_PRIORITY },
-
- /* I2C block */
- { IIC0_ALI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY },
- { IIC0_TACKI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY },
- { IIC0_WAITI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY },
- { IIC0_DTEI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY },
-
- { IIC1_ALI_IRQ, IIC1_IPR_ADDR, IIC1_IPR_POS, IIC1_PRIORITY },
- { IIC1_TACKI_IRQ, IIC1_IPR_ADDR, IIC1_IPR_POS, IIC1_PRIORITY },
- { IIC1_WAITI_IRQ, IIC1_IPR_ADDR, IIC1_IPR_POS, IIC1_PRIORITY },
- { IIC1_DTEI_IRQ, IIC1_IPR_ADDR, IIC1_IPR_POS, IIC1_PRIORITY },
-
- /* SIOF */
- { SIOF0_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY },
-
- /* SIU */
- { SIU_IRQ, SIU_IPR_ADDR, SIU_IPR_POS, SIU_PRIORITY },
-
- /* VIO interrupt */
- { CEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY },
- { BEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY },
- { VEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY },
-
- /*MFI interrupt*/
-
- { MFI_IRQ, MFI_IPR_ADDR, MFI_IPR_POS, MFI_PRIORITY },
-
- /* LCD controller */
- { LCDC_IRQ, LCDC_IPR_ADDR, LCDC_IPR_POS, LCDC_PRIORITY },
-};
-
/*
* Initialize IRQ setting
*/
-void __init
-init_7343se_IRQ(void)
+void __init init_7343se_IRQ(void)
{
- /* Setup Multiplexed interrupts */
- ctrl_outw(8, PA_CPLD_MODESET); /* Set all CPLD interrupts to active
- * low.
- */
- /* Mask all CPLD controller interrupts */
- ctrl_outw(0x0fff, PA_CPLD_IMSK);
-
- /* PC Card interrupts */
- make_intreq_irq(PC_IRQ0);
- make_intreq_irq(PC_IRQ1);
- make_intreq_irq(PC_IRQ2);
- make_intreq_irq(PC_IRQ3);
-
- /* Extension Slot Interrupts */
- make_intreq_irq(EXT_IRQ0);
- make_intreq_irq(EXT_IRQ1);
- make_intreq_irq(EXT_IRQ2);
- make_intreq_irq(EXT_IRQ3);
-
- /* USB Controller interrupts */
- make_intreq_irq(USB_IRQ0);
- make_intreq_irq(USB_IRQ1);
-
- /* Serial Controller interrupts */
- make_intreq_irq(UART_IRQ0);
- make_intreq_irq(UART_IRQ1);
-
- /* Setup all external interrupts to be active low */
- ctrl_outw(0xaaaa, INTC_ICR1);
-
- make_ipr_irq(se7343_irq5_ipr_map, ARRAY_SIZE(se7343_irq5_ipr_map));
-
- setup_irq(IRQ5_IRQ, &irq5);
- /* Set port control to use IRQ5 */
- *(u16 *)0xA4050108 &= ~0xc;
-
- make_ipr_irq(se7343_siof0_vpu_ipr_map, ARRAY_SIZE(se7343_siof0_vpu_ipr_map));
-
- ctrl_outb(0x0f, INTC_IMCR5); /* enable SCIF IRQ */
-
- make_ipr_irq(se7343_other_ipr_map, ARRAY_SIZE(se7343_other_ipr_map));
-
- ctrl_outw(0x2000, PA_MRSHPC + 0x0c); /* mrshpc irq enable */
+ int i;
+
+ ctrl_outw(0, PA_CPLD_IMSK); /* disable all irqs */
+ ctrl_outw(0x2000, 0xb03fffec); /* mrshpc irq enable */
+
+ for (i = 0; i < SE7343_FPGA_IRQ_NR; i++)
+ set_irq_chip_and_handler_name(SE7343_FPGA_IRQ_BASE + i,
+ &se7343_irq_chip,
+ handle_level_irq, "level");
+
+ set_irq_chained_handler(IRQ0_IRQ, se7343_irq_demux);
+ set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW);
+ set_irq_chained_handler(IRQ1_IRQ, se7343_irq_demux);
+ set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW);
+ set_irq_chained_handler(IRQ4_IRQ, se7343_irq_demux);
+ set_irq_type(IRQ4_IRQ, IRQ_TYPE_LEVEL_LOW);
+ set_irq_chained_handler(IRQ5_IRQ, se7343_irq_demux);
+ set_irq_type(IRQ5_IRQ, IRQ_TYPE_LEVEL_LOW);
}
diff --git a/arch/sh/boards/se/7343/setup.c b/arch/sh/boards/se/7343/setup.c
index c9431b3a051..8ae718d6c71 100644
--- a/arch/sh/boards/se/7343/setup.c
+++ b/arch/sh/boards/se/7343/setup.c
@@ -1,10 +1,11 @@
#include <linux/init.h>
#include <linux/platform_device.h>
+#include <linux/mtd/physmap.h>
#include <asm/machvec.h>
#include <asm/mach/se7343.h>
+#include <asm/heartbeat.h>
#include <asm/irq.h>
-
-void init_7343se_IRQ(void);
+#include <asm/io.h>
static struct resource smc91x_resources[] = {
[0] = {
@@ -17,8 +18,8 @@ static struct resource smc91x_resources[] = {
* shared with other devices via externel
* interrupt controller in FPGA...
*/
- .start = EXT_IRQ2,
- .end = EXT_IRQ2,
+ .start = SMC_IRQ,
+ .end = SMC_IRQ,
.flags = IORESOURCE_IRQ,
},
};
@@ -38,16 +39,65 @@ static struct resource heartbeat_resources[] = {
},
};
+static struct heartbeat_data heartbeat_data = {
+ .regsize = 16,
+};
+
static struct platform_device heartbeat_device = {
.name = "heartbeat",
.id = -1,
+ .dev = {
+ .platform_data = &heartbeat_data,
+ },
.num_resources = ARRAY_SIZE(heartbeat_resources),
.resource = heartbeat_resources,
};
+static struct mtd_partition nor_flash_partitions[] = {
+ {
+ .name = "loader",
+ .offset = 0x00000000,
+ .size = 128 * 1024,
+ },
+ {
+ .name = "rootfs",
+ .offset = MTDPART_OFS_APPEND,
+ .size = 31 * 1024 * 1024,
+ },
+ {
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ },
+};
+
+static struct physmap_flash_data nor_flash_data = {
+ .width = 2,
+ .parts = nor_flash_partitions,
+ .nr_parts = ARRAY_SIZE(nor_flash_partitions),
+};
+
+static struct resource nor_flash_resources[] = {
+ [0] = {
+ .start = 0x00000000,
+ .end = 0x01ffffff,
+ .flags = IORESOURCE_MEM,
+ }
+};
+
+static struct platform_device nor_flash_device = {
+ .name = "physmap-flash",
+ .dev = {
+ .platform_data = &nor_flash_data,
+ },
+ .num_resources = ARRAY_SIZE(nor_flash_resources),
+ .resource = nor_flash_resources,
+};
+
static struct platform_device *sh7343se_platform_devices[] __initdata = {
&smc91x_device,
&heartbeat_device,
+ &nor_flash_device,
};
static int __init sh7343se_devices_setup(void)
@@ -55,10 +105,19 @@ static int __init sh7343se_devices_setup(void)
return platform_add_devices(sh7343se_platform_devices,
ARRAY_SIZE(sh7343se_platform_devices));
}
+device_initcall(sh7343se_devices_setup);
+/*
+ * Initialize the board
+ */
static void __init sh7343se_setup(char **cmdline_p)
{
- device_initcall(sh7343se_devices_setup);
+ ctrl_outw(0xf900, FPGA_OUT); /* FPGA */
+
+ ctrl_outw(0x0002, PORT_PECR); /* PORT E 1 = IRQ5 */
+ ctrl_outw(0x0020, PORT_PSELD);
+
+ printk(KERN_INFO "MS7343CP01 Setup...done\n");
}
/*
@@ -90,5 +149,4 @@ static struct sh_machine_vector mv_7343se __initmv = {
.mv_outsl = sh7343se_outsl,
.mv_init_irq = init_7343se_IRQ,
- .mv_irq_demux = shmse_irq_demux,
};
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-15 19:40:10 +0000