diff options
Diffstat (limited to 'include/asm-arm')
57 files changed, 1670 insertions, 515 deletions
diff --git a/include/asm-arm/arch-aaec2000/uncompress.h b/include/asm-arm/arch-aaec2000/uncompress.h index fff0c94b75c..300f4bf3bc7 100644 --- a/include/asm-arm/arch-aaec2000/uncompress.h +++ b/include/asm-arm/arch-aaec2000/uncompress.h @@ -15,7 +15,7 @@ #define UART(x) (*(volatile unsigned long *)(serial_port + (x))) -static void putstr( const char *s ) +static void putc(int c) { unsigned long serial_port; do { @@ -28,17 +28,16 @@ static void putstr( const char *s ) return; } while (0); - for (; *s; s++) { - /* wait for space in the UART's transmitter */ - while ((UART(UART_SR) & UART_SR_TxFF)); - /* send the character out. */ - UART(UART_DR) = *s; - /* if a LF, also do CR... */ - if (*s == 10) { - while ((UART(UART_SR) & UART_SR_TxFF)); - UART(UART_DR) = 13; - } - } + /* wait for space in the UART's transmitter */ + while ((UART(UART_SR) & UART_SR_TxFF)) + barrier(); + + /* send the character out. */ + UART(UART_DR) = c; +} + +static inline void flush(void) +{ } #define arch_decomp_setup() diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_emac.h b/include/asm-arm/arch-at91rm9200/at91rm9200_emac.h new file mode 100644 index 00000000000..fbc091e61e2 --- /dev/null +++ b/include/asm-arm/arch-at91rm9200/at91rm9200_emac.h @@ -0,0 +1,138 @@ +/* + * include/asm-arm/arch-at91rm9200/at91rm9200_emac.h + * + * Copyright (C) 2005 Ivan Kokshaysky + * Copyright (C) SAN People + * + * Ethernet MAC registers. + * Based on AT91RM9200 datasheet revision E. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91RM9200_EMAC_H +#define AT91RM9200_EMAC_H + +#define AT91_EMAC_CTL 0x00 /* Control Register */ +#define AT91_EMAC_LB (1 << 0) /* Loopback */ +#define AT91_EMAC_LBL (1 << 1) /* Loopback Local */ +#define AT91_EMAC_RE (1 << 2) /* Receive Enable */ +#define AT91_EMAC_TE (1 << 3) /* Transmit Enable */ +#define AT91_EMAC_MPE (1 << 4) /* Management Port Enable */ +#define AT91_EMAC_CSR (1 << 5) /* Clear Statistics Registers */ +#define AT91_EMAC_INCSTAT (1 << 6) /* Increment Statistics Registers */ +#define AT91_EMAC_WES (1 << 7) /* Write Enable for Statistics Registers */ +#define AT91_EMAC_BP (1 << 8) /* Back Pressure */ + +#define AT91_EMAC_CFG 0x04 /* Configuration Register */ +#define AT91_EMAC_SPD (1 << 0) /* Speed */ +#define AT91_EMAC_FD (1 << 1) /* Full Duplex */ +#define AT91_EMAC_BR (1 << 2) /* Bit Rate */ +#define AT91_EMAC_CAF (1 << 4) /* Copy All Frames */ +#define AT91_EMAC_NBC (1 << 5) /* No Broadcast */ +#define AT91_EMAC_MTI (1 << 6) /* Multicast Hash Enable */ +#define AT91_EMAC_UNI (1 << 7) /* Unicast Hash Enable */ +#define AT91_EMAC_BIG (1 << 8) /* Receive 1522 Bytes */ +#define AT91_EMAC_EAE (1 << 9) /* External Address Match Enable */ +#define AT91_EMAC_CLK (3 << 10) /* MDC Clock Divisor */ +#define AT91_EMAC_CLK_DIV8 (0 << 10) +#define AT91_EMAC_CLK_DIV16 (1 << 10) +#define AT91_EMAC_CLK_DIV32 (2 << 10) +#define AT91_EMAC_CLK_DIV64 (3 << 10) +#define AT91_EMAC_RTY (1 << 12) /* Retry Test */ +#define AT91_EMAC_RMII (1 << 13) /* Reduce MII (RMII) */ + +#define AT91_EMAC_SR 0x08 /* Status Register */ +#define AT91_EMAC_SR_LINK (1 << 0) /* Link */ +#define AT91_EMAC_SR_MDIO (1 << 1) /* MDIO pin */ +#define AT91_EMAC_SR_IDLE (1 << 2) /* PHY idle */ + +#define AT91_EMAC_TAR 0x0c /* Transmit Address Register */ + +#define AT91_EMAC_TCR 0x10 /* Transmit Control Register */ +#define AT91_EMAC_LEN (0x7ff << 0) /* Transmit Frame Length */ +#define AT91_EMAC_NCRC (1 << 15) /* No CRC */ + +#define AT91_EMAC_TSR 0x14 /* Transmit Status Register */ +#define AT91_EMAC_TSR_OVR (1 << 0) /* Transmit Buffer Overrun */ +#define AT91_EMAC_TSR_COL (1 << 1) /* Collision Occurred */ +#define AT91_EMAC_TSR_RLE (1 << 2) /* Retry Limit Exceeded */ +#define AT91_EMAC_TSR_IDLE (1 << 3) /* Transmitter Idle */ +#define AT91_EMAC_TSR_BNQ (1 << 4) /* Transmit Buffer not Queued */ +#define AT91_EMAC_TSR_COMP (1 << 5) /* Transmit Complete */ +#define AT91_EMAC_TSR_UND (1 << 6) /* Transmit Underrun */ + +#define AT91_EMAC_RBQP 0x18 /* Receive Buffer Queue Pointer */ + +#define AT91_EMAC_RSR 0x20 /* Receive Status Register */ +#define AT91_EMAC_RSR_BNA (1 << 0) /* Buffer Not Available */ +#define AT91_EMAC_RSR_REC (1 << 1) /* Frame Received */ +#define AT91_EMAC_RSR_OVR (1 << 2) /* RX Overrun */ + +#define AT91_EMAC_ISR 0x24 /* Interrupt Status Register */ +#define AT91_EMAC_DONE (1 << 0) /* Management Done */ +#define AT91_EMAC_RCOM (1 << 1) /* Receive Complete */ +#define AT91_EMAC_RBNA (1 << 2) /* Receive Buffer Not Available */ +#define AT91_EMAC_TOVR (1 << 3) /* Transmit Buffer Overrun */ +#define AT91_EMAC_TUND (1 << 4) /* Transmit Buffer Underrun */ +#define AT91_EMAC_RTRY (1 << 5) /* Retry Limit */ +#define AT91_EMAC_TBRE (1 << 6) /* Transmit Buffer Register Empty */ +#define AT91_EMAC_TCOM (1 << 7) /* Transmit Complete */ +#define AT91_EMAC_TIDLE (1 << 8) /* Transmit Idle */ +#define AT91_EMAC_LINK (1 << 9) /* Link */ +#define AT91_EMAC_ROVR (1 << 10) /* RX Overrun */ +#define AT91_EMAC_ABT (1 << 11) /* Abort */ + +#define AT91_EMAC_IER 0x28 /* Interrupt Enable Register */ +#define AT91_EMAC_IDR 0x2c /* Interrupt Disable Register */ +#define AT91_EMAC_IMR 0x30 /* Interrupt Mask Register */ + +#define AT91_EMAC_MAN 0x34 /* PHY Maintenance Register */ +#define AT91_EMAC_DATA (0xffff << 0) /* MDIO Data */ +#define AT91_EMAC_REGA (0x1f << 18) /* MDIO Register */ +#define AT91_EMAC_PHYA (0x1f << 23) /* MDIO PHY Address */ +#define AT91_EMAC_RW (3 << 28) /* Read/Write operation */ +#define AT91_EMAC_RW_W (1 << 28) +#define AT91_EMAC_RW_R (2 << 28) +#define AT91_EMAC_MAN_802_3 0x40020000 /* IEEE 802.3 value */ + +/* + * Statistics Registers. + */ +#define AT91_EMAC_FRA 0x40 /* Frames Transmitted OK */ +#define AT91_EMAC_SCOL 0x44 /* Single Collision Frame */ +#define AT91_EMAC_MCOL 0x48 /* Multiple Collision Frame */ +#define AT91_EMAC_OK 0x4c /* Frames Received OK */ +#define AT91_EMAC_SEQE 0x50 /* Frame Check Sequence Error */ +#define AT91_EMAC_ALE 0x54 /* Alignmemt Error */ +#define AT91_EMAC_DTE 0x58 /* Deffered Transmission Frame */ +#define AT91_EMAC_LCOL 0x5c /* Late Collision */ +#define AT91_EMAC_ECOL 0x60 /* Excessive Collision */ +#define AT91_EMAC_TUE 0x64 /* Transmit Underrun Error */ +#define AT91_EMAC_CSE 0x68 /* Carrier Sense Error */ +#define AT91_EMAC_DRFC 0x6c /* Discard RX Frame */ +#define AT91_EMAC_ROV 0x70 /* Receive Overrun */ +#define AT91_EMAC_CDE 0x74 /* Code Error */ +#define AT91_EMAC_ELR 0x78 /* Excessive Length Error */ +#define AT91_EMAC_RJB 0x7c /* Receive Jabber */ +#define AT91_EMAC_USF 0x80 /* Undersize Frame */ +#define AT91_EMAC_SQEE 0x84 /* SQE Test Error */ + +/* + * Address Registers. + */ +#define AT91_EMAC_HSL 0x90 /* Hash Address Low [31:0] */ +#define AT91_EMAC_HSH 0x94 /* Hash Address High [63:32] */ +#define AT91_EMAC_SA1L 0x98 /* Specific Address 1 Low, bytes 0-3 */ +#define AT91_EMAC_SA1H 0x9c /* Specific Address 1 High, bytes 4-5 */ +#define AT91_EMAC_SA2L 0xa0 /* Specific Address 2 Low, bytes 0-3 */ +#define AT91_EMAC_SA2H 0xa4 /* Specific Address 2 High, bytes 4-5 */ +#define AT91_EMAC_SA3L 0xa8 /* Specific Address 3 Low, bytes 0-3 */ +#define AT91_EMAC_SA3H 0xac /* Specific Address 3 High, bytes 4-5 */ +#define AT91_EMAC_SA4L 0xb0 /* Specific Address 4 Low, bytes 0-3 */ +#define AT91_EMAC_SA4H 0xb4 /* Specific Address 4 High, bytes 4-5 */ + +#endif diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h b/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h index 9bfffdbf1e0..2910d359f91 100644 --- a/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h +++ b/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h @@ -172,6 +172,7 @@ #define AT91_PMC_MDIV_4 (3 << 8) #define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-3 Registers */ + #define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */ #define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */ #define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */ @@ -286,8 +287,32 @@ #define AT91_MC_RCB (1 << 0) /* Remap Command Bit */ #define AT91_MC_ASR (AT91_MC + 0x04) /* MC Abort Status Register */ +#define AT91_MC_UNADD (1 << 0) /* Undefined Address Abort Status */ +#define AT91_MC_MISADD (1 << 1) /* Misaligned Address Abort Status */ +#define AT91_MC_ABTSZ (3 << 8) /* Abort Size Status */ +#define AT91_MC_ABTSZ_BYTE (0 << 8) +#define AT91_MC_ABTSZ_HALFWORD (1 << 8) +#define AT91_MC_ABTSZ_WORD (2 << 8) +#define AT91_MC_ABTTYP (3 << 10) /* Abort Type Status */ +#define AT91_MC_ABTTYP_DATAREAD (0 << 10) +#define AT91_MC_ABTTYP_DATAWRITE (1 << 10) +#define AT91_MC_ABTTYP_FETCH (2 << 10) +#define AT91_MC_MST0 (1 << 16) /* ARM920T Abort Source */ +#define AT91_MC_MST1 (1 << 17) /* PDC Abort Source */ +#define AT91_MC_MST2 (1 << 18) /* UHP Abort Source */ +#define AT91_MC_MST3 (1 << 19) /* EMAC Abort Source */ +#define AT91_MC_SVMST0 (1 << 24) /* Saved ARM920T Abort Source */ +#define AT91_MC_SVMST1 (1 << 25) /* Saved PDC Abort Source */ +#define AT91_MC_SVMST2 (1 << 26) /* Saved UHP Abort Source */ +#define AT91_MC_SVMST3 (1 << 27) /* Saved EMAC Abort Source */ + #define AT91_MC_AASR (AT91_MC + 0x08) /* MC Abort Address Status Register */ + #define AT91_MC_MPR (AT91_MC + 0x0c) /* MC Master Priority Register */ +#define AT91_MPR_MSTP0 (7 << 0) /* ARM920T Priority */ +#define AT91_MPR_MSTP1 (7 << 4) /* PDC Priority */ +#define AT91_MPR_MSTP2 (7 << 8) /* UHP Priority */ +#define AT91_MPR_MSTP3 (7 << 12) /* EMAC Priority */ /* External Bus Interface (EBI) registers */ #define AT91_EBI_CSA (AT91_MC + 0x60) /* Chip Select Assignment Register */ @@ -309,8 +334,10 @@ /* Static Memory Controller (SMC) registers */ #define AT91_SMC_CSR(n) (AT91_MC + 0x70 + ((n) * 4))/* SMC Chip Select Register */ #define AT91_SMC_NWS (0x7f << 0) /* Number of Wait States */ +#define AT91_SMC_NWS_(x) ((x) << 0) #define AT91_SMC_WSEN (1 << 7) /* Wait State Enable */ #define AT91_SMC_TDF (0xf << 8) /* Data Float Time */ +#define AT91_SMC_TDF_(x) ((x) << 8) #define AT91_SMC_BAT (1 << 12) /* Byte Access Type */ #define AT91_SMC_DBW (3 << 13) /* Data Bus Width */ #define AT91_SMC_DBW_16 (1 << 13) @@ -322,7 +349,78 @@ #define AT91_SMC_ACSS_2 (2 << 16) #define AT91_SMC_ACSS_3 (3 << 16) #define AT91_SMC_RWSETUP (7 << 24) /* Read & Write Signal Time Setup */ +#define AT91_SMC_RWSETUP_(x) ((x) << 24) #define AT91_SMC_RWHOLD (7 << 28) /* Read & Write Signal Hold Time */ - +#define AT91_SMC_RWHOLD_(x) ((x) << 28) + +/* SDRAM Controller registers */ +#define AT91_SDRAMC_MR (AT91_MC + 0x90) /* Mode Register */ +#define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */ +#define AT91_SDRAMC_MODE_NORMAL (0 << 0) +#define AT91_SDRAMC_MODE_NOP (1 << 0) +#define AT91_SDRAMC_MODE_PRECHARGE (2 << 0) +#define AT91_SDRAMC_MODE_LMR (3 << 0) +#define AT91_SDRAMC_MODE_REFRESH (4 << 0) +#define AT91_SDRAMC_DBW (1 << 4) /* Data Bus Width */ +#define AT91_SDRAMC_DBW_32 (0 << 4) +#define AT91_SDRAMC_DBW_16 (1 << 4) + +#define AT91_SDRAMC_TR (AT91_MC + 0x94) /* Refresh Timer Register */ +#define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Count */ + +#define AT91_SDRAMC_CR (AT91_MC + 0x98) /* Configuration Register */ +#define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */ +#define AT91_SDRAMC_NC_8 (0 << 0) +#define AT91_SDRAMC_NC_9 (1 << 0) +#define AT91_SDRAMC_NC_10 (2 << 0) +#define AT91_SDRAMC_NC_11 (3 << 0) +#define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */ +#define AT91_SDRAMC_NR_11 (0 << 2) +#define AT91_SDRAMC_NR_12 (1 << 2) +#define AT91_SDRAMC_NR_13 (2 << 2) +#define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */ +#define AT91_SDRAMC_NB_2 (0 << 4) +#define AT91_SDRAMC_NB_4 (1 << 4) +#define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */ +#define AT91_SDRAMC_CAS_2 (2 << 5) +#define AT91_SDRAMC_TWR (0xf << 7) /* Write Recovery Delay */ +#define AT91_SDRAMC_TRC (0xf << 11) /* Row Cycle Delay */ +#define AT91_SDRAMC_TRP (0xf << 15) /* Row Precharge Delay */ +#define AT91_SDRAMC_TRCD (0xf << 19) /* Row to Column Delay */ +#define AT91_SDRAMC_TRAS (0xf << 23) /* Active to Precharge Delay */ +#define AT91_SDRAMC_TXSR (0xf << 27) /* Exit Self Refresh to Active Delay */ + +#define AT91_SDRAMC_SRR (AT91_MC + 0x9c) /* Self Refresh Register */ +#define AT91_SDRAMC_LPR (AT91_MC + 0xa0) /* Low Power Register */ +#define AT91_SDRAMC_IER (AT91_MC + 0xa4) /* Interrupt Enable Register */ +#define AT91_SDRAMC_IDR (AT91_MC + 0xa8) /* Interrupt Disable Register */ +#define AT91_SDRAMC_IMR (AT91_MC + 0xac) /* Interrupt Mask Register */ +#define AT91_SDRAMC_ISR (AT91_MC + 0xb0) /* Interrupt Status Register */ + +/* Burst Flash Controller register */ +#define AT91_BFC_MR (AT91_MC + 0xc0) /* Mode Register */ +#define AT91_BFC_BFCOM (3 << 0) /* Burst Flash Controller Operating Mode */ +#define AT91_BFC_BFCOM_DISABLED (0 << 0) +#define AT91_BFC_BFCOM_ASYNC (1 << 0) +#define AT91_BFC_BFCOM_BURST (2 << 0) +#define AT91_BFC_BFCC (3 << 2) /* Burst Flash Controller Clock */ +#define AT91_BFC_BFCC_MCK (1 << 2) +#define AT91_BFC_BFCC_DIV2 (2 << 2) +#define AT91_BFC_BFCC_DIV4 (3 << 2) +#define AT91_BFC_AVL (0xf << 4) /* Address Valid Latency */ +#define AT91_BFC_PAGES (7 << 8) /* Page Size */ +#define AT91_BFC_PAGES_NO_PAGE (0 << 8) +#define AT91_BFC_PAGES_16 (1 << 8) +#define AT91_BFC_PAGES_32 (2 << 8) +#define AT91_BFC_PAGES_64 (3 << 8) +#define AT91_BFC_PAGES_128 (4 << 8) +#define AT91_BFC_PAGES_256 (5 << 8) +#define AT91_BFC_PAGES_512 (6 << 8) +#define AT91_BFC_PAGES_1024 (7 << 8) +#define AT91_BFC_OEL (3 << 12) /* Output Enable Latency */ +#define AT91_BFC_BAAEN (1 << 16) /* Burst Address Advance Enable */ +#define AT91_BFC_BFOEH (1 << 17) /* Burst Flash Output Enable Handling */ +#define AT91_BFC_MUXEN (1 << 18) /* Multiplexed Bus Enable */ +#define AT91_BFC_RDYEN (1 << 19) /* Ready Enable Mode */ #endif diff --git a/include/asm-arm/arch-at91rm9200/uncompress.h b/include/asm-arm/arch-at91rm9200/uncompress.h index b30dd552071..7b38497c24b 100644 --- a/include/asm-arm/arch-at91rm9200/uncompress.h +++ b/include/asm-arm/arch-at91rm9200/uncompress.h @@ -31,21 +31,22 @@ * * This does not append a newline */ -static void putstr(const char *s) +static void putc(int c) +{ + void __iomem *sys = (void __iomem *) AT91_BASE_SYS; /* physical address */ + + while (!(__raw_readl(sys + AT91_DBGU_SR) & AT91_DBGU_TXRDY)) + barrier(); + __raw_writel(c, sys + AT91_DBGU_THR); +} + +static inline void flush(void) { void __iomem *sys = (void __iomem *) AT91_BASE_SYS; /* physical address */ - while (*s) { - while (!(__raw_readl(sys + AT91_DBGU_SR) & AT91_DBGU_TXRDY)) { barrier(); } - __raw_writel(*s, sys + AT91_DBGU_THR); - if (*s == '\n') { - while (!(__raw_readl(sys + AT91_DBGU_SR) & AT91_DBGU_TXRDY)) { barrier(); } - __raw_writel('\r', sys + AT91_DBGU_THR); - } - s++; - } /* wait for transmission to complete */ - while (!(__raw_readl(sys + AT91_DBGU_SR) & AT91_DBGU_TXEMPTY)) { barrier(); } + while (!(__raw_readl(sys + AT91_DBGU_SR) & AT91_DBGU_TXEMPTY)) + barrier(); } #define arch_decomp_setup() diff --git a/include/asm-arm/arch-cl7500/uncompress.h b/include/asm-arm/arch-cl7500/uncompress.h index 68601b3e3b9..c437e0c88c3 100644 --- a/include/asm-arm/arch-cl7500/uncompress.h +++ b/include/asm-arm/arch-cl7500/uncompress.h @@ -3,27 +3,19 @@ * * Copyright (C) 1999, 2000 Nexus Electronics Ltd. */ - #define BASE 0x03010000 #define SERBASE (BASE + (0x2f8 << 2)) -static __inline__ void putc(char c) +static inline void putc(char c) { - while (!(*((volatile unsigned int *)(SERBASE + 0x14)) & 0x20)); + while (!(*((volatile unsigned int *)(SERBASE + 0x14)) & 0x20)) + barrier(); + *((volatile unsigned int *)(SERBASE)) = c; } -/* - * This does not append a newline - */ -static void putstr(const char *s) +static inline void flush(void) { - while (*s) { - putc(*s); - if (*s == '\n') - putc('\r'); - s++; - } } static __inline__ void arch_decomp_setup(void) diff --git a/include/asm-arm/arch-clps711x/uncompress.h b/include/asm-arm/arch-clps711x/uncompress.h index 9fc4bcfa168..07157b7e4b2 100644 --- a/include/asm-arm/arch-clps711x/uncompress.h +++ b/include/asm-arm/arch-clps711x/uncompress.h @@ -25,7 +25,6 @@ #undef CLPS7111_BASE #define CLPS7111_BASE CLPS7111_PHYS_BASE -#define barrier() __asm__ __volatile__("": : :"memory") #define __raw_readl(p) (*(unsigned long *)(p)) #define __raw_writel(v,p) (*(unsigned long *)(p) = (v)) @@ -40,21 +39,15 @@ /* * This does not append a newline */ -static void putstr(const char *s) +static inline void putc(int c) { - char c; - - while ((c = *s++) != '\0') { - while (clps_readl(SYSFLGx) & SYSFLG_UTXFF) - barrier(); - clps_writel(c, UARTDRx); + while (clps_readl(SYSFLGx) & SYSFLG_UTXFF) + barrier(); + clps_writel(c, UARTDRx); +} - if (c == '\n') { - while (clps_readl(SYSFLGx) & SYSFLG_UTXFF) - barrier(); - clps_writel('\r', UARTDRx); - } - } +static inline void flush(void) +{ while (clps_readl(SYSFLGx) & SYSFLG_UBUSY) barrier(); } diff --git a/include/asm-arm/arch-ebsa110/uncompress.h b/include/asm-arm/arch-ebsa110/uncompress.h index eee95581a92..66b19c7fd90 100644 --- a/include/asm-arm/arch-ebsa110/uncompress.h +++ b/include/asm-arm/arch-ebsa110/uncompress.h @@ -8,33 +8,34 @@ * published by the Free Software Foundation. */ +#include <linux/serial_reg.h> + +#define SERIAL_BASE ((unsigned char *)0xfe000be0) + /* * This does not append a newline */ -static void putstr(const char *s) +static inline void putc(int c) +{ + unsigned char v, *base = SERIAL_BASE; + + do { + v = base[UART_LSR << 2]; + barrier(); + } while (!(v & UART_LSR_THRE)); + + base[UART_TX << 2] = c; +} + +static inline void flush(void) { - unsigned long tmp1, tmp2; - __asm__ __volatile__( - "ldrb %0, [%2], #1\n" -" teq %0, #0\n" -" beq 3f\n" -"1: strb %0, [%3]\n" -"2: ldrb %1, [%3, #0x14]\n" -" and %1, %1, #0x60\n" -" teq %1, #0x60\n" -" bne 2b\n" -" teq %0, #'\n'\n" -" moveq %0, #'\r'\n" -" beq 1b\n" -" ldrb %0, [%2], #1\n" -" teq %0, #0\n" -" bne 1b\n" -"3: ldrb %1, [%3, #0x14]\n" -" and %1, %1, #0x60\n" -" teq %1, #0x60\n" -" bne 3b" - : "=&r" (tmp1), "=&r" (tmp2) - : "r" (s), "r" (0xf0000be0) : "cc"); + unsigned char v, *base = SERIAL_BASE; + + do { + v = base[UART_LSR << 2]; + barrier(); + } while ((v & (UART_LSR_TEMT|UART_LSR_THRE)) != + (UART_LSR_TEMT|UART_LSR_THRE)); } /* diff --git a/include/asm-arm/arch-ebsa285/uncompress.h b/include/asm-arm/arch-ebsa285/uncompress.h index c2fd84e2d90..86142c882b3 100644 --- a/include/asm-arm/arch-ebsa285/uncompress.h +++ b/include/asm-arm/arch-ebsa285/uncompress.h @@ -15,10 +15,11 @@ #define DC21285_BASE ((volatile unsigned int *)0x42000160) #define SER0_BASE ((volatile unsigned char *)0x7c0003f8) -static __inline__ void putc(char c) +static inline void putc(char c) { if (machine_is_netwinder()) { - while ((SER0_BASE[5] & 0x60) != 0x60); + while ((SER0_BASE[5] & 0x60) != 0x60) + barrier(); SER0_BASE[0] = c; } else { while (DC21285_BASE[6] & 8); @@ -26,17 +27,8 @@ static __inline__ void putc(char c) } } -/* - * This does not append a newline - */ -static void putstr(const char *s) +static inline void flush(void) { - while (*s) { - putc(*s); - if (*s == '\n') - putc('\r'); - s++; - } } /* diff --git a/include/asm-arm/arch-ep93xx/uncompress.h b/include/asm-arm/arch-ep93xx/uncompress.h index 4410d217077..c15274c85d5 100644 --- a/include/asm-arm/arch-ep93xx/uncompress.h +++ b/include/asm-arm/arch-ep93xx/uncompress.h @@ -16,17 +16,27 @@ static unsigned char __raw_readb(unsigned int ptr) return *((volatile unsigned char *)ptr); } +static unsigned int __raw_readl(unsigned int ptr) +{ + return *((volatile unsigned int *)ptr); +} + static void __raw_writeb(unsigned char value, unsigned int ptr) { *((volatile unsigned char *)ptr) = value; } +static void __raw_writel(unsigned int value, unsigned int ptr) +{ + *((volatile unsigned int *)ptr) = value; +} + #define PHYS_UART1_DATA 0x808c0000 #define PHYS_UART1_FLAG 0x808c0018 #define UART1_FLAG_TXFF 0x20 -static __inline__ void putc(char c) +static inline void putc(int c) { int i; @@ -39,15 +49,37 @@ static __inline__ void putc(char c) __raw_writeb(c, PHYS_UART1_DATA); } -static void putstr(const char *s) +static inline void flush(void) { - while (*s) { - putc(*s); - if (*s == '\n') - putc('\r'); - s++; - } } -#define arch_decomp_setup() + +/* + * Some bootloaders don't turn off DMA from the ethernet MAC before + * jumping to linux, which means that we might end up with bits of RX + * status and packet data scribbled over the uncompressed kernel image. + * Work around this by resetting the ethernet MAC before we uncompress. + */ +#define PHYS_ETH_SELF_CTL 0x80010020 +#define ETH_SELF_CTL_RESET 0x00000001 + +static void ethernet_reset(void) +{ + unsigned int v; + + /* Reset the ethernet MAC. */ + v = __raw_readl(PHYS_ETH_SELF_CTL); + __raw_writel(v | ETH_SELF_CTL_RESET, PHYS_ETH_SELF_CTL); + + /* Wait for reset to finish. */ + while (__raw_readl(PHYS_ETH_SELF_CTL) & ETH_SELF_CTL_RESET) + ; +} + + +static void arch_decomp_setup(void) +{ + ethernet_reset(); +} + #define arch_decomp_wdog() diff --git a/include/asm-arm/arch-h720x/uncompress.h b/include/asm-arm/arch-h720x/uncompress.h index 9535764bcc7..18c69e0f358 100644 --- a/include/asm-arm/arch-h720x/uncompress.h +++ b/include/asm-arm/arch-h720x/uncompress.h @@ -12,22 +12,20 @@ #define LSR 0x14 #define TEMPTY 0x40 -static void putstr(const char *s) +static inline void putc(int c) { - char c; volatile unsigned char *p = (volatile unsigned char *)(IO_PHYS+0x20000); - while ( (c = *s++) != '\0') { - /* wait until transmit buffer is empty */ - while((p[LSR] & TEMPTY) == 0x0); - /* write next character */ - *p = c; - - if(c == '\n') { - while((p[LSR] & TEMPTY) == 0x0); - *p = '\r'; - } - } + /* wait until transmit buffer is empty */ + while((p[LSR] & TEMPTY) == 0x0) + barrier(); + + /* write next character */ + *p = c; +} + +static inline void flush(void) +{ } /* diff --git a/include/asm-arm/arch-imx/uncompress.h b/include/asm-arm/arch-imx/uncompress.h index 096077f2750..da333f69136 100644 --- a/include/asm-arm/arch-imx/uncompress.h +++ b/include/asm-arm/arch-imx/uncompress.h @@ -39,8 +39,7 @@ * * This does not append a newline */ -static void -putstr(const char *s) +static void putc(int c) { unsigned long serial_port; @@ -54,20 +53,14 @@ putstr(const char *s) return; } while(0); - while (*s) { - while ( !(UART(USR2) & USR2_TXFE) ) - barrier(); + while (!(UART(USR2) & USR2_TXFE)) + barrier(); - UART(TXR) = *s; - - if (*s == '\n') { - while ( !(UART(USR2) & USR2_TXFE) ) - barrier(); + UART(TXR) = c; +} - UART(TXR) = '\r'; - } - s++; - } +static inline void flush(void) +{ } /* diff --git a/include/asm-arm/arch-integrator/uncompress.h b/include/asm-arm/arch-integrator/uncompress.h index 3957402741d..f61825c4d90 100644 --- a/include/asm-arm/arch-integrator/uncompress.h +++ b/include/asm-arm/arch-integrator/uncompress.h @@ -28,21 +28,18 @@ /* * This does not append a newline */ -static void putstr(const char *s) +static void putc(int c) { - while (*s) { - while (AMBA_UART_FR & (1 << 5)); + while (AMBA_UART_FR & (1 << 5)) + barrier(); - AMBA_UART_DR = *s; - - if (*s == '\n') { - while (AMBA_UART_FR & (1 << 5)); + AMBA_UART_DR = c; +} - AMBA_UART_DR = '\r'; - } - s++; - } - while (AMBA_UART_FR & (1 << 3)); +static inline void flush(void) +{ + while (AMBA_UART_FR & (1 << 3)) + barrier(); } /* diff --git a/include/asm-arm/arch-iop3xx/uncompress.h b/include/asm-arm/arch-iop3xx/uncompress.h index 82b88762c3c..c98eb6254b1 100644 --- a/include/asm-arm/arch-iop3xx/uncompress.h +++ b/include/asm-arm/arch-iop3xx/uncompress.h @@ -19,23 +19,15 @@ static volatile UTYPE uart_base; #define TX_DONE (UART_LSR_TEMT|UART_LSR_THRE) -static __inline__ void putc(char c) +static inline void putc(char c) { - while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE); + while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE) + barrier(); *uart_base = c; } -/* - * This does not append a newline - */ -static void putstr(const char *s) +static inline void flush(void) { - while (*s) { - putc(*s); - if (*s == '\n') - putc('\r'); - s++; - } } static __inline__ void __arch_decomp_setup(unsigned long arch_id) diff --git a/include/asm-arm/arch-ixp2000/uncompress.h b/include/asm-arm/arch-ixp2000/uncompress.h index 3d3d5b2ed6e..f66b408f363 100644 --- a/include/asm-arm/arch-ixp2000/uncompress.h +++ b/include/asm-arm/arch-ixp2000/uncompress.h @@ -29,23 +29,18 @@ #define UARTSR PHYS(0x14) /* Status reg */ -static __inline__ void putc(char c) +static inline void putc(int c) { int j = 0x1000; - while (--j && !(*UARTSR & UART_LSR_THRE)); + while (--j && !(*UARTSR & UART_LSR_THRE)) + barrier(); + *UARTDR = c; } -static void putstr(const char *s) +static inline void flush(void) { - while (*s) - { - putc(*s); - if (*s == '\n') - putc('\r'); - s++; - } } #define arch_decomp_setup() diff --git a/include/asm-arm/arch-ixp23xx/debug-macro.S b/include/asm-arm/arch-ixp23xx/debug-macro.S new file mode 100644 index 00000000000..eb99fd69fd2 --- /dev/null +++ b/include/asm-arm/arch-ixp23xx/debug-macro.S @@ -0,0 +1,23 @@ +/* + * include/asm-arm/arch-ixp23xx/debug-macro.S + * + * Debugging macro include header + * + * Copyright (C) 1994-1999 Russell King + * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <asm/arch/ixp23xx.h> + + .macro addruart,rx + mrc p15, 0, \rx, c1, c0 + tst \rx, #1 @ mmu enabled? + ldreq \rx, =IXP23XX_PERIPHERAL_PHYS @ physical + ldrne \rx, =IXP23XX_PERIPHERAL_VIRT @ virtual + .endm + +#define UART_SHIFT 2 +#include <asm/hardware/debug-8250.S> diff --git a/include/asm-arm/arch-ixp23xx/dma.h b/include/asm-arm/arch-ixp23xx/dma.h new file mode 100644 index 00000000000..2f4335e3b83 --- /dev/null +++ b/include/asm-arm/arch-ixp23xx/dma.h @@ -0,0 +1,3 @@ +/* + * include/asm-arm/arch-ixp23xx/dma.h + */ diff --git a/include/asm-arm/arch-ixp23xx/entry-macro.S b/include/asm-arm/arch-ixp23xx/entry-macro.S new file mode 100644 index 00000000000..0ef4e6016ac --- /dev/null +++ b/include/asm-arm/arch-ixp23xx/entry-macro.S @@ -0,0 +1,31 @@ +/* + * include/asm-arm/arch-ixp23xx/entry-macro.S + */ + + .macro disable_fiq + .endm + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + ldr \irqnr, =(IXP23XX_INTC_VIRT + IXP23XX_INTR_IRQ_ENC_ST_OFFSET) + ldr \irqnr, [\irqnr] @ get interrupt number + cmp \irqnr, #0x0 @ suprious interrupt ? + movne \irqnr, \irqnr, lsr #2 @ skip unwanted low order bits + subne \irqnr, \irqnr, #1 @ convert to 0 based + +#if 0 + cmp \irqnr, #IRQ_IXP23XX_PCI_INT_RPH + bne 1001f + mov \irqnr, #IRQ_IXP23XX_INTA + + ldr \irqnr, =0xf5000030 + + mov \tmp, #(1<<26) + tst \irqnr, \tmp + movne \irqnr, #IRQ_IXP23XX_INTB + + mov \tmp, #(1<<27) + tst \irqnr, \tmp + movne \irqnr, #IRQ_IXP23XX_INTA +1001: +#endif + .endm diff --git a/include/asm-arm/arch-ixp23xx/hardware.h b/include/asm-arm/arch-ixp23xx/hardware.h new file mode 100644 index 00000000000..c0010d21a68 --- /dev/null +++ b/include/asm-arm/arch-ixp23xx/hardware.h @@ -0,0 +1,37 @@ +/* + * include/asm-arm/arch-ixp23xx/hardware.h + * + * Copyright (C) 2002-2004 Intel Corporation. + * Copyricht (C) 2005 MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Hardware definitions for IXP23XX based systems + */ + +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +/* PCI IO info */ +#define PCIO_BASE IXP23XX_PCI_IO_VIRT +#define PCIBIOS_MIN_IO 0x00000000 +#define PCIBIOS_MIN_MEM 0xe0000000 + +#include "ixp23xx.h" + +#define pcibios_assign_all_busses() 0 + +/* + * Platform helper functions + */ +#include "platform.h" + +/* + * Platform-specific headers + */ +#include "ixdp2351.h" + + +#endif diff --git a/include/asm-arm/arch-ixp23xx/io.h b/include/asm-arm/arch-ixp23xx/io.h new file mode 100644 index 00000000000..18415a81ac7 --- /dev/null +++ b/include/asm-arm/arch-ixp23xx/io.h @@ -0,0 +1,54 @@ +/* + * include/asm-arm/arch-ixp23xx/io.h + * + * Original Author: Naeem M Afzal <naeem.m.afzal@intel.com> + * Maintainer: Deepak Saxena <dsaxena@plexity.net> + * + * Copyright (C) 2003-2005 Intel Corp. + * Copyright (C) 2005 MontaVista Software, Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_IO_H +#define __ASM_ARCH_IO_H + +#define IO_SPACE_LIMIT 0xffffffff + +#define __io(p) ((void __iomem*)((p) + IXP23XX_PCI_IO_VIRT)) +#define __mem_pci(a) (a) + +#include <linux/kernel.h> /* For BUG */ + +static inline void __iomem * +ixp23xx_ioremap(unsigned long addr, unsigned long size, unsigned long flags) +{ + if (addr >= IXP23XX_PCI_MEM_START && + addr <= IXP23XX_PCI_MEM_START + IXP23XX_PCI_MEM_SIZE) { + if (addr + size > IXP23XX_PCI_MEM_START + IXP23XX_PCI_MEM_SIZE) + return NULL; + + return (void __iomem *) + ((addr - IXP23XX_PCI_MEM_START) + IXP23XX_PCI_MEM_VIRT); + } + + return __ioremap(addr, size, flags); +} + +static inline void +ixp23xx_iounmap(void __iomem *addr) +{ + if ((((u32)addr) >= IXP23XX_PCI_MEM_VIRT) && + (((u32)addr) < IXP23XX_PCI_MEM_VIRT + IXP23XX_PCI_MEM_SIZE)) + return; + + __iounmap(addr); +} + +#define __arch_ioremap(a,s,f) ixp23xx_ioremap(a,s,f) +#define __arch_iounmap(a) ixp23xx_iounmap(a) + + +#endif diff --git a/include/asm-arm/arch-ixp23xx/irqs.h b/include/asm-arm/arch-ixp23xx/irqs.h new file mode 100644 index 00000000000..e6963958572 --- /dev/null +++ b/include/asm-arm/arch-ixp23xx/irqs.h @@ -0,0 +1,223 @@ +/* + * include/asm-arm/arch-ixp23xx/irqs.h + * + * IRQ definitions for IXP23XX based systems + * + * Author: Naeem Afzal <naeem.m.afzal@intel.com> + * + * Copyright (C) 2003-2004 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_IRQS_H +#define __ASM_ARCH_IRQS_H + +#define NR_IXP23XX_IRQS IRQ_IXP23XX_INTB+1 +#define IRQ_IXP23XX_EXTIRQS NR_IXP23XX_IRQS + + +#define IRQ_IXP23XX_DBG0 0 /* Debug/Execution/MBox */ +#define IRQ_IXP23XX_DBG1 1 /* Debug/Execution/MBox */ +#define IRQ_IXP23XX_NPE_TRG 2 /* npe_trigger */ +#define IRQ_IXP23XX_TIMER1 3 /* Timer[0] */ +#define IRQ_IXP23XX_TIMER2 4 /* Timer[1] */ +#define IRQ_IXP23XX_TIMESTAMP 5 /* Timer[2], Time-stamp */ +#define IRQ_IXP23XX_WDOG 6 /* Time[3], Watchdog Timer */ +#define IRQ_IXP23XX_PCI_DBELL 7 /* PCI Doorbell */ +#define IRQ_IXP23XX_PCI_DMA1 8 /* PCI DMA Channel 1 */ +#define IRQ_IXP23XX_PCI_DMA2 9 /* PCI DMA Channel 2 */ +#define IRQ_IXP23XX_PCI_DMA3 10 /* PCI DMA Channel 3 */ +#define IRQ_IXP23XX_PCI_INT_RPH 11 /* pcxg_pci_int_rph */ +#define IRQ_IXP23XX_CPP_PMU 12 /* xpxg_pm_int_rpl */ +#define IRQ_IXP23XX_SWINT0 13 /* S/W Interrupt0 */ +#define IRQ_IXP23XX_SWINT1 14 /* S/W Interrupt1 */ +#define IRQ_IXP23XX_UART2 15 /* UART1 Interrupt */ +#define IRQ_IXP23XX_UART1 16 /* UART0 Interrupt */ +#define IRQ_IXP23XX_XSI_PMU_ROLLOVER 17 /* AHB Performance M. Unit counter rollover */ +#define IRQ_IXP23XX_XSI_AHB_PM0 18 /* intr_pm_o */ +#define IRQ_IXP23XX_XSI_AHB_ECE0 19 /* intr_ece_o */ +#define IRQ_IXP23XX_XSI_AHB_GASKET 20 /* gas_intr_o */ +#define IRQ_IXP23XX_XSI_CPP 21 /* xsi2cpp_int */ +#define IRQ_IXP23XX_CPP_XSI 22 /* cpp2xsi_int */ +#define IRQ_IXP23XX_ME_ATTN0 23 /* ME_ATTN */ +#define IRQ_IXP23XX_ME_ATTN1 24 /* ME_ATTN */ +#define IRQ_IXP23XX_ME_ATTN2 25 /* ME_ATTN */ +#define IRQ_IXP23XX_ME_ATTN3 26 /* ME_ATTN */ +#define IRQ_IXP23XX_PCI_ERR_RPH 27 /* PCXG_PCI_ERR_RPH */ +#define IRQ_IXP23XX_D0XG_ECC_CORR 28 /* D0XG_DRAM_ECC_CORR */ +#define IRQ_IXP23XX_D0XG_ECC_UNCORR 29 /* D0XG_DRAM_ECC_UNCORR */ +#define IRQ_IXP23XX_SRAM_ERR1 30 /* SRAM1_ERR */ +#define IRQ_IXP23XX_SRAM_ERR0 31 /* SRAM0_ERR */ +#define IRQ_IXP23XX_MEDIA_ERR 32 /* MEDIA_ERR */ +#define IRQ_IXP23XX_STH_DRAM_ECC_MAJ 33 /* STH_DRAM0_ECC_MAJ */ +#define IRQ_IXP23XX_GPIO6 34 /* GPIO0 interrupts */ +#define IRQ_IXP23XX_GPIO7 35 /* GPIO1 interrupts */ +#define IRQ_IXP23XX_GPIO8 36 /* GPIO2 interrupts */ +#define IRQ_IXP23XX_GPIO9 37 /* GPIO3 interrupts */ +#define IRQ_IXP23XX_GPIO10 38 /* GPIO4 interrupts */ +#define IRQ_IXP23XX_GPIO11 39 /* GPIO5 interrupts */ +#define IRQ_IXP23XX_GPIO12 40 /* GPIO6 interrupts */ +#define IRQ_IXP23XX_GPIO13 41 /* GPIO7 interrupts */ +#define IRQ_IXP23XX_GPIO14 42 /* GPIO8 interrupts */ +#define IRQ_IXP23XX_GPIO15 43 /* GPIO9 interrupts */ +#define IRQ_IXP23XX_SHAC_RING0 44 /* SHAC Ring Full */ +#define IRQ_IXP23XX_SHAC_RING1 45 /* SHAC Ring Full */ +#define IRQ_IXP23XX_SHAC_RING2 46 /* SHAC Ring Full */ +#define IRQ_IXP23XX_SHAC_RING3 47 /* SHAC Ring Full */ +#define IRQ_IXP23XX_SHAC_RING4 48 /* SHAC Ring Full */ +#define IRQ_IXP23XX_SHAC_RING5 49 /* SHAC Ring Full */ +#define IRQ_IXP23XX_SHAC_RING6 50 /* SHAC RING Full */ +#define IRQ_IXP23XX_SHAC_RING7 51 /* SHAC Ring Full */ +#define IRQ_IXP23XX_SHAC_RING8 52 /* SHAC Ring Full */ +#define IRQ_IXP23XX_SHAC_RING9 53 /* SHAC Ring Full */ +#define IRQ_IXP23XX_SHAC_RING10 54 /* SHAC Ring Full */ +#define IRQ_IXP23XX_SHAC_RING11 55 /* SHAC Ring Full */ +#define IRQ_IXP23XX_ME_THREAD_A0_ME0 56 /* ME_THREAD_A */ +#define IRQ_IXP23XX_ME_THREAD_A1_ME0 57 /* ME_THREAD_A */ +#define IRQ_IXP23XX_ME_THREAD_A2_ME0 58 /* ME_THREAD_A */ +#define IRQ_IXP23XX_ME_THREAD_A3_ME0 59 /* ME_THREAD_A */ +#define IRQ_IXP23XX_ME_THREAD_A4_ME0 60 /* ME_THREAD_A */ +#define IRQ_IXP23XX_ME_THREAD_A5_ME0 61 /* ME_THREAD_A */ +#define IRQ_IXP23XX_ME_THREAD_A6_ME0 62 /* ME_THREAD_A */ +#define IRQ_IXP23XX_ME_THREAD_A7_ME0 63 /* ME_THREAD_A */ +#define IRQ_IXP23XX_ME_THREAD_A8_ME1 64 /* ME_THREAD_A */ +#define IRQ_IXP23XX_ME_THREAD_A9_ME1 65 /* ME_THREAD_A */ +#define IRQ_IXP23XX_ME_THREAD_A10_ME1 66 /* ME_THREAD_A */ +#define IRQ_IXP23XX_ME_THREAD_A11_ME1 67 /* ME_THREAD_A */ +#define IRQ_IXP23XX_ME_THREAD_A12_ME1 68 /* ME_THREAD_A */ +#define IRQ_IXP23XX_ME_THREAD_A13_ME1 69 /* ME_THREAD_A */ +#define IRQ_IXP23XX_ME_THREAD_A14_ME1 70 /* ME_THREAD_A */ +#define IRQ_IXP23XX_ME_THREAD_A15_ME1 71 /* ME_THREAD_A */ +#define IRQ_IXP23XX_ME_THREAD_A16_ME2 72 /* ME_THREAD_A */ +#define IRQ_IXP23XX_ME_THREAD_A17_ME2 73 /* ME_THREAD_A */ +#define IRQ_IXP23XX_ME_THREAD_A18_ME2 74 /* ME_THREAD_A */ +#define IRQ_IXP23XX_ME_THREAD_A19_ME2 75 /* ME_THREAD_A */ +#define IRQ_IXP23XX_ME_THREAD_A20_ME2 76 /* ME_THREAD_A */ +#define IRQ_IXP23XX_ME_THREAD_A21_ME2 77 /* ME_THREAD_A */ +#define IRQ_IXP23XX_ME_THREAD_A22_ME2 78 /* ME_THREAD_A */ +#define IRQ_IXP23XX_ME_THREAD_A23_ME2 79 /* ME_THREAD_A */ +#define IRQ_IXP23XX_ME_THREAD_A24_ME3 80 /* ME_THREAD_A */ +#define IRQ_IXP23XX_ME_THREAD_A25_ME3 81 /* ME_THREAD_A */ +#define IRQ_IXP23XX_ME_THREAD_A26_ME3 82 /* ME_THREAD_A */ +#define IRQ_IXP23XX_ME_THREAD_A27_ME3 83 /* ME_THREAD_A */ +#define IRQ_IXP23XX_ME_THREAD_A28_ME3 84 /* ME_THREAD_A */ +#define IRQ_IXP23XX_ME_THREAD_A29_ME3 85 /* ME_THREAD_A */ +#define IRQ_IXP23XX_ME_THREAD_A30_ME3 86 /* ME_THREAD_A */ +#define IRQ_IXP23XX_ME_THREAD_A31_ME3 87 /* ME_THREAD_A */ +#define IRQ_IXP23XX_ME_THREAD_B0_ME0 88 /* ME_THREAD_B */ +#define IRQ_IXP23XX_ME_THREAD_B1_ME0 89 /* ME_THREAD_B */ +#define IRQ_IXP23XX_ME_THREAD_B2_ME0 90 /* ME_THREAD_B */ +#define IRQ_IXP23XX_ME_THREAD_B3_ME0 91 /* ME_THREAD_B */ +#define IRQ_IXP23XX_ME_THREAD_B4_ME0 92 /* ME_THREAD_B */ +#define IRQ_IXP23XX_ME_THREAD_B5_ME0 93 /* ME_THREAD_B */ +#define IRQ_IXP23XX_ME_THREAD_B6_ME0 94 /* ME_THREAD_B */ +#define IRQ_IXP23XX_ME_THREAD_B7_ME0 95 /* ME_THREAD_B */ +#define IRQ_IXP23XX_ME_THREAD_B8_ME1 96 /* ME_THREAD_B */ +#define IRQ_IXP23XX_ME_THREAD_B9_ME1 97 /* ME_THREAD_B */ +#define IRQ_IXP23XX_ME_THREAD_B10_ME1 98 /* ME_THREAD_B */ +#define IRQ_IXP23XX_ME_THREAD_B11_ME1 99 /* ME_THREAD_B */ +#define IRQ_IXP23XX_ME_THREAD_B12_ME1 100 /* ME_THREAD_B */ +#define IRQ_IXP23XX_ME_THREAD_B13_ME1 101 /* ME_THREAD_B */ +#define IRQ_IXP23XX_ME_THREAD_B14_ME1 102 /* ME_THREAD_B */ +#define IRQ_IXP23XX_ME_THREAD_B15_ME1 103 /* ME_THREAD_B */ +#define IRQ_IXP23XX_ME_THREAD_B16_ME2 104 /* ME_THREAD_B */ +#define IRQ_IXP23XX_ME_THREAD_B17_ME2 105 /* ME_THREAD_B */ +#define IRQ_IXP23XX_ME_THREAD_B18_ME2 106 /* ME_THREAD_B */ +#define IRQ_IXP23XX_ME_THREAD_B19_ME2 107 /* ME_THREAD_B */ +#define IRQ_IXP23XX_ME_THREAD_B20_ME2 108 /* ME_THREAD_B */ +#define IRQ_IXP23XX_ME_THREAD_B21_ME2 109 /* ME_THREAD_B */ +#define IRQ_IXP23XX_ME_THREAD_B22_ME2 110 /* ME_THREAD_B */ +#define IRQ_IXP23XX_ME_THREAD_B23_ME2 111 /* ME_THREAD_B */ +#define IRQ_IXP23XX_ME_THREAD_B24_ME3 112 /* ME_THREAD_B */ +#define IRQ_IXP23XX_ME_THREAD_B25_ME3 113 /* ME_THREAD_B */ +#define IRQ_IXP23XX_ME_THREAD_B26_ME3 114 /* ME_THREAD_B */ +#define IRQ_IXP23XX_ME_THREAD_B27_ME3 115 /* ME_THREAD_B */ +#define IRQ_IXP23XX_ME_THREAD_B28_ME3 116 /* ME_THREAD_B */ +#define IRQ_IXP23XX_ME_THREAD_B29_ME3 117 /* ME_THREAD_B */ +#define IRQ_IXP23XX_ME_THREAD_B30_ME3 118 /* ME_THREAD_B */ +#define IRQ_IXP23XX_ME_THREAD_B31_ME3 119 /* ME_THREAD_B */ + +#define NUM_IXP23XX_RAW_IRQS 120 + +#define IRQ_IXP23XX_INTA 120 /* Indirect pcxg_pci_int_rph */ +#define IRQ_IXP23XX_INTB 121 /* Indirect pcxg_pci_int_rph */ + +#define NR_IXP23XX_IRQ (IRQ_IXP23XX_INTB + 1) + +/* + * We default to 32 per-board IRQs. Increase this number if you need + * more, but keep it realistic. + */ +#define NR_IXP23XX_MACH_IRQS 32 + +#define NR_IRQS NR_IXP23XX_IRQS + NR_IXP23XX_MACH_IRQS + +#define IXP23XX_MACH_IRQ(irq) (NR_IXP23XX_IRQ + (irq)) + + +/* + * IXDP2351-specific interrupts + */ + +/* + * External PCI interrupts signaled through INTB + * + */ +#define IXDP2351_INTB_IRQ_BASE 0 +#define IRQ_IXDP2351_INTA_82546 IXP23XX_MACH_IRQ(0) +#define IRQ_IXDP2351_INTB_82546 IXP23XX_MACH_IRQ(1) +#define IRQ_IXDP2351_SPCI_DB_0 IXP23XX_MACH_IRQ(2) +#define IRQ_IXDP2351_SPCI_DB_1 IXP23XX_MACH_IRQ(3) +#define IRQ_IXDP2351_SPCI_PMC_INTA IXP23XX_MACH_IRQ(4) +#define IRQ_IXDP2351_SPCI_PMC_INTB IXP23XX_MACH_IRQ(5) +#define IRQ_IXDP2351_SPCI_PMC_INTC IXP23XX_MACH_IRQ(6) +#define IRQ_IXDP2351_SPCI_PMC_INTD IXP23XX_MACH_IRQ(7) +#define IRQ_IXDP2351_SPCI_FIC IXP23XX_MACH_IRQ(8) + +#define IXDP2351_INTB_IRQ_BIT(irq) (irq - IXP23XX_MACH_IRQ(0)) +#define IXDP2351_INTB_IRQ_MASK(irq) (1 << IXDP2351_INTB_IRQ_BIT(irq)) +#define IXDP2351_INTB_IRQ_VALID 0x01FF +#define IXDP2351_INTB_IRQ_NUM 16 + +/* + * Other external interrupts signaled through INTA + */ +#define IXDP2351_INTA_IRQ_BASE 16 +#define IRQ_IXDP2351_IPMI_FROM IXP23XX_MACH_IRQ(16) +#define IRQ_IXDP2351_125US IXP23XX_MACH_IRQ(17) +#define IRQ_IXDP2351_DB_0_ADD IXP23XX_MACH_IRQ(18) +#define IRQ_IXDP2351_DB_1_ADD IXP23XX_MACH_IRQ(19) +#define IRQ_IXDP2351_DEBUG1 IXP23XX_MACH_IRQ(20) +#define IRQ_IXDP2351_ADD_UART IXP23XX_MACH_IRQ(21) +#define IRQ_IXDP2351_FIC_ADD IXP23XX_MACH_IRQ(24) +#define IRQ_IXDP2351_CS8900 IXP23XX_MACH_IRQ(25) +#define IRQ_IXDP2351_BBSRAM IXP23XX_MACH_IRQ(26) +#define IRQ_IXDP2351_CONFIG_MEDIA IXP23XX_MACH_IRQ(27) +#define IRQ_IXDP2351_CLOCK_REF IXP23XX_MACH_IRQ(28) +#define IRQ_IXDP2351_A10_NP IXP23XX_MACH_IRQ(29) +#define IRQ_IXDP2351_A11_NP IXP23XX_MACH_IRQ(30) +#define IRQ_IXDP2351_DEBUG_NP IXP23XX_MACH_IRQ(31) + +#define IXDP2351_INTA_IRQ_BIT(irq) (irq - IXP23XX_MACH_IRQ(16)) +#define IXDP2351_INTA_IRQ_MASK(irq) (1 << IXDP2351_INTA_IRQ_BIT(irq)) +#define IXDP2351_INTA_IRQ_VALID 0xFF3F +#define IXDP2351_INTA_IRQ_NUM 16 + + +/* + * ADI RoadRunner IRQs + */ +#define IRQ_ROADRUNNER_PCI_INTA IRQ_IXP23XX_INTA +#define IRQ_ROADRUNNER_PCI_INTB IRQ_IXP23XX_INTB +#define IRQ_ROADRUNNER_PCI_INTC IRQ_IXP23XX_GPIO11 +#define IRQ_ROADRUNNER_PCI_INTD IRQ_IXP23XX_GPIO12 + +/* + * Put new board definitions here + */ + + +#endif diff --git a/include/asm-arm/arch-ixp23xx/ixdp2351.h b/include/asm-arm/arch-ixp23xx/ixdp2351.h new file mode 100644 index 00000000000..4a24f8f1565 --- /dev/null +++ b/include/asm-arm/arch-ixp23xx/ixdp2351.h @@ -0,0 +1,89 @@ +/* + * include/asm-arm/arch-ixp23xx/ixdp2351.h + * + * Register and other defines for IXDP2351 + * + * Copyright (c) 2002-2004 Intel Corp. + * Copytight (c) 2005 MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef __ASM_ARCH_IXDP2351_H +#define __ASM_ARCH_IXDP2351_H + +/* + * NP module memory map + */ +#define IXDP2351_NP_PHYS_BASE (IXP23XX_EXP_BUS_CS4_BASE) +#define IXDP2351_NP_PHYS_SIZE 0x00100000 +#define IXDP2351_NP_VIRT_BASE 0xeff00000 + +#define IXDP2351_VIRT_CS8900_BASE (IXDP2351_NP_VIRT_BASE) +#define IXDP2351_VIRT_CS8900_END (IXDP2351_VIRT_CS8900_BASE + 16) + +#define IXDP2351_VIRT_NP_CPLD_BASE (IXP23XX_EXP_BUS_CS4_BASE_VIRT + 0x00010000) + +#define IXDP2351_NP_CPLD_REG(reg) ((volatile u16 *)(IXDP2351_VIRT_NP_CPLD_BASE + reg)) + +#define IXDP2351_NP_CPLD_RESET1_REG IXDP2351_NP_CPLD_REG(0x00) +#define IXDP2351_NP_CPLD_LED_REG IXDP2351_NP_CPLD_REG(0x02) +#define IXDP2351_NP_CPLD_VERSION_REG IXDP2351_NP_CPLD_REG(0x04) + +/* + * Base board module memory map + */ + +#define IXDP2351_BB_BASE_PHYS (IXP23XX_EXP_BUS_CS5_BASE) +#define IXDP2351_BB_SIZE 0x01000000 +#define IXDP2351_BB_BASE_VIRT (0xee000000) + +#define IXDP2351_BB_AREA_BASE(offset) (IXDP2351_BB_BASE_VIRT + offset) + +#define IXDP2351_VIRT_NVRAM_BASE IXDP2351_BB_AREA_BASE(0x0) +#define IXDP2351_NVRAM_SIZE (0x20000) + +#define IXDP2351_VIRT_MB_IXF1104_BASE IXDP3251_BB_AREA_BASE(0x00020000) +#define IXDP2351_VIRT_ADD_UART_BASE IXDP2351_BB_AREA_BASE(0x000240C0) +#define IXDP2351_VIRT_FIC_BASE IXDP2351_BB_AREA_BASE(0x00200000) +#define IXDP2351_VIRT_DB0_BASE IXDP2351_BB_AREA_BASE(0x00400000) +#define IXDP2351_VIRT_DB1_BASE IXDP2351_BB_AREA_BASE(0x00600000) +#define IXDP2351_VIRT_CPLD_BASE IXDP2351_BB_AREA_BASE(0x00024000) + +/* + * On board CPLD registers + */ +#define IXDP2351_CPLD_BB_REG(reg) ((volatile u16 *)(IXDP2351_VIRT_CPLD_BASE + reg)) + +#define IXDP2351_CPLD_RESET0_REG IXDP2351_CPLD_BB_REG(0x00) +#define IXDP2351_CPLD_RESET1_REG IXDP2351_CPLD_BB_REG(0x04) + +#define IXDP2351_CPLD_RESET1_MAGIC 0x55AA +#define IXDP2351_CPLD_RESET1_ENABLE 0x8000 + +#define IXDP2351_CPLD_FPGA_CONFIG_REG IXDP2351_CPLD_BB_REG(0x08) +#define IXDP2351_CPLD_INTB_MASK_SET_REG IXDP2351_CPLD_BB_REG(0x10) +#define IXDP2351_CPLD_INTA_MASK_SET_REG IXDP2351_CPLD_BB_REG(0x14) +#define IXDP2351_CPLD_INTB_STAT_REG IXDP2351_CPLD_BB_REG(0x18) +#define IXDP2351_CPLD_INTA_STAT_REG IXDP2351_CPLD_BB_REG(0x1C) +#define IXDP2351_CPLD_INTB_RAW_REG IXDP2351_CPLD_BB_REG(0x20) /* read */ +#define IXDP2351_CPLD_INTA_RAW_REG IXDP2351_CPLD_BB_REG(0x24) /* read */ +#define IXDP2351_CPLD_INTB_MASK_CLR_REG IXDP2351_CPLD_INTB_RAW_REG /* write */ +#define IXDP2351_CPLD_INTA_MASK_CLR_REG IXDP2351_CPLD_INTA_RAW_REG /* write */ +#define IXDP2351_CPLD_INTB_SIM_REG IXDP2351_CPLD_BB_REG(0x28) +#define IXDP2351_CPLD_INTA_SIM_REG IXDP2351_CPLD_BB_REG(0x2C) + /* Interrupt bits are defined in irqs.h */ +#define IXDP2351_CPLD_BB_GBE0_REG IXDP2351_CPLD_BB_REG(0x30) +#define IXDP2351_CPLD_BB_GBE1_REG IXDP2351_CPLD_BB_REG(0x34) + +/* #define IXDP2351_CPLD_BB_MISC_REG IXDP2351_CPLD_REG(0x1C) */ +/* #define IXDP2351_CPLD_BB_MISC_REV_MASK 0xFF */ +/* #define IXDP2351_CPLD_BB_GDXCS0_REG IXDP2351_CPLD_REG(0x24) */ +/* #define IXDP2351_CPLD_BB_GDXCS1_REG IXDP2351_CPLD_REG(0x28) */ +/* #define IXDP2351_CPLD_BB_CLOCK_REG IXDP2351_CPLD_REG(0x04) */ + + +#endif diff --git a/include/asm-arm/arch-ixp23xx/ixp23xx.h b/include/asm-arm/arch-ixp23xx/ixp23xx.h new file mode 100644 index 00000000000..e49e1ca61b1 --- /dev/null +++ b/include/asm-arm/arch-ixp23xx/ixp23xx.h @@ -0,0 +1,306 @@ +/* + * include/asm-arm/arch-ixp23xx/ixp23xx.h + * + * Register definitions for IXP23XX + * + * Copyright (C) 2003-2005 Intel Corporation. + * Copyright (C) 2005 MontaVista Software, Inc. + * + * Maintainer: Deepak Saxena <dsaxena@plexity.net> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_IXP23XX_H +#define __ASM_ARCH_IXP23XX_H + +/* + * IXP2300 linux memory map: + * + * virt phys size + * fffd0000 a0000000 64K XSI2CPP_CSR + * fffc0000 c4000000 4K EXP_CFG + * fff00000 c8000000 64K PERIPHERAL + * fe000000 1c0000000 16M CAP_CSR + * fd000000 1c8000000 16M MSF_CSR + * fb000000 16M --- + * fa000000 1d8000000 32M PCI_IO + * f8000000 1da000000 32M PCI_CFG + * f6000000 1de000000 32M PCI_CREG + * f4000000 32M --- + * f0000000 1e0000000 64M PCI_MEM + * e[c-f]000000 per-platform mappings + */ + + +/**************************************************************************** + * Static mappings. + ****************************************************************************/ +#define IXP23XX_XSI2CPP_CSR_PHYS 0xa0000000 +#define IXP23XX_XSI2CPP_CSR_VIRT 0xfffd0000 +#define IXP23XX_XSI2CPP_CSR_SIZE 0x00010000 + +#define IXP23XX_EXP_CFG_PHYS 0xc4000000 +#define IXP23XX_EXP_CFG_VIRT 0xfffc0000 +#define IXP23XX_EXP_CFG_SIZE 0x00001000 + +#define IXP23XX_PERIPHERAL_PHYS 0xc8000000 +#define IXP23XX_PERIPHERAL_VIRT 0xfff00000 +#define IXP23XX_PERIPHERAL_SIZE 0x00010000 + +#define IXP23XX_CAP_CSR_PHYS 0x1c0000000ULL +#define IXP23XX_CAP_CSR_VIRT 0xfe000000 +#define IXP23XX_CAP_CSR_SIZE 0x01000000 + +#define IXP23XX_MSF_CSR_PHYS 0x1c8000000ULL +#define IXP23XX_MSF_CSR_VIRT 0xfd000000 +#define IXP23XX_MSF_CSR_SIZE 0x01000000 + +#define IXP23XX_PCI_IO_PHYS 0x1d8000000ULL +#define IXP23XX_PCI_IO_VIRT 0xfa000000 +#define IXP23XX_PCI_IO_SIZE 0x02000000 + +#define IXP23XX_PCI_CFG_PHYS 0x1da000000ULL +#define IXP23XX_PCI_CFG_VIRT 0xf8000000 +#define IXP23XX_PCI_CFG_SIZE 0x02000000 +#define IXP23XX_PCI_CFG0_VIRT IXP23XX_PCI_CFG_VIRT +#define IXP23XX_PCI_CFG1_VIRT (IXP23XX_PCI_CFG_VIRT + 0x01000000) + +#define IXP23XX_PCI_CREG_PHYS 0x1de000000ULL +#define IXP23XX_PCI_CREG_VIRT 0xf6000000 +#define IXP23XX_PCI_CREG_SIZE 0x02000000 +#define IXP23XX_PCI_CSR_VIRT (IXP23XX_PCI_CREG_VIRT + 0x01000000) + +#define IXP23XX_PCI_MEM_START 0xe0000000 +#define IXP23XX_PCI_MEM_PHYS 0x1e0000000ULL +#define IXP23XX_PCI_MEM_VIRT 0xf0000000 +#define IXP23XX_PCI_MEM_SIZE 0x04000000 + + +/**************************************************************************** + * XSI2CPP CSRs. + ****************************************************************************/ +#define IXP23XX_XSI2CPP_REG(x) ((volatile unsigned long *)(IXP23XX_XSI2CPP_CSR_VIRT + (x))) +#define IXP23XX_CPP2XSI_CURR_XFER_REG3 IXP23XX_XSI2CPP_REG(0xf8) +#define IXP23XX_CPP2XSI_ADDR_31 (1 << 19) +#define IXP23XX_CPP2XSI_PSH_OFF (1 << 20) +#define IXP23XX_CPP2XSI_COH_OFF (1 << 21) + + +/**************************************************************************** + * Expansion Bus Config. + ****************************************************************************/ +#define IXP23XX_EXP_CFG_REG(x) ((volatile unsigned long *)(IXP23XX_EXP_CFG_VIRT + (x))) +#define IXP23XX_EXP_CS0 IXP23XX_EXP_CFG_REG(0x00) +#define IXP23XX_EXP_CS1 IXP23XX_EXP_CFG_REG(0x04) +#define IXP23XX_EXP_CS2 IXP23XX_EXP_CFG_REG(0x08) +#define IXP23XX_EXP_CS3 IXP23XX_EXP_CFG_REG(0x0c) +#define IXP23XX_EXP_CS4 IXP23XX_EXP_CFG_REG(0x10) +#define IXP23XX_EXP_CS5 IXP23XX_EXP_CFG_REG(0x14) +#define IXP23XX_EXP_CS6 IXP23XX_EXP_CFG_REG(0x18) +#define IXP23XX_EXP_CS7 IXP23XX_EXP_CFG_REG(0x1c) +#define IXP23XX_FLASH_WRITABLE (0x2) +#define IXP23XX_FLASH_BUS8 (0x1) + +#define IXP23XX_EXP_CFG0 IXP23XX_EXP_CFG_REG(0x20) +#define IXP23XX_EXP_CFG1 IXP23XX_EXP_CFG_REG(0x24) +#define IXP23XX_EXP_CFG0_MEM_MAP (1 << 31) +#define IXP23XX_EXP_CFG0_XSCALE_SPEED_SEL (3 << 22) +#define IXP23XX_EXP_CFG0_XSCALE_SPEED_EN (1 << 21) +#define IXP23XX_EXP_CFG0_CPP_SPEED_SEL (3 << 19) +#define IXP23XX_EXP_CFG0_CPP_SPEED_EN (1 << 18) +#define IXP23XX_EXP_CFG0_PCI_SWIN (3 << 16) +#define IXP23XX_EXP_CFG0_PCI_DWIN (3 << 14) +#define IXP23XX_EXP_CFG0_PCI33_MODE (1 << 13) +#define IXP23XX_EXP_CFG0_QDR_SPEED_SEL (1 << 12) +#define IXP23XX_EXP_CFG0_CPP_DIV_SEL (1 << 5) +#define IXP23XX_EXP_CFG0_XSI_NOT_PRES (1 << 4) +#define IXP23XX_EXP_CFG0_PROM_BOOT (1 << 3) +#define IXP23XX_EXP_CFG0_PCI_ARB (1 << 2) +#define IXP23XX_EXP_CFG0_PCI_HOST (1 << 1) +#define IXP23XX_EXP_CFG0_FLASH_WIDTH (1 << 0) + +#define IXP23XX_EXP_UNIT_FUSE IXP23XX_EXP_CFG_REG(0x28) +#define IXP23XX_EXP_MSF_MUX IXP23XX_EXP_CFG_REG(0x30) + +#define IXP23XX_EXP_BUS_PHYS 0x90000000 +#define IXP23XX_EXP_BUS_WINDOW_SIZE 0x01000000 + +#define IXP23XX_EXP_BUS_CS0_BASE (IXP23XX_EXP_BUS_PHYS + 0x00000000) +#define IXP23XX_EXP_BUS_CS1_BASE (IXP23XX_EXP_BUS_PHYS + 0x01000000) +#define IXP23XX_EXP_BUS_CS2_BASE (IXP23XX_EXP_BUS_PHYS + 0x02000000) +#define IXP23XX_EXP_BUS_CS3_BASE (IXP23XX_EXP_BUS_PHYS + 0x03000000) +#define IXP23XX_EXP_BUS_CS4_BASE (IXP23XX_EXP_BUS_PHYS + 0x04000000) +#define IXP23XX_EXP_BUS_CS5_BASE (IXP23XX_EXP_BUS_PHYS + 0x05000000) +#define IXP23XX_EXP_BUS_CS6_BASE (IXP23XX_EXP_BUS_PHYS + 0x06000000) +#define IXP23XX_EXP_BUS_CS7_BASE (IXP23XX_EXP_BUS_PHYS + 0x07000000) + + +/**************************************************************************** + * Peripherals. + ****************************************************************************/ +#define IXP23XX_UART1_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x0000) +#define IXP23XX_UART2_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x1000) +#define IXP23XX_PMU_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x2000) +#define IXP23XX_INTC_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x3000) +#define IXP23XX_GPIO_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x4000) +#define IXP23XX_TIMER_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x5000) +#define IXP23XX_NPE0_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x6000) +#define IXP23XX_DSR_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x7000) +#define IXP23XX_NPE1_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x8000) +#define IXP23XX_ETH0_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x9000) +#define IXP23XX_ETH1_VIRT (IXP23XX_PERIPHERAL_VIRT + 0xA000) +#define IXP23XX_GIG0_VIRT (IXP23XX_PERIPHERAL_VIRT + 0xB000) +#define IXP23XX_GIG1_VIRT (IXP23XX_PERIPHERAL_VIRT + 0xC000) +#define IXP23XX_DDRS_VIRT (IXP23XX_PERIPHERAL_VIRT + 0xD000) + +#define IXP23XX_UART1_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x0000) +#define IXP23XX_UART2_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x1000) +#define IXP23XX_PMU_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x2000) +#define IXP23XX_INTC_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x3000) +#define IXP23XX_GPIO_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x4000) +#define IXP23XX_TIMER_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x5000) +#define IXP23XX_NPE0_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x6000) +#define IXP23XX_DSR_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x7000) +#define IXP23XX_NPE1_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x8000) +#define IXP23XX_ETH0_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x9000) +#define IXP23XX_ETH1_PHYS (IXP23XX_PERIPHERAL_PHYS + 0xA000) +#define IXP23XX_GIG0_PHYS (IXP23XX_PERIPHERAL_PHYS + 0xB000) +#define IXP23XX_GIG1_PHYS (IXP23XX_PERIPHERAL_PHYS + 0xC000) +#define IXP23XX_DDRS_PHYS (IXP23XX_PERIPHERAL_PHYS + 0xD000) + + +/**************************************************************************** + * Interrupt controller. + ****************************************************************************/ +#define IXP23XX_INTC_REG(x) ((volatile unsigned long *)(IXP23XX_INTC_VIRT + (x))) +#define IXP23XX_INTR_ST1 IXP23XX_INTC_REG(0x00) +#define IXP23XX_INTR_ST2 IXP23XX_INTC_REG(0x04) +#define IXP23XX_INTR_ST3 IXP23XX_INTC_REG(0x08) +#define IXP23XX_INTR_ST4 IXP23XX_INTC_REG(0x0c) +#define IXP23XX_INTR_EN1 IXP23XX_INTC_REG(0x10) +#define IXP23XX_INTR_EN2 IXP23XX_INTC_REG(0x14) +#define IXP23XX_INTR_EN3 IXP23XX_INTC_REG(0x18) +#define IXP23XX_INTR_EN4 IXP23XX_INTC_REG(0x1c) +#define IXP23XX_INTR_SEL1 IXP23XX_INTC_REG(0x20) +#define IXP23XX_INTR_SEL2 IXP23XX_INTC_REG(0x24) +#define IXP23XX_INTR_SEL3 IXP23XX_INTC_REG(0x28) +#define IXP23XX_INTR_SEL4 IXP23XX_INTC_REG(0x2c) +#define IXP23XX_INTR_IRQ_ST1 IXP23XX_INTC_REG(0x30) +#define IXP23XX_INTR_IRQ_ST2 IXP23XX_INTC_REG(0x34) +#define IXP23XX_INTR_IRQ_ST3 IXP23XX_INTC_REG(0x38) +#define IXP23XX_INTR_IRQ_ST4 IXP23XX_INTC_REG(0x3c) +#define IXP23XX_INTR_IRQ_ENC_ST_OFFSET 0x54 + + +/**************************************************************************** + * GPIO. + ****************************************************************************/ +#define IXP23XX_GPIO_REG(x) ((volatile unsigned long *)(IXP23XX_GPIO_VIRT + (x))) +#define IXP23XX_GPIO_GPOUTR IXP23XX_GPIO_REG(0x00) +#define IXP23XX_GPIO_GPOER IXP23XX_GPIO_REG(0x04) +#define IXP23XX_GPIO_GPINR IXP23XX_GPIO_REG(0x08) +#define IXP23XX_GPIO_GPISR IXP23XX_GPIO_REG(0x0c) +#define IXP23XX_GPIO_GPIT1R IXP23XX_GPIO_REG(0x10) +#define IXP23XX_GPIO_GPIT2R IXP23XX_GPIO_REG(0x14) +#define IXP23XX_GPIO_GPCLKR IXP23XX_GPIO_REG(0x18) +#define IXP23XX_GPIO_GPDBSELR IXP23XX_GPIO_REG(0x1c) + +#define IXP23XX_GPIO_STYLE_MASK 0x7 +#define IXP23XX_GPIO_STYLE_ACTIVE_HIGH 0x0 +#define IXP23XX_GPIO_STYLE_ACTIVE_LOW 0x1 +#define IXP23XX_GPIO_STYLE_RISING_EDGE 0x2 +#define IXP23XX_GPIO_STYLE_FALLING_EDGE 0x3 +#define IXP23XX_GPIO_STYLE_TRANSITIONAL 0x4 + +#define IXP23XX_GPIO_STYLE_SIZE 3 + + +/**************************************************************************** + * Timer. + ****************************************************************************/ +#define IXP23XX_TIMER_REG(x) ((volatile unsigned long *)(IXP23XX_TIMER_VIRT + (x))) +#define IXP23XX_TIMER_CONT IXP23XX_TIMER_REG(0x00) +#define IXP23XX_TIMER1_TIMESTAMP IXP23XX_TIMER_REG(0x04) +#define IXP23XX_TIMER1_RELOAD IXP23XX_TIMER_REG(0x08) +#define IXP23XX_TIMER2_TIMESTAMP IXP23XX_TIMER_REG(0x0c) +#define IXP23XX_TIMER2_RELOAD IXP23XX_TIMER_REG(0x10) +#define IXP23XX_TIMER_WDOG IXP23XX_TIMER_REG(0x14) +#define IXP23XX_TIMER_WDOG_EN IXP23XX_TIMER_REG(0x18) +#define IXP23XX_TIMER_WDOG_KEY IXP23XX_TIMER_REG(0x1c) +#define IXP23XX_TIMER_WDOG_KEY_MAGIC 0x482e +#define IXP23XX_TIMER_STATUS IXP23XX_TIMER_REG(0x20) +#define IXP23XX_TIMER_SOFT_RESET IXP23XX_TIMER_REG(0x24) +#define IXP23XX_TIMER_SOFT_RESET_EN IXP23XX_TIMER_REG(0x28) + +#define IXP23XX_TIMER_ENABLE (1 << 0) +#define IXP23XX_TIMER_ONE_SHOT (1 << 1) +/* Low order bits of reload value ignored */ +#define IXP23XX_TIMER_RELOAD_MASK (0x3) +#define IXP23XX_TIMER_DISABLED (0x0) +#define IXP23XX_TIMER1_INT_PEND (1 << 0) +#define IXP23XX_TIMER2_INT_PEND (1 << 1) +#define IXP23XX_TIMER_STATUS_TS_PEND (1 << 2) +#define IXP23XX_TIMER_STATUS_WDOG_PEND (1 << 3) +#define IXP23XX_TIMER_STATUS_WARM_RESET (1 << 4) + + +/**************************************************************************** + * CAP CSRs. + ****************************************************************************/ +#define IXP23XX_GLOBAL_REG(x) ((volatile unsigned long *)(IXP23XX_CAP_CSR_VIRT + 0x4a00 + (x))) +#define IXP23XX_PROD_IDG IXP23XX_GLOBAL_REG(0x00) +#define IXP23XX_MISC_CONTROL IXP23XX_GLOBAL_REG(0x04) +#define IXP23XX_MSF_CLK_CNTRL IXP23XX_GLOBAL_REG(0x08) +#define IXP23XX_RESET0 IXP23XX_GLOBAL_REG(0x0c) +#define IXP23XX_RESET1 IXP23XX_GLOBAL_REG(0x10) +#define IXP23XX_STRAP_OPTIONS IXP23XX_GLOBAL_REG(0x18) + +#define IXP23XX_ENABLE_WATCHDOG (1 << 24) +#define IXP23XX_SHPC_INIT_COMP (1 << 21) +#define IXP23XX_RST_ALL (1 << 16) +#define IXP23XX_RESET_PCI (1 << 2) +#define IXP23XX_PCI_UNIT_RESET (1 << 1) +#define IXP23XX_XSCALE_RESET (1 << 0) + + +/**************************************************************************** + * PCI CSRs. + ****************************************************************************/ +#define IXP23XX_PCI_CREG(x) ((volatile unsigned long *)(IXP23XX_PCI_CREG_VIRT + (x))) +#define IXP23XX_PCI_CMDSTAT IXP23XX_PCI_CREG(0x04) +#define IXP23XX_PCI_SRAM_BAR IXP23XX_PCI_CREG(0x14) +#define IXP23XX_PCI_SDRAM_BAR IXP23XX_PCI_CREG(0x18) + + +#define IXP23XX_PCI_CSR(x) ((volatile unsigned long *)(IXP23XX_PCI_CREG_VIRT + 0x01000000 + (x))) +#define IXP23XX_PCI_OUT_INT_STATUS IXP23XX_PCI_CSR(0x0030) +#define IXP23XX_PCI_OUT_INT_MASK IXP23XX_PCI_CSR(0x0034) +#define IXP23XX_PCI_SRAM_BASE_ADDR_MASK IXP23XX_PCI_CSR(0x00fc) +#define IXP23XX_PCI_DRAM_BASE_ADDR_MASK IXP23XX_PCI_CSR(0x0100) +#define IXP23XX_PCI_CONTROL IXP23XX_PCI_CSR(0x013c) +#define IXP23XX_PCI_ADDR_EXT IXP23XX_PCI_CSR(0x0140) +#define IXP23XX_PCI_ME_PUSH_STATUS IXP23XX_PCI_CSR(0x0148) +#define IXP23XX_PCI_ME_PUSH_EN IXP23XX_PCI_CSR(0x014c) +#define IXP23XX_PCI_ERR_STATUS IXP23XX_PCI_CSR(0x0150) +#define IXP23XX_PCI_ERROR_STATUS IXP23XX_PCI_CSR(0x0150) +#define IXP23XX_PCI_ERR_ENABLE IXP23XX_PCI_CSR(0x0154) +#define IXP23XX_PCI_XSCALE_INT_STATUS IXP23XX_PCI_CSR(0x0158) +#define IXP23XX_PCI_XSCALE_INT_ENABLE IXP23XX_PCI_CSR(0x015c) +#define IXP23XX_PCI_CPP_ADDR_BITS IXP23XX_PCI_CSR(0x0160) + + +#ifndef __ASSEMBLY__ +/* + * Is system memory on the XSI or CPP bus? + */ +static inline unsigned ixp23xx_cpp_boot(void) +{ + return (*IXP23XX_EXP_CFG0 & IXP23XX_EXP_CFG0_XSI_NOT_PRES); +} +#endif + + +#endif diff --git a/include/asm-arm/arch-ixp23xx/memory.h b/include/asm-arm/arch-ixp23xx/memory.h new file mode 100644 index 00000000000..bebcf0aa0d7 --- /dev/null +++ b/include/asm-arm/arch-ixp23xx/memory.h @@ -0,0 +1,46 @@ +/* + * include/asm-arm/arch-ixp23xx/memory.h + * + * Copyright (c) 2003-2004 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef __ASM_ARCH_MEMORY_H +#define __ASM_ARCH_MEMORY_H + +#include <asm/hardware.h> + +/* + * Physical DRAM offset. + */ +#define PHYS_OFFSET (0x00000000) + + +/* + * Virtual view <-> DMA view memory address translations + * virt_to_bus: Used to translate the virtual address to an + * address suitable to be passed to set_dma_addr + * bus_to_virt: Used to convert an address for DMA operations + * to an address that the kernel can use. + */ +#ifndef __ASSEMBLY__ + +#define __virt_to_bus(v) \ + ({ unsigned int ret; \ + ret = ((__virt_to_phys(v) - 0x00000000) + \ + (*((volatile int *)IXP23XX_PCI_SDRAM_BAR) & 0xfffffff0)); \ + ret; }) + +#define __bus_to_virt(b) \ + ({ unsigned int data; \ + data = *((volatile int *)IXP23XX_PCI_SDRAM_BAR); \ + __phys_to_virt((((b - (data & 0xfffffff0)) + 0x00000000))); }) + +#endif + + +#endif diff --git a/include/asm-arm/arch-ixp23xx/platform.h b/include/asm-arm/arch-ixp23xx/platform.h new file mode 100644 index 00000000000..f85b4685a49 --- /dev/null +++ b/include/asm-arm/arch-ixp23xx/platform.h @@ -0,0 +1,31 @@ +/* + * include/asm-arm/arch-ixp23xx/platform.h + * + * Various bits of code used by platform-level code. + * + * Author: Deepak Saxena <dsaxena@plexity.net> + * + * Copyright 2005 (c) MontaVista Software, Inc. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASSEMBLY__ + +struct pci_sys_data; + +void ixp23xx_map_io(void); +void ixp23xx_init_irq(void); +void ixp23xx_sys_init(void); +int ixp23xx_pci_setup(int, struct pci_sys_data *); +void ixp23xx_pci_preinit(void); +struct pci_bus *ixp23xx_pci_scan_bus(int, struct pci_sys_data*); + +extern struct sys_timer ixp23xx_timer; + +#define IXP23XX_UART_XTAL 14745600 + + +#endif diff --git a/include/asm-arm/arch-ixp23xx/system.h b/include/asm-arm/arch-ixp23xx/system.h new file mode 100644 index 00000000000..925e6b0c338 --- /dev/null +++ b/include/asm-arm/arch-ixp23xx/system.h @@ -0,0 +1,33 @@ +/* + * include/asm-arm/arch-ixp23xx/system.h + * + * Copyright (C) 2003 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <asm/hardware.h> +#include <asm/mach-types.h> + +static inline void arch_idle(void) +{ +#if 0 + if (!hlt_counter) + cpu_do_idle(); +#endif +} + +static inline void arch_reset(char mode) +{ + /* First try machine specific support */ + if (machine_is_ixdp2351()) { + *IXDP2351_CPLD_RESET1_REG = IXDP2351_CPLD_RESET1_MAGIC; + (void) *IXDP2351_CPLD_RESET1_REG; + *IXDP2351_CPLD_RESET1_REG = IXDP2351_CPLD_RESET1_ENABLE; + } + + /* Use on-chip reset capability */ + *IXP23XX_RESET0 |= IXP23XX_RST_ALL; +} diff --git a/include/asm-arm/arch-ixp23xx/time.h b/include/asm-arm/arch-ixp23xx/time.h new file mode 100644 index 00000000000..f6828fdd288 --- /dev/null +++ b/include/asm-arm/arch-ixp23xx/time.h @@ -0,0 +1,3 @@ +/* + * include/asm-arm/arch-ixp23xx/time.h + */ diff --git a/include/asm-arm/arch-ixp23xx/timex.h b/include/asm-arm/arch-ixp23xx/timex.h new file mode 100644 index 00000000000..516f72fe608 --- /dev/null +++ b/include/asm-arm/arch-ixp23xx/timex.h @@ -0,0 +1,7 @@ +/* + * include/asm-arm/arch-ixp23xx/timex.h + * + * XScale architecture timex specifications + */ + +#define CLOCK_TICK_RATE 75000000 diff --git a/include/asm-arm/arch-ixp23xx/uncompress.h b/include/asm-arm/arch-ixp23xx/uncompress.h new file mode 100644 index 00000000000..62623fa9b2f --- /dev/null +++ b/include/asm-arm/arch-ixp23xx/uncompress.h @@ -0,0 +1,45 @@ +/* + * include/asm-arm/arch-ixp23xx/uncompress.h + * + * Copyright (C) 2002-2004 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_UNCOMPRESS_H +#define __ASM_ARCH_UNCOMPRESS_H + +#include <asm/hardware.h> +#include <linux/serial_reg.h> + +#define UART_BASE ((volatile u32 *)IXP23XX_UART1_PHYS) + +static __inline__ void putc(char c) +{ + int j; + + for (j = 0; j < 0x1000; j++) { + if (UART_BASE[UART_LSR] & UART_LSR_THRE) + break; + } + + UART_BASE[UART_TX] = c; +} + +static void putstr(const char *s) +{ + while (*s) { + putc(*s); + if (*s == '\n') + putc('\r'); + s++; + } +} + +#define arch_decomp_setup() +#define arch_decomp_wdog() + + +#endif diff --git a/include/asm-arm/arch-ixp23xx/vmalloc.h b/include/asm-arm/arch-ixp23xx/vmalloc.h new file mode 100644 index 00000000000..9f256665854 --- /dev/null +++ b/include/asm-arm/arch-ixp23xx/vmalloc.h @@ -0,0 +1,10 @@ +/* + * include/asm-arm/arch-ixp23xx/vmalloc.h + * + * Copyright (c) 2005 MontaVista Software, Inc. + * + * NPU mappings end at 0xf0000000 and we allocate 64MB for board + * specific static I/O. + */ + +#define VMALLOC_END (0xec000000) diff --git a/include/asm-arm/arch-ixp4xx/uncompress.h b/include/asm-arm/arch-ixp4xx/uncompress.h index 960c35810a2..09ae6c91be6 100644 --- a/include/asm-arm/arch-ixp4xx/uncompress.h +++ b/include/asm-arm/arch-ixp4xx/uncompress.h @@ -21,26 +21,18 @@ static volatile u32* uart_base; -static __inline__ void putc(char c) +static inline void putc(int c) { /* Check THRE and TEMT bits before we transmit the character. */ - while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE); + while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE) + barrier(); + *uart_base = c; } -/* - * This does not append a newline - */ -static void putstr(const char *s) +static void flush(void) { - while (*s) - { - putc(*s); - if (*s == '\n') - putc('\r'); - s++; - } } static __inline__ void __arch_decomp_setup(unsigned long arch_id) diff --git a/include/asm-arm/arch-l7200/uncompress.h b/include/asm-arm/arch-l7200/uncompress.h index 1caa2b560f5..9fcd40aee3e 100644 --- a/include/asm-arm/arch-l7200/uncompress.h +++ b/include/asm-arm/arch-l7200/uncompress.h @@ -16,22 +16,17 @@ #define __raw_writeb(v,p) (*(volatile unsigned char *)(p) = (v)) #define __raw_readb(p) (*(volatile unsigned char *)(p)) -static __inline__ void putc(char c) +static inline void putc(int c) { while(__raw_readb(IO_UART + 0x18) & 0x20 || - __raw_readb(IO_UART + 0x18) & 0x08); + __raw_readb(IO_UART + 0x18) & 0x08) + barrier(); + __raw_writeb(c, IO_UART + 0x00); } -static void putstr(const char *s) +static inline void flush(void) { - while (*s) { - if (*s == 10) { /* If a LF, add CR */ - putc(10); - putc(13); - } - putc(*(s++)); - } } static __inline__ void arch_decomp_setup(void) diff --git a/include/asm-arm/arch-lh7a40x/uncompress.h b/include/asm-arm/arch-lh7a40x/uncompress.h index ec8ab67122f..f8053346f60 100644 --- a/include/asm-arm/arch-lh7a40x/uncompress.h +++ b/include/asm-arm/arch-lh7a40x/uncompress.h @@ -22,20 +22,15 @@ #define UART_STATUS (*(volatile unsigned long*) (UART2_PHYS + UART_R_STATUS)) #define UART_DATA (*(volatile unsigned long*) (UART2_PHYS + UART_R_DATA)) -static __inline__ void putc (char ch) +static inline void putc(int ch) { while (UART_STATUS & nTxRdy) - ; + barrier(); UART_DATA = ch; } -static void putstr (const char* sz) +static inline void flush(void) { - for (; *sz; ++sz) { - putc (*sz); - if (*sz == '\n') - putc ('\r'); - } } /* NULL functions; we don't presently need them */ diff --git a/include/asm-arm/arch-omap/uncompress.h b/include/asm-arm/arch-omap/uncompress.h index c718264affb..ca2c8bec82e 100644 --- a/include/asm-arm/arch-omap/uncompress.h +++ b/include/asm-arm/arch-omap/uncompress.h @@ -30,8 +30,7 @@ unsigned int system_rev; #define check_port(base, shift) ((base[UART_OMAP_MDR1 << shift] & 7) == 0) #define omap_get_id() ((*(volatile unsigned int *)(0xfffed404)) >> 12) & ID_MASK -static void -putstr(const char *s) +static void putc(int c) { volatile u8 * uart = 0; int shift = 2; @@ -69,16 +68,13 @@ putstr(const char *s) /* * Now, xmit each character */ - while (*s) { - while (!(uart[UART_LSR << shift] & UART_LSR_THRE)) - barrier(); - uart[UART_TX << shift] = *s; - if (*s++ == '\n') { - while (!(uart[UART_LSR << shift] & UART_LSR_THRE)) - barrier(); - uart[UART_TX << shift] = '\r'; - } - } + while (!(uart[UART_LSR << shift] & UART_LSR_THRE)) + barrier(); + uart[UART_TX << shift] = c; +} + +static inline void flush(void) +{ } /* diff --git a/include/asm-arm/arch-pxa/irqs.h b/include/asm-arm/arch-pxa/irqs.h index 05c4b702759..67af238a8f8 100644 --- a/include/asm-arm/arch-pxa/irqs.h +++ b/include/asm-arm/arch-pxa/irqs.h @@ -176,6 +176,7 @@ #elif defined(CONFIG_SHARP_LOCOMO) #define NR_IRQS (IRQ_LOCOMO_SPI_TEND + 1) #elif defined(CONFIG_ARCH_LUBBOCK) || \ + defined(CONFIG_MACH_LOGICPD_PXA270) || \ defined(CONFIG_MACH_MAINSTONE) #define NR_IRQS (IRQ_BOARD_END) #else @@ -196,6 +197,11 @@ #define LUBBOCK_USB_DISC_IRQ LUBBOCK_IRQ(6) /* usb disconnect */ #define LUBBOCK_LAST_IRQ LUBBOCK_IRQ(6) +#define LPD270_IRQ(x) (IRQ_BOARD_START + (x)) +#define LPD270_USBC_IRQ LPD270_IRQ(2) +#define LPD270_ETHERNET_IRQ LPD270_IRQ(3) +#define LPD270_AC97_IRQ LPD270_IRQ(4) + #define MAINSTONE_IRQ(x) (IRQ_BOARD_START + (x)) #define MAINSTONE_MMC_IRQ MAINSTONE_IRQ(0) #define MAINSTONE_USIM_IRQ MAINSTONE_IRQ(1) diff --git a/include/asm-arm/arch-pxa/lpd270.h b/include/asm-arm/arch-pxa/lpd270.h new file mode 100644 index 00000000000..501d240ac12 --- /dev/null +++ b/include/asm-arm/arch-pxa/lpd270.h @@ -0,0 +1,38 @@ +/* + * include/asm-arm/arch-pxa/lpd270.h + * + * Author: Lennert Buytenhek + * Created: Feb 10, 2006 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_LPD270_H +#define __ASM_ARCH_LPD270_H + +#define LPD270_CPLD_PHYS PXA_CS2_PHYS +#define LPD270_CPLD_VIRT 0xf0000000 +#define LPD270_CPLD_SIZE 0x00100000 + +#define LPD270_ETH_PHYS (PXA_CS2_PHYS + 0x01000000) + +/* CPLD registers */ +#define LPD270_CPLD_REG(x) ((unsigned long)(LPD270_CPLD_VIRT + (x))) +#define LPD270_CONTROL LPD270_CPLD_REG(0x00) +#define LPD270_PERIPHERAL0 LPD270_CPLD_REG(0x04) +#define LPD270_PERIPHERAL1 LPD270_CPLD_REG(0x08) +#define LPD270_CPLD_REVISION LPD270_CPLD_REG(0x14) +#define LPD270_EEPROM_SPI_ITF LPD270_CPLD_REG(0x20) +#define LPD270_MODE_PINS LPD270_CPLD_REG(0x24) +#define LPD270_EGPIO LPD270_CPLD_REG(0x30) +#define LPD270_INT_MASK LPD270_CPLD_REG(0x40) +#define LPD270_INT_STATUS LPD270_CPLD_REG(0x50) + +#define LPD270_INT_AC97 (1 << 4) /* AC'97 CODEC IRQ */ +#define LPD270_INT_ETHERNET (1 << 3) /* Ethernet controller IRQ */ +#define LPD270_INT_USBC (1 << 2) /* USB client cable detection IRQ */ + + +#endif diff --git a/include/asm-arm/arch-pxa/uncompress.h b/include/asm-arm/arch-pxa/uncompress.h index fe38090444e..178aa2e073a 100644 --- a/include/asm-arm/arch-pxa/uncompress.h +++ b/include/asm-arm/arch-pxa/uncompress.h @@ -17,23 +17,18 @@ #define UART FFUART -static __inline__ void putc(char c) +static inline void putc(char c) { - while (!(UART[5] & 0x20)); + while (!(UART[5] & 0x20)) + barrier(); UART[0] = c; } /* * This does not append a newline */ -static void putstr(const char *s) +static inline void flush(void) { - while (*s) { - putc(*s); - if (*s == '\n') - putc('\r'); - s++; - } } /* diff --git a/include/asm-arm/arch-realview/uncompress.h b/include/asm-arm/arch-realview/uncompress.h index b5e4d360665..f05631d7674 100644 --- a/include/asm-arm/arch-realview/uncompress.h +++ b/include/asm-arm/arch-realview/uncompress.h @@ -27,22 +27,16 @@ /* * This does not append a newline */ -static void putstr(const char *s) +static inline void putc(int c) { - while (*s) { - while (AMBA_UART_FR & (1 << 5)) - barrier(); - - AMBA_UART_DR = *s; + while (AMBA_UART_FR & (1 << 5)) + barrier(); - if (*s == '\n') { - while (AMBA_UART_FR & (1 << 5)) - barrier(); + AMBA_UART_DR = c; +} - AMBA_UART_DR = '\r'; - } - s++; - } +static inline void flush(void) +{ while (AMBA_UART_FR & (1 << 3)) barrier(); } diff --git a/include/asm-arm/arch-rpc/uncompress.h b/include/asm-arm/arch-rpc/uncompress.h index 43035fec64d..06231ede54e 100644 --- a/include/asm-arm/arch-rpc/uncompress.h +++ b/include/asm-arm/arch-rpc/uncompress.h @@ -67,31 +67,28 @@ extern __attribute__((pure)) struct param_struct *params(void); /* * This does not append a newline */ -static void putstr(const char *s) +static void putc(int c) { extern void ll_write_char(char *, char c, char white); int x,y; - unsigned char c; char *ptr; x = params->video_x; y = params->video_y; - while ( ( c = *(unsigned char *)s++ ) != '\0' ) { - if ( c == '\n' ) { + if (c == '\n') { + if (++y >= video_num_lines) + y--; + } else if (c == '\r') { + x = 0; + } else { + ptr = VIDMEM + ((y*video_num_columns*params->bytes_per_char_v+x)*bytes_per_char_h); + ll_write_char(ptr, c, white); + if (++x >= video_num_columns) { x = 0; if ( ++y >= video_num_lines ) { y--; } - } else { - ptr = VIDMEM + ((y*video_num_columns*params->bytes_per_char_v+x)*bytes_per_char_h); - ll_write_char(ptr, c, white); - if ( ++x >= video_num_columns ) { - x = 0; - if ( ++y >= video_num_lines ) { - y--; - } - } } } @@ -99,6 +96,10 @@ static void putstr(const char *s) params->video_y = y; } +static inline void flush(void) +{ +} + static void error(char *x); /* diff --git a/include/asm-arm/arch-s3c2410/uncompress.h b/include/asm-arm/arch-s3c2410/uncompress.h index 4367ec054b5..a6f6a0e44af 100644 --- a/include/asm-arm/arch-s3c2410/uncompress.h +++ b/include/asm-arm/arch-s3c2410/uncompress.h @@ -67,8 +67,7 @@ uart_rd(unsigned int reg) * waiting for tx to happen... */ -static void -putc(char ch) +static void putc(int ch) { int cpuid = S3C2410_GSTATUS1_2410; @@ -77,9 +76,6 @@ putc(char ch) cpuid &= S3C2410_GSTATUS1_IDMASK; #endif - if (ch == '\n') - putc('\r'); /* expand newline to \r\n */ - if (uart_rd(S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) { int level; @@ -101,19 +97,16 @@ putc(char ch) } else { /* not using fifos */ - while ((uart_rd(S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE) != S3C2410_UTRSTAT_TXE); + while ((uart_rd(S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE) != S3C2410_UTRSTAT_TXE) + barrier(); } /* write byte to transmission register */ uart_wr(S3C2410_UTXH, ch); } -static void -putstr(const char *ptr) +static inline void flush(void) { - for (; *ptr != '\0'; ptr++) { - putc(*ptr); - } } #define __raw_writel(d,ad) do { *((volatile unsigned int *)(ad)) = (d); } while(0) diff --git a/include/asm-arm/arch-sa1100/uncompress.h b/include/asm-arm/arch-sa1100/uncompress.h index 43453501ee6..2601a77a6dd 100644 --- a/include/asm-arm/arch-sa1100/uncompress.h +++ b/include/asm-arm/arch-sa1100/uncompress.h @@ -17,7 +17,7 @@ #define UART(x) (*(volatile unsigned long *)(serial_port + (x))) -static void putstr( const char *s ) +static void putc(int c) { unsigned long serial_port; @@ -31,19 +31,16 @@ static void putstr( const char *s ) return; } while (0); - for (; *s; s++) { - /* wait for space in the UART's transmitter */ - while (!(UART(UTSR1) & UTSR1_TNF)); + /* wait for space in the UART's transmitter */ + while (!(UART(UTSR1) & UTSR1_TNF)) + barrier(); - /* send the character out. */ - UART(UTDR) = *s; + /* send the character out. */ + UART(UTDR) = c; +} - /* if a LF, also do CR... */ - if (*s == 10) { - while (!(UART(UTSR1) & UTSR1_TNF)); - UART(UTDR) = 13; - } - } +static inline void flush(void) +{ } /* diff --git a/include/asm-arm/arch-shark/uncompress.h b/include/asm-arm/arch-shark/uncompress.h index 910a8e0a0ca..7eca6534f1b 100644 --- a/include/asm-arm/arch-shark/uncompress.h +++ b/include/asm-arm/arch-shark/uncompress.h @@ -9,7 +9,7 @@ #define SERIAL_BASE ((volatile unsigned char *)0x400003f8) -static __inline__ void putc(char c) +static inline void putc(int c) { int t; @@ -18,17 +18,8 @@ static __inline__ void putc(char c) while (t--); } -/* - * This does not append a newline - */ -static void putstr(const char *s) +static inline void flush(void) { - while (*s) { - putc(*s); - if (*s == '\n') - putc('\r'); - s++; - } } #ifdef DEBUG diff --git a/include/asm-arm/arch-versatile/uncompress.h b/include/asm-arm/arch-versatile/uncompress.h index 2f57499c7b9..7215133d051 100644 --- a/include/asm-arm/arch-versatile/uncompress.h +++ b/include/asm-arm/arch-versatile/uncompress.h @@ -25,22 +25,16 @@ /* * This does not append a newline */ -static void putstr(const char *s) +static inline void putc(int c) { - while (*s) { - while (AMBA_UART_FR & (1 << 5)) - barrier(); - - AMBA_UART_DR = *s; + while (AMBA_UART_FR & (1 << 5)) + barrier(); - if (*s == '\n') { - while (AMBA_UART_FR & (1 << 5)) - barrier(); + AMBA_UART_DR = c; +} - AMBA_UART_DR = '\r'; - } - s++; - } +static inline void flush(void) +{ while (AMBA_UART_FR & (1 << 3)) barrier(); } diff --git a/include/asm-arm/assembler.h b/include/asm-arm/assembler.h index f31ac92b6c7..d53bafa9bf1 100644 --- a/include/asm-arm/assembler.h +++ b/include/asm-arm/assembler.h @@ -80,16 +80,33 @@ instr regs /* - * Save the current IRQ state and disable IRQs. Note that this macro - * assumes FIQs are enabled, and that the processor is in SVC mode. + * Enable and disable interrupts */ - .macro save_and_disable_irqs, oldcpsr - mrs \oldcpsr, cpsr #if __LINUX_ARM_ARCH__ >= 6 + .macro disable_irq cpsid i + .endm + + .macro enable_irq + cpsie i + .endm #else - msr cpsr_c, #PSR_I_BIT | MODE_SVC + .macro disable_irq + msr cpsr_c, #PSR_I_BIT | SVC_MODE + .endm + + .macro enable_irq + msr cpsr_c, #SVC_MODE + .endm #endif + +/* + * Save the current IRQ state and disable IRQs. Note that this macro + * assumes FIQs are enabled, and that the processor is in SVC mode. + */ + .macro save_and_disable_irqs, oldcpsr + mrs \oldcpsr, cpsr + disable_irq .endm /* diff --git a/include/asm-arm/bitops.h b/include/asm-arm/bitops.h index d02de721ecc..0ac54b1a8ba 100644 --- a/include/asm-arm/bitops.h +++ b/include/asm-arm/bitops.h @@ -117,65 +117,7 @@ ____atomic_test_and_change_bit(unsigned int bit, volatile unsigned long *p) return res & mask; } -/* - * Now the non-atomic variants. We let the compiler handle all - * optimisations for these. These are all _native_ endian. - */ -static inline void __set_bit(int nr, volatile unsigned long *p) -{ - p[nr >> 5] |= (1UL << (nr & 31)); -} - -static inline void __clear_bit(int nr, volatile unsigned long *p) -{ - p[nr >> 5] &= ~(1UL << (nr & 31)); -} - -static inline void __change_bit(int nr, volatile unsigned long *p) -{ - p[nr >> 5] ^= (1UL << (nr & 31)); -} - -static inline int __test_and_set_bit(int nr, volatile unsigned long *p) -{ - unsigned long oldval, mask = 1UL << (nr & 31); - - p += nr >> 5; - - oldval = *p; - *p = oldval | mask; - return oldval & mask; -} - -static inline int __test_and_clear_bit(int nr, volatile unsigned long *p) -{ - unsigned long oldval, mask = 1UL << (nr & 31); - - p += nr >> 5; - - oldval = *p; - *p = oldval & ~mask; - return oldval & mask; -} - -static inline int __test_and_change_bit(int nr, volatile unsigned long *p) -{ - unsigned long oldval, mask = 1UL << (nr & 31); - - p += nr >> 5; - - oldval = *p; - *p = oldval ^ mask; - return oldval & mask; -} - -/* - * This routine doesn't need to be atomic. - */ -static inline int __test_bit(int nr, const volatile unsigned long * p) -{ - return (p[nr >> 5] >> (nr & 31)) & 1UL; -} +#include <asm-generic/bitops/non-atomic.h> /* * A note about Endian-ness. @@ -261,7 +203,6 @@ extern int _find_next_bit_be(const unsigned long *p, int size, int offset); #define test_and_set_bit(nr,p) ATOMIC_BITOP_LE(test_and_set_bit,nr,p) #define test_and_clear_bit(nr,p) ATOMIC_BITOP_LE(test_and_clear_bit,nr,p) #define test_and_change_bit(nr,p) ATOMIC_BITOP_LE(test_and_change_bit,nr,p) -#define test_bit(nr,p) __test_bit(nr,p) #define find_first_zero_bit(p,sz) _find_first_zero_bit_le(p,sz) #define find_next_zero_bit(p,sz,off) _find_next_zero_bit_le(p,sz,off) #define find_first_bit(p,sz) _find_first_bit_le(p,sz) @@ -280,7 +221,6 @@ extern int _find_next_bit_be(const unsigned long *p, int size, int offset); #define test_and_set_bit(nr,p) ATOMIC_BITOP_BE(test_and_set_bit,nr,p) #define test_and_clear_bit(nr,p) ATOMIC_BITOP_BE(test_and_clear_bit,nr,p) #define test_and_change_bit(nr,p) ATOMIC_BITOP_BE(test_and_change_bit,nr,p) -#define test_bit(nr,p) __test_bit(nr,p) #define find_first_zero_bit(p,sz) _find_first_zero_bit_be(p,sz) #define find_next_zero_bit(p,sz,off) _find_next_zero_bit_be(p,sz,off) #define find_first_bit(p,sz) _find_first_bit_be(p,sz) @@ -292,57 +232,41 @@ extern int _find_next_bit_be(const unsigned long *p, int size, int offset); #if __LINUX_ARM_ARCH__ < 5 -/* - * ffz = Find First Zero in word. Undefined if no zero exists, - * so code should check against ~0UL first.. - */ -static inline unsigned long ffz(unsigned long word) -{ - int k; - - word = ~word; - k = 31; - if (word & 0x0000ffff) { k -= 16; word <<= 16; } - if (word & 0x00ff0000) { k -= 8; word <<= 8; } - if (word & 0x0f000000) { k -= 4; word <<= 4; } - if (word & 0x30000000) { k -= 2; word <<= 2; } - if (word & 0x40000000) { k -= 1; } - return k; -} - -/* - * ffz = Find First Zero in word. Undefined if no zero exists, - * so code should check against ~0UL first.. - */ -static inline unsigned long __ffs(unsigned long word) -{ - int k; - - k = 31; - if (word & 0x0000ffff) { k -= 16; word <<= 16; } - if (word & 0x00ff0000) { k -= 8; word <<= 8; } - if (word & 0x0f000000) { k -= 4; word <<= 4; } - if (word & 0x30000000) { k -= 2; word <<= 2; } - if (word & 0x40000000) { k -= 1; } - return k; -} - -/* - * fls: find last bit set. - */ +#include <asm-generic/bitops/ffz.h> +#include <asm-generic/bitops/__ffs.h> +#include <asm-generic/bitops/fls.h> +#include <asm-generic/bitops/ffs.h> -#define fls(x) generic_fls(x) -#define fls64(x) generic_fls64(x) - -/* - * ffs: find first bit set. This is defined the same way as - * the libc and compiler builtin ffs routines, therefore - * differs in spirit from the above ffz (man ffs). - */ +#else -#define ffs(x) generic_ffs(x) +static inline int constant_fls(int x) +{ + int r = 32; -#else + if (!x) + return 0; + if (!(x & 0xffff0000u)) { + x <<= 16; + r -= 16; + } + if (!(x & 0xff000000u)) { + x <<= 8; + r -= 8; + } + if (!(x & 0xf0000000u)) { + x <<= 4; + r -= 4; + } + if (!(x & 0xc0000000u)) { + x <<= 2; + r -= 2; + } + if (!(x & 0x80000000u)) { + x <<= 1; + r -= 1; + } + return r; +} /* * On ARMv5 and above those functions can be implemented around @@ -350,39 +274,18 @@ static inline unsigned long __ffs(unsigned long word) */ #define fls(x) \ - ( __builtin_constant_p(x) ? generic_fls(x) : \ + ( __builtin_constant_p(x) ? constant_fls(x) : \ ({ int __r; asm("clz\t%0, %1" : "=r"(__r) : "r"(x) : "cc"); 32-__r; }) ) -#define fls64(x) generic_fls64(x) #define ffs(x) ({ unsigned long __t = (x); fls(__t & -__t); }) #define __ffs(x) (ffs(x) - 1) #define ffz(x) __ffs( ~(x) ) #endif -/* - * Find first bit set in a 168-bit bitmap, where the first - * 128 bits are unlikely to be set. - */ -static inline int sched_find_first_bit(const unsigned long *b) -{ - unsigned long v; - unsigned int off; - - for (off = 0; v = b[off], off < 4; off++) { - if (unlikely(v)) - break; - } - return __ffs(v) + off * 32; -} - -/* - * hweightN: returns the hamming weight (i.e. the number - * of bits set) of a N-bit word - */ +#include <asm-generic/bitops/fls64.h> -#define hweight32(x) generic_hweight32(x) -#define hweight16(x) generic_hweight16(x) -#define hweight8(x) generic_hweight8(x) +#include <asm-generic/bitops/sched.h> +#include <asm-generic/bitops/hweight.h> /* * Ext2 is defined to use little-endian byte ordering. @@ -397,7 +300,7 @@ static inline int sched_find_first_bit(const unsigned long *b) #define ext2_clear_bit_atomic(lock,nr,p) \ test_and_clear_bit(WORD_BITOFF_TO_LE(nr), (unsigned long *)(p)) #define ext2_test_bit(nr,p) \ - __test_bit(WORD_BITOFF_TO_LE(nr), (unsigned long *)(p)) + test_bit(WORD_BITOFF_TO_LE(nr), (unsigned long *)(p)) #define ext2_find_first_zero_bit(p,sz) \ _find_first_zero_bit_le(p,sz) #define ext2_find_next_zero_bit(p,sz,off) \ @@ -410,7 +313,7 @@ static inline int sched_find_first_bit(const unsigned long *b) #define minix_set_bit(nr,p) \ __set_bit(WORD_BITOFF_TO_LE(nr), (unsigned long *)(p)) #define minix_test_bit(nr,p) \ - __test_bit(WORD_BITOFF_TO_LE(nr), (unsigned long *)(p)) + test_bit(WORD_BITOFF_TO_LE(nr), (unsigned long *)(p)) #define minix_test_and_set_bit(nr,p) \ __test_and_set_bit(WORD_BITOFF_TO_LE(nr), (unsigned long *)(p)) #define minix_test_and_clear_bit(nr,p) \ diff --git a/include/asm-arm/cacheflush.h b/include/asm-arm/cacheflush.h index 09e19a783a5..746be56b1b7 100644 --- a/include/asm-arm/cacheflush.h +++ b/include/asm-arm/cacheflush.h @@ -71,6 +71,14 @@ # endif #endif +#if defined(CONFIG_CPU_XSC3) +# ifdef _CACHE +# define MULTI_CACHE 1 +# else +# define _CACHE xsc3 +# endif +#endif + #if defined(CONFIG_CPU_V6) //# ifdef _CACHE # define MULTI_CACHE 1 diff --git a/include/asm-arm/domain.h b/include/asm-arm/domain.h index da1d960387d..f8ea2de4848 100644 --- a/include/asm-arm/domain.h +++ b/include/asm-arm/domain.h @@ -16,11 +16,29 @@ * DOMAIN_IO - domain 2 includes all IO only * DOMAIN_USER - domain 1 includes all user memory only * DOMAIN_KERNEL - domain 0 includes all kernel memory only + * + * The domain numbering depends on whether we support 36 physical + * address for I/O or not. Addresses above the 32 bit boundary can + * only be mapped using supersections and supersections can only + * be set for domain 0. We could just default to DOMAIN_IO as zero, + * but there may be systems with supersection support and no 36-bit + * addressing. In such cases, we want to map system memory with + * supersections to reduce TLB misses and footprint. + * + * 36-bit addressing and supersections are only available on + * CPUs based on ARMv6+ or the Intel XSC3 core. */ +#ifndef CONFIG_IO_36 #define DOMAIN_KERNEL 0 #define DOMAIN_TABLE 0 #define DOMAIN_USER 1 #define DOMAIN_IO 2 +#else +#define DOMAIN_KERNEL 2 +#define DOMAIN_TABLE 2 +#define DOMAIN_USER 1 +#define DOMAIN_IO 0 +#endif /* * Domain types diff --git a/include/asm-arm/memory.h b/include/asm-arm/memory.h index b4e1146ab68..afa5c3ea077 100644 --- a/include/asm-arm/memory.h +++ b/include/asm-arm/memory.h @@ -172,9 +172,7 @@ static inline __deprecated void *bus_to_virt(unsigned long x) * virt_addr_valid(k) indicates whether a virtual address is valid */ #ifndef CONFIG_DISCONTIGMEM - -#define page_to_pfn(page) (((page) - mem_map) + PHYS_PFN_OFFSET) -#define pfn_to_page(pfn) ((mem_map + (pfn)) - PHYS_PFN_OFFSET) +#define ARCH_PFN_OFFSET (PHYS_PFN_OFFSET) #define pfn_valid(pfn) ((pfn) >= PHYS_PFN_OFFSET && (pfn) < (PHYS_PFN_OFFSET + max_mapnr)) #define virt_to_page(kaddr) (pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)) @@ -189,13 +187,8 @@ static inline __deprecated void *bus_to_virt(unsigned long x) * around in memory. */ #include <linux/numa.h> - -#define page_to_pfn(page) \ - (( (page) - page_zone(page)->zone_mem_map) \ - + page_zone(page)->zone_start_pfn) - -#define pfn_to_page(pfn) \ - (PFN_TO_MAPBASE(pfn) + LOCAL_MAP_NR((pfn) << PAGE_SHIFT)) +#define arch_pfn_to_nid(pfn) (PFN_TO_NID(pfn)) +#define arch_local_page_offset(pfn, nid) (LOCAL_MAP_NR((pfn) << PAGE_OFFSET)) #define pfn_valid(pfn) \ ({ \ @@ -243,4 +236,6 @@ static inline __deprecated void *bus_to_virt(unsigned long x) #endif +#include <asm-generic/memory_model.h> + #endif diff --git a/include/asm-arm/page.h b/include/asm-arm/page.h index 416320d9541..a404d2bf0c6 100644 --- a/include/asm-arm/page.h +++ b/include/asm-arm/page.h @@ -40,6 +40,7 @@ * v4wb - ARMv4 with writeback cache, without minicache * v4_mc - ARMv4 with minicache * xscale - Xscale + * xsc3 - XScalev3 */ #undef _USER #undef MULTI_USER @@ -84,6 +85,14 @@ # endif #endif +#ifdef CONFIG_CPU_XSC3 +# ifdef _USER +# define MULTI_USER 1 +# else +# define _USER xsc3_mc +# endif +#endif + #ifdef CONFIG_CPU_COPY_V6 # define MULTI_USER 1 #endif diff --git a/include/asm-arm/pgalloc.h b/include/asm-arm/pgalloc.h index bc18ff40518..c4ac2e67768 100644 --- a/include/asm-arm/pgalloc.h +++ b/include/asm-arm/pgalloc.h @@ -10,10 +10,15 @@ #ifndef _ASMARM_PGALLOC_H #define _ASMARM_PGALLOC_H +#include <asm/domain.h> +#include <asm/pgtable-hwdef.h> #include <asm/processor.h> #include <asm/cacheflush.h> #include <asm/tlbflush.h> +#define _PAGE_USER_TABLE (PMD_TYPE_TABLE | PMD_BIT4 | PMD_DOMAIN(DOMAIN_USER)) +#define _PAGE_KERNEL_TABLE (PMD_TYPE_TABLE | PMD_BIT4 | PMD_DOMAIN(DOMAIN_KERNEL)) + /* * Since we have only two-level page tables, these are trivial */ diff --git a/include/asm-arm/pgtable-hwdef.h b/include/asm-arm/pgtable-hwdef.h new file mode 100644 index 00000000000..1d033495cc7 --- /dev/null +++ b/include/asm-arm/pgtable-hwdef.h @@ -0,0 +1,88 @@ +/* + * linux/include/asm-arm/pgtable-hwdef.h + * + * Copyright (C) 1995-2002 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef _ASMARM_PGTABLE_HWDEF_H +#define _ASMARM_PGTABLE_HWDEF_H + +/* + * Hardware page table definitions. + * + * + Level 1 descriptor (PMD) + * - common + */ +#define PMD_TYPE_MASK (3 << 0) +#define PMD_TYPE_FAULT (0 << 0) +#define PMD_TYPE_TABLE (1 << 0) +#define PMD_TYPE_SECT (2 << 0) +#define PMD_BIT4 (1 << 4) +#define PMD_DOMAIN(x) ((x) << 5) +#define PMD_PROTECTION (1 << 9) /* v5 */ +/* + * - section + */ +#define PMD_SECT_BUFFERABLE (1 << 2) +#define PMD_SECT_CACHEABLE (1 << 3) +#define PMD_SECT_AP_WRITE (1 << 10) +#define PMD_SECT_AP_READ (1 << 11) +#define PMD_SECT_TEX(x) ((x) << 12) /* v5 */ +#define PMD_SECT_APX (1 << 15) /* v6 */ +#define PMD_SECT_S (1 << 16) /* v6 */ +#define PMD_SECT_nG (1 << 17) /* v6 */ +#define PMD_SECT_SUPER (1 << 18) /* v6 */ + +#define PMD_SECT_UNCACHED (0) +#define PMD_SECT_BUFFERED (PMD_SECT_BUFFERABLE) +#define PMD_SECT_WT (PMD_SECT_CACHEABLE) +#define PMD_SECT_WB (PMD_SECT_CACHEABLE | PMD_SECT_BUFFERABLE) +#define PMD_SECT_MINICACHE (PMD_SECT_TEX(1) | PMD_SECT_CACHEABLE) +#define PMD_SECT_WBWA (PMD_SECT_TEX(1) | PMD_SECT_CACHEABLE | PMD_SECT_BUFFERABLE) +#define PMD_SECT_NONSHARED_DEV (PMD_SECT_TEX(2)) + +/* + * - coarse table (not used) + */ + +/* + * + Level 2 descriptor (PTE) + * - common + */ +#define PTE_TYPE_MASK (3 << 0) +#define PTE_TYPE_FAULT (0 << 0) +#define PTE_TYPE_LARGE (1 << 0) +#define PTE_TYPE_SMALL (2 << 0) +#define PTE_TYPE_EXT (3 << 0) /* v5 */ +#define PTE_BUFFERABLE (1 << 2) +#define PTE_CACHEABLE (1 << 3) + +/* + * - extended small page/tiny page + */ +#define PTE_EXT_XN (1 << 0) /* v6 */ +#define PTE_EXT_AP_MASK (3 << 4) +#define PTE_EXT_AP0 (1 << 4) +#define PTE_EXT_AP1 (2 << 4) +#define PTE_EXT_AP_UNO_SRO (0 << 4) +#define PTE_EXT_AP_UNO_SRW (PTE_EXT_AP0) +#define PTE_EXT_AP_URO_SRW (PTE_EXT_AP1) +#define PTE_EXT_AP_URW_SRW (PTE_EXT_AP1|PTE_EXT_AP0) +#define PTE_EXT_TEX(x) ((x) << 6) /* v5 */ +#define PTE_EXT_APX (1 << 9) /* v6 */ +#define PTE_EXT_SHARED (1 << 10) /* v6 */ +#define PTE_EXT_NG (1 << 11) /* v6 */ + +/* + * - small page + */ +#define PTE_SMALL_AP_MASK (0xff << 4) +#define PTE_SMALL_AP_UNO_SRO (0x00 << 4) +#define PTE_SMALL_AP_UNO_SRW (0x55 << 4) +#define PTE_SMALL_AP_URO_SRW (0xaa << 4) +#define PTE_SMALL_AP_URW_SRW (0xff << 4) + +#endif diff --git a/include/asm-arm/pgtable.h b/include/asm-arm/pgtable.h index 70e00d08345..e595ae24efe 100644 --- a/include/asm-arm/pgtable.h +++ b/include/asm-arm/pgtable.h @@ -137,81 +137,6 @@ extern void __pgd_error(const char *file, int line, unsigned long val); #define SUPERSECTION_MASK (~(SUPERSECTION_SIZE-1)) /* - * Hardware page table definitions. - * - * + Level 1 descriptor (PMD) - * - common - */ -#define PMD_TYPE_MASK (3 << 0) -#define PMD_TYPE_FAULT (0 << 0) -#define PMD_TYPE_TABLE (1 << 0) -#define PMD_TYPE_SECT (2 << 0) -#define PMD_BIT4 (1 << 4) -#define PMD_DOMAIN(x) ((x) << 5) -#define PMD_PROTECTION (1 << 9) /* v5 */ -/* - * - section - */ -#define PMD_SECT_BUFFERABLE (1 << 2) -#define PMD_SECT_CACHEABLE (1 << 3) -#define PMD_SECT_AP_WRITE (1 << 10) -#define PMD_SECT_AP_READ (1 << 11) -#define PMD_SECT_TEX(x) ((x) << 12) /* v5 */ -#define PMD_SECT_APX (1 << 15) /* v6 */ -#define PMD_SECT_S (1 << 16) /* v6 */ -#define PMD_SECT_nG (1 << 17) /* v6 */ -#define PMD_SECT_SUPER (1 << 18) /* v6 */ - -#define PMD_SECT_UNCACHED (0) -#define PMD_SECT_BUFFERED (PMD_SECT_BUFFERABLE) -#define PMD_SECT_WT (PMD_SECT_CACHEABLE) -#define PMD_SECT_WB (PMD_SECT_CACHEABLE | PMD_SECT_BUFFERABLE) -#define PMD_SECT_MINICACHE (PMD_SECT_TEX(1) | PMD_SECT_CACHEABLE) -#define PMD_SECT_WBWA (PMD_SECT_TEX(1) | PMD_SECT_CACHEABLE | PMD_SECT_BUFFERABLE) -#define PMD_SECT_NONSHARED_DEV (PMD_SECT_TEX(2)) - -/* - * - coarse table (not used) - */ - -/* - * + Level 2 descriptor (PTE) - * - common - */ -#define PTE_TYPE_MASK (3 << 0) -#define PTE_TYPE_FAULT (0 << 0) -#define PTE_TYPE_LARGE (1 << 0) -#define PTE_TYPE_SMALL (2 << 0) -#define PTE_TYPE_EXT (3 << 0) /* v5 */ -#define PTE_BUFFERABLE (1 << 2) -#define PTE_CACHEABLE (1 << 3) - -/* - * - extended small page/tiny page - */ -#define PTE_EXT_XN (1 << 0) /* v6 */ -#define PTE_EXT_AP_MASK (3 << 4) -#define PTE_EXT_AP0 (1 << 4) -#define PTE_EXT_AP1 (2 << 4) -#define PTE_EXT_AP_UNO_SRO (0 << 4) -#define PTE_EXT_AP_UNO_SRW (PTE_EXT_AP0) -#define PTE_EXT_AP_URO_SRW (PTE_EXT_AP1) -#define PTE_EXT_AP_URW_SRW (PTE_EXT_AP1|PTE_EXT_AP0) -#define PTE_EXT_TEX(x) ((x) << 6) /* v5 */ -#define PTE_EXT_APX (1 << 9) /* v6 */ -#define PTE_EXT_SHARED (1 << 10) /* v6 */ -#define PTE_EXT_NG (1 << 11) /* v6 */ - -/* - * - small page - */ -#define PTE_SMALL_AP_MASK (0xff << 4) -#define PTE_SMALL_AP_UNO_SRO (0x00 << 4) -#define PTE_SMALL_AP_UNO_SRW (0x55 << 4) -#define PTE_SMALL_AP_URO_SRW (0xaa << 4) -#define PTE_SMALL_AP_URW_SRW (0xff << 4) - -/* * "Linux" PTE definitions. * * We keep two sets of PTEs - the hardware and the linux version. @@ -236,11 +161,6 @@ extern void __pgd_error(const char *file, int line, unsigned long val); #ifndef __ASSEMBLY__ -#include <asm/domain.h> - -#define _PAGE_USER_TABLE (PMD_TYPE_TABLE | PMD_BIT4 | PMD_DOMAIN(DOMAIN_USER)) -#define _PAGE_KERNEL_TABLE (PMD_TYPE_TABLE | PMD_BIT4 | PMD_DOMAIN(DOMAIN_KERNEL)) - /* * The following macros handle the cache and bufferable bits... */ diff --git a/include/asm-arm/poll.h b/include/asm-arm/poll.h index 2744ca831f5..5030b2b232a 100644 --- a/include/asm-arm/poll.h +++ b/include/asm-arm/poll.h @@ -16,6 +16,7 @@ #define POLLWRBAND 0x0200 #define POLLMSG 0x0400 #define POLLREMOVE 0x1000 +#define POLLRDHUP 0x2000 struct pollfd { int fd; diff --git a/include/asm-arm/proc-fns.h b/include/asm-arm/proc-fns.h index 7bef2bf6be5..106045edb86 100644 --- a/include/asm-arm/proc-fns.h +++ b/include/asm-arm/proc-fns.h @@ -138,6 +138,14 @@ # define CPU_NAME cpu_xscale # endif # endif +# ifdef CONFIG_CPU_XSC3 +# ifdef CPU_NAME +# undef MULTI_CPU +# define MULTI_CPU +# else +# define CPU_NAME cpu_xsc3 +# endif +# endif # ifdef CONFIG_CPU_V6 # ifdef CPU_NAME # undef MULTI_CPU diff --git a/include/asm-arm/rtc.h b/include/asm-arm/rtc.h index 370dfe77589..1a5c9232a91 100644 --- a/include/asm-arm/rtc.h +++ b/include/asm-arm/rtc.h @@ -25,9 +25,6 @@ struct rtc_ops { int (*proc)(char *buf); }; -void rtc_time_to_tm(unsigned long, struct rtc_time *); -int rtc_tm_to_time(struct rtc_time *, unsigned long *); -int rtc_valid_tm(struct rtc_time *); void rtc_next_alarm_time(struct rtc_time *, struct rtc_time *, struct rtc_time *); void rtc_update(unsigned long, unsigned long); int register_rtc(struct rtc_ops *); diff --git a/include/asm-arm/system.h b/include/asm-arm/system.h index ec91d1ff032..95b3abf4851 100644 --- a/include/asm-arm/system.h +++ b/include/asm-arm/system.h @@ -108,6 +108,25 @@ extern void __show_regs(struct pt_regs *); extern int cpu_architecture(void); extern void cpu_init(void); +/* + * Intel's XScale3 core supports some v6 features (supersections, L2) + * but advertises itself as v5 as it does not support the v6 ISA. For + * this reason, we need a way to explicitly test for this type of CPU. + */ +#ifndef CONFIG_CPU_XSC3 +#define cpu_is_xsc3() 0 +#else +static inline int cpu_is_xsc3(void) +{ + extern unsigned int processor_id; + + if ((processor_id & 0xffffe000) == 0x69056000) + return 1; + + return 0; +} +#endif + #define set_cr(x) \ __asm__ __volatile__( \ "mcr p15, 0, %0, c1, c0, 0 @ set CR" \ diff --git a/include/asm-arm/tlb.h b/include/asm-arm/tlb.h index f49bfb78c22..cb740025d41 100644 --- a/include/asm-arm/tlb.h +++ b/include/asm-arm/tlb.h @@ -19,6 +19,14 @@ #include <asm/cacheflush.h> #include <asm/tlbflush.h> + +#ifndef CONFIG_MMU + +#include <linux/pagemap.h> +#include <asm-generic/tlb.h> + +#else /* !CONFIG_MMU */ + #include <asm/pgalloc.h> /* @@ -82,4 +90,5 @@ tlb_end_vma(struct mmu_gather *tlb, struct vm_area_struct *vma) #define tlb_migrate_finish(mm) do { } while (0) +#endif /* CONFIG_MMU */ #endif diff --git a/include/asm-arm/tlbflush.h b/include/asm-arm/tlbflush.h index 0c2acc944a0..728992451dd 100644 --- a/include/asm-arm/tlbflush.h +++ b/include/asm-arm/tlbflush.h @@ -11,6 +11,13 @@ #define _ASMARM_TLBFLUSH_H #include <linux/config.h> + +#ifndef CONFIG_MMU + +#define tlb_flush(tlb) ((void) tlb) + +#else /* CONFIG_MMU */ + #include <asm/glue.h> #define TLB_V3_PAGE (1 << 0) @@ -423,4 +430,6 @@ extern void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte #endif +#endif /* CONFIG_MMU */ + #endif |