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path: root/arch/mips/mm/c-r4k.c
AgeCommit message (Expand)Author
2005-10-29Rename page argument of flush_cache_page to something more descriptive.Ralf Baechle
2005-10-29Cleanup the mess in cpu_cache_init.Ralf Baechle
2005-10-29Add/Fix missing bit of R4600 hit cacheop workaround.Thiemo Seufer
2005-10-29Minor code cleanup.Thiemo Seufer
2005-10-29More .set push/pop.Thiemo Seufer
2005-10-29Let r4600 PRID detection match only legacy CPUs, cleanups.Thiemo Seufer
2005-10-29Avoid SMP cacheflushes. This is a minor optimization of startup butRalf Baechle
2005-10-29More AP / SP bits for the 34K, the Malta bits and things. Still wantsRalf Baechle
2005-10-29Mark a few variables __read_mostly.Ralf Baechle
2005-10-29MIPS R2 instruction hazard handling.Ralf Baechle
2005-10-29Better interface to run uncached cache setup code.Thiemo Seufer
2005-10-29Sparseify MIPS.Ralf Baechle
2005-10-29Base Au1200 2.6 support.Pete Popov
2005-10-29Use intermediate variable.Thiemo Seufer
2005-10-29Moves a test which determines if we actually need to perform aRalf Baechle
2005-10-29Update MIPS to use the 4-level pagetable code thereby getting rid ofRalf Baechle
2005-10-2925Kf is also physically indexed.Ralf Baechle
2005-10-2920Kc and SB1 don't suffer from aliases.Ralf Baechle
2005-10-29Move missplaced code line to the right place.Ralf Baechle
2005-10-29Use hardware mechanism to deal with cache aliases in the 24K.Ralf Baechle
2005-10-29Remove old wrong bits of cache code.Ralf Baechle
2005-09-05[PATCH] mips: nuke trailing whitespaceRalf Baechle
2005-09-05[PATCH] mips: clean up 32/64-bit configurationRalf Baechle
2005-04-16Linux-2.6.12-rc2Linus Torvalds
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