1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
|
/*
* arch/arm/plat-orion/irq.c
*
* Marvell Orion SoC IRQ handling.
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <asm/plat-orion/irq.h>
static void orion_irq_mask(u32 irq)
{
void __iomem *maskaddr = get_irq_chip_data(irq);
u32 mask;
mask = readl(maskaddr);
mask &= ~(1 << (irq & 31));
writel(mask, maskaddr);
}
static void orion_irq_unmask(u32 irq)
{
void __iomem *maskaddr = get_irq_chip_data(irq);
u32 mask;
mask = readl(maskaddr);
mask |= 1 << (irq & 31);
writel(mask, maskaddr);
}
static struct irq_chip orion_irq_chip = {
.name = "orion_irq",
.mask = orion_irq_mask,
.mask_ack = orion_irq_mask,
.unmask = orion_irq_unmask,
};
void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr)
{
unsigned int i;
/*
* Mask all interrupts initially.
*/
writel(0, maskaddr);
/*
* Register IRQ sources.
*/
for (i = 0; i < 32; i++) {
unsigned int irq = irq_start + i;
set_irq_chip(irq, &orion_irq_chip);
set_irq_chip_data(irq, maskaddr);
set_irq_handler(irq, handle_level_irq);
irq_desc[irq].status |= IRQ_LEVEL;
set_irq_flags(irq, IRQF_VALID);
}
}
|
